2 files changed, 122 insertions, 9 deletions
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index d3d4534e3c74..773e380b5fe8 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -57,12 +57,12 @@
        addi    reg,reg,(label)-_stext; /* virt addr of handler ... */
 #define EXCEPTION_PROLOG_1(area)                                \
-        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
        std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
        std     r10,area+EX_R10(r13);                                   \
        std     r11,area+EX_R11(r13);                                   \
        std     r12,area+EX_R12(r13);                                   \
-        mfspr   r9,SPRN_SPRG1;                                          \
+        mfspr   r9,SPRN_SPRG_SCRATCH0;                                  \
        std     r9,area+EX_R13(r13);                                    \
        mfcr    r9
@@ -144,7 +144,7 @@
        .globl label##_pSeries;                         \
 label##_pSeries:                                        \
        HMT_MEDIUM;                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 #define HSTD_EXCEPTION_PSERIES(n, label)                \
@@ -152,13 +152,13 @@ label##_pSeries:					\
        .globl label##_pSeries;                         \
 label##_pSeries:                                        \
        HMT_MEDIUM;                                     \
-        mtspr   SPRN_SPRG1,r20;         /* save r20 */  \
+        mtspr   SPRN_SPRG_SCRATCH0,r20; /* save r20 */  \
        mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
        mtspr   SPRN_SRR0,r20;                          \
        mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
        mtspr   SPRN_SRR1,r20;                          \
-        mfspr   r20,SPRN_SPRG1;         /* restore r20 */ \
+        mfspr   r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
@@ -167,15 +167,15 @@ label##_pSeries:					\
        .globl label##_pSeries;                                         \
 label##_pSeries:                                                        \
        HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
-        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
        std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
        std     r10,PACA_EXGEN+EX_R10(r13);                             \
        lbz     r10,PACASOFTIRQEN(r13);                                 \
        mfcr    r9;                                                     \
        cmpwi   r10,0;                                                  \
        beq     masked_interrupt;                                       \
-        mfspr   r10,SPRN_SPRG1;                                         \
+        mfspr   r10,SPRN_SPRG_SCRATCH0;                                 \
        std     r10,PACA_EXGEN+EX_R13(r13);                             \
        std     r11,PACA_EXGEN+EX_R11(r13);                             \
        std     r12,PACA_EXGEN+EX_R12(r13);                             \
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1170267736d3..a8179cc99ac4 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -646,6 +646,119 @@
 #endif
 /*
+ * SPRG usage:
+ *
+ * All 64-bit:
+ *      - SPRG3 stores PACA pointer
+ *
+ * 64-bit server:
+ *      - SPRG0 unused (reserved for HV on Power4)
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 scratch for exception vectors
+ *
+ * All 32-bit:
+ *      - SPRG3 current thread_info pointer
+ *        (virtual on BookE, physical on others)
+ *
+ * 32-bit classic:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 indicator that we are in RTAS
+ *      - SPRG4 (603 only) pseudo TLB LRU data
+ *
+ * 32-bit 40x:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 scratch for exception vectors
+ *      - SPRG4 scratch for exception vectors (not 403)
+ *      - SPRG5 scratch for exception vectors (not 403)
+ *      - SPRG6 scratch for exception vectors (not 403)
+ *      - SPRG7 scratch for exception vectors (not 403)
+ *
+ * 32-bit 440 and FSL BookE:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors (*)
+ *      - SPRG2 scratch for crit interrupts handler
+ *      - SPRG4 scratch for exception vectors
+ *      - SPRG5 scratch for exception vectors
+ *      - SPRG6 scratch for machine check handler
+ *      - SPRG7 scratch for exception vectors
+ *      - SPRG9 scratch for debug vectors (e500 only)
+ *
+ *      Additionally, BookE separates "read" and "write"
+ *      of those registers. That allows to use the userspace
+ *      readable variant for reads, which can avoid a fault
+ *      with KVM type virtualization.
+ *
+ *      (*) Under KVM, the host SPRG1 is used to point to
+ *      the current VCPU data structure
+ *
+ * 32-bit 8xx:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 apparently unused but initialized
+ *
+ */
+#ifdef CONFIG_PPC64
+#define SPRN_SPRG_PACA          SPRN_SPRG3
+#else
+#define SPRN_SPRG_THREAD        SPRN_SPRG3
+#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG2
+#endif
+#ifdef CONFIG_PPC_BOOK3S_32
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_RTAS          SPRN_SPRG2
+#define SPRN_SPRG_603_LRU       SPRN_SPRG4
+#endif
+#ifdef CONFIG_40x
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH2      SPRN_SPRG2
+#define SPRN_SPRG_SCRATCH3      SPRN_SPRG4
+#define SPRN_SPRG_SCRATCH4      SPRN_SPRG5
+#define SPRN_SPRG_SCRATCH5      SPRN_SPRG6
+#define SPRN_SPRG_SCRATCH6      SPRN_SPRG7
+#endif
+#ifdef CONFIG_BOOKE
+#define SPRN_SPRG_RSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_WSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_RSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_WSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_RSCRATCH2     SPRN_SPRG4R
+#define SPRN_SPRG_WSCRATCH2     SPRN_SPRG4W
+#define SPRN_SPRG_RSCRATCH3     SPRN_SPRG5R
+#define SPRN_SPRG_WSCRATCH3     SPRN_SPRG5W
+#define SPRN_SPRG_RSCRATCH_MC   SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_MC   SPRN_SPRG6W
+#define SPRN_SPRG_RSCRATCH4     SPRN_SPRG7R
+#define SPRN_SPRG_WSCRATCH4     SPRN_SPRG7W
+#ifdef CONFIG_E200
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG6W
+#else
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG9
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG9
+#endif
+#define SPRN_SPRG_RVCPU         SPRN_SPRG1
+#define SPRN_SPRG_WVCPU         SPRN_SPRG1
+#endif
+#ifdef CONFIG_8xx
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#endif
+/*
 * An mtfsf instruction with the L bit set. On CPUs that support this a
 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
 *

diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index d3d4534e3c74..773e380b5fe8 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h
@@ -57,12 +57,12 @@
57	addi reg,reg,(label)-_stext; /* virt addr of handler ... */	57	addi reg,reg,(label)-_stext; /* virt addr of handler ... */
58		58
59	#define EXCEPTION_PROLOG_1(area) \	59	#define EXCEPTION_PROLOG_1(area) \
60	mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \	60	mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
61	std r9,area+EX_R9(r13); /* save r9 - r12 */ \	61	std r9,area+EX_R9(r13); /* save r9 - r12 */ \
62	std r10,area+EX_R10(r13); \	62	std r10,area+EX_R10(r13); \
63	std r11,area+EX_R11(r13); \	63	std r11,area+EX_R11(r13); \
64	std r12,area+EX_R12(r13); \	64	std r12,area+EX_R12(r13); \
65	mfspr r9,SPRN_SPRG1; \	65	mfspr r9,SPRN_SPRG_SCRATCH0; \
66	std r9,area+EX_R13(r13); \	66	std r9,area+EX_R13(r13); \
67	mfcr r9	67	mfcr r9
68		68
@@ -144,7 +144,7 @@
144	.globl label##_pSeries; \	144	.globl label##_pSeries; \
145	label##_pSeries: \	145	label##_pSeries: \
146	HMT_MEDIUM; \	146	HMT_MEDIUM; \
147	mtspr SPRN_SPRG1,r13; /* save r13 */ \	147	mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
148	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)	148	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
149		149
150	#define HSTD_EXCEPTION_PSERIES(n, label) \	150	#define HSTD_EXCEPTION_PSERIES(n, label) \
@@ -152,13 +152,13 @@ label##_pSeries: \
152	.globl label##_pSeries; \	152	.globl label##_pSeries; \
153	label##_pSeries: \	153	label##_pSeries: \
154	HMT_MEDIUM; \	154	HMT_MEDIUM; \
155	mtspr SPRN_SPRG1,r20; /* save r20 */ \	155	mtspr SPRN_SPRG_SCRATCH0,r20; /* save r20 */ \
156	mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \	156	mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
157	mtspr SPRN_SRR0,r20; \	157	mtspr SPRN_SRR0,r20; \
158	mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \	158	mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
159	mtspr SPRN_SRR1,r20; \	159	mtspr SPRN_SRR1,r20; \
160	mfspr r20,SPRN_SPRG1; /* restore r20 */ \	160	mfspr r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
161	mtspr SPRN_SPRG1,r13; /* save r13 */ \	161	mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
162	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)	162	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
163		163
164		164
@@ -167,15 +167,15 @@ label##_pSeries: \
167	.globl label##_pSeries; \	167	.globl label##_pSeries; \
168	label##_pSeries: \	168	label##_pSeries: \
169	HMT_MEDIUM; \	169	HMT_MEDIUM; \
170	mtspr SPRN_SPRG1,r13; /* save r13 */ \	170	mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
171	mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \	171	mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
172	std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \	172	std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
173	std r10,PACA_EXGEN+EX_R10(r13); \	173	std r10,PACA_EXGEN+EX_R10(r13); \
174	lbz r10,PACASOFTIRQEN(r13); \	174	lbz r10,PACASOFTIRQEN(r13); \
175	mfcr r9; \	175	mfcr r9; \
176	cmpwi r10,0; \	176	cmpwi r10,0; \
177	beq masked_interrupt; \	177	beq masked_interrupt; \
178	mfspr r10,SPRN_SPRG1; \	178	mfspr r10,SPRN_SPRG_SCRATCH0; \
179	std r10,PACA_EXGEN+EX_R13(r13); \	179	std r10,PACA_EXGEN+EX_R13(r13); \
180	std r11,PACA_EXGEN+EX_R11(r13); \	180	std r11,PACA_EXGEN+EX_R11(r13); \
181	std r12,PACA_EXGEN+EX_R12(r13); \	181	std r12,PACA_EXGEN+EX_R12(r13); \


diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 1170267736d3..a8179cc99ac4 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h
@@ -646,6 +646,119 @@
646	#endif	646	#endif
647		647
648	/*	648	/*
		649	* SPRG usage:
		650	*
		651	* All 64-bit:
		652	* - SPRG3 stores PACA pointer
		653	*
		654	* 64-bit server:
		655	* - SPRG0 unused (reserved for HV on Power4)
		656	* - SPRG1 scratch for exception vectors
		657	* - SPRG2 scratch for exception vectors
		658	*
		659	* All 32-bit:
		660	* - SPRG3 current thread_info pointer
		661	* (virtual on BookE, physical on others)
		662	*
		663	* 32-bit classic:
		664	* - SPRG0 scratch for exception vectors
		665	* - SPRG1 scratch for exception vectors
		666	* - SPRG2 indicator that we are in RTAS
		667	* - SPRG4 (603 only) pseudo TLB LRU data
		668	*
		669	* 32-bit 40x:
		670	* - SPRG0 scratch for exception vectors
		671	* - SPRG1 scratch for exception vectors
		672	* - SPRG2 scratch for exception vectors
		673	* - SPRG4 scratch for exception vectors (not 403)
		674	* - SPRG5 scratch for exception vectors (not 403)
		675	* - SPRG6 scratch for exception vectors (not 403)
		676	* - SPRG7 scratch for exception vectors (not 403)
		677	*
		678	* 32-bit 440 and FSL BookE:
		679	* - SPRG0 scratch for exception vectors
		680	* - SPRG1 scratch for exception vectors (*)
		681	* - SPRG2 scratch for crit interrupts handler
		682	* - SPRG4 scratch for exception vectors
		683	* - SPRG5 scratch for exception vectors
		684	* - SPRG6 scratch for machine check handler
		685	* - SPRG7 scratch for exception vectors
		686	* - SPRG9 scratch for debug vectors (e500 only)
		687	*
		688	* Additionally, BookE separates "read" and "write"
		689	* of those registers. That allows to use the userspace
		690	* readable variant for reads, which can avoid a fault
		691	* with KVM type virtualization.
		692	*
		693	* (*) Under KVM, the host SPRG1 is used to point to
		694	* the current VCPU data structure
		695	*
		696	* 32-bit 8xx:
		697	* - SPRG0 scratch for exception vectors
		698	* - SPRG1 scratch for exception vectors
		699	* - SPRG2 apparently unused but initialized
		700	*
		701	*/
		702	#ifdef CONFIG_PPC64
		703	#define SPRN_SPRG_PACA SPRN_SPRG3
		704	#else
		705	#define SPRN_SPRG_THREAD SPRN_SPRG3
		706	#endif
		707
		708	#ifdef CONFIG_PPC_BOOK3S_64
		709	#define SPRN_SPRG_SCRATCH0 SPRN_SPRG1
		710	#define SPRN_SPRG_SCRATCH1 SPRN_SPRG2
		711	#endif
		712
		713	#ifdef CONFIG_PPC_BOOK3S_32
		714	#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
		715	#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
		716	#define SPRN_SPRG_RTAS SPRN_SPRG2
		717	#define SPRN_SPRG_603_LRU SPRN_SPRG4
		718	#endif
		719
		720	#ifdef CONFIG_40x
		721	#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
		722	#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
		723	#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
		724	#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
		725	#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
		726	#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
		727	#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
		728	#endif
		729
		730	#ifdef CONFIG_BOOKE
		731	#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
		732	#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
		733	#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
		734	#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
		735	#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
		736	#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
		737	#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
		738	#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
		739	#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
		740	#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
		741	#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG6R
		742	#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG6W
		743	#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
		744	#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
		745	#ifdef CONFIG_E200
		746	#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
		747	#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
		748	#else
		749	#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
		750	#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
		751	#endif
		752	#define SPRN_SPRG_RVCPU SPRN_SPRG1
		753	#define SPRN_SPRG_WVCPU SPRN_SPRG1
		754	#endif
		755
		756	#ifdef CONFIG_8xx
		757	#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
		758	#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
		759	#endif
		760
		761	/*
649	* An mtfsf instruction with the L bit set. On CPUs that support this a	762	* An mtfsf instruction with the L bit set. On CPUs that support this a
650	* full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.	763	* full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
651	*	764	*