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-rw-r--r--arch/powerpc/include/asm/fsl_guts.h5
-rw-r--r--arch/powerpc/include/asm/mmu-8xx.h2
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc32.h20
-rw-r--r--arch/powerpc/include/asm/pte-8xx.h7
4 files changed, 31 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index 77ced0b3d81d..43b6bb1a4a9c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -68,7 +68,10 @@ struct ccsr_guts {
68 u8 res0b4[0xc0 - 0xb4]; 68 u8 res0b4[0xc0 - 0xb4];
69 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register 69 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
70 Called 'elbcvselcr' on 86xx SOCs */ 70 Called 'elbcvselcr' on 86xx SOCs */
71 u8 res0c4[0x224 - 0xc4]; 71 u8 res0c4[0x100 - 0xc4];
72 __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
73 There are 16 registers */
74 u8 res140[0x224 - 0x140];
72 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ 75 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
73 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ 76 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
74 u8 res22c[0x604 - 0x22c]; 77 u8 res22c[0x604 - 0x22c];
diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
index 3d11d3ce79ec..986b9e1e1044 100644
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -56,6 +56,7 @@
56 * additional information from the MI_EPN, and MI_TWC registers. 56 * additional information from the MI_EPN, and MI_TWC registers.
57 */ 57 */
58#define SPRN_MI_RPN 790 58#define SPRN_MI_RPN 790
59#define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
59 60
60/* Define an RPN value for mapping kernel memory to large virtual 61/* Define an RPN value for mapping kernel memory to large virtual
61 * pages for boot initialization. This has real page number of 0, 62 * pages for boot initialization. This has real page number of 0,
@@ -129,6 +130,7 @@
129 * additional information from the MD_EPN, and MD_TWC registers. 130 * additional information from the MD_EPN, and MD_TWC registers.
130 */ 131 */
131#define SPRN_MD_RPN 798 132#define SPRN_MD_RPN 798
133#define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
132 134
133/* This is a temporary storage register that could be used to save 135/* This is a temporary storage register that could be used to save
134 * a processor working register during a tablewalk. 136 * a processor working register during a tablewalk.
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 945e47adf7db..234e07c47803 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -170,6 +170,25 @@ static inline unsigned long pte_update(pte_t *p,
170#ifdef PTE_ATOMIC_UPDATES 170#ifdef PTE_ATOMIC_UPDATES
171 unsigned long old, tmp; 171 unsigned long old, tmp;
172 172
173#ifdef CONFIG_PPC_8xx
174 unsigned long tmp2;
175
176 __asm__ __volatile__("\
1771: lwarx %0,0,%4\n\
178 andc %1,%0,%5\n\
179 or %1,%1,%6\n\
180 /* 0x200 == Extended encoding, bit 22 */ \
181 /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
182 rlwimi %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
183 rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
184 or %1,%3,%1\n\
185 xori %1,%1,0x200\n"
186" stwcx. %1,0,%4\n\
187 bne- 1b"
188 : "=&r" (old), "=&r" (tmp), "=m" (*p), "=&r" (tmp2)
189 : "r" (p), "r" (clr), "r" (set), "m" (*p)
190 : "cc" );
191#else /* CONFIG_PPC_8xx */
173 __asm__ __volatile__("\ 192 __asm__ __volatile__("\
1741: lwarx %0,0,%3\n\ 1931: lwarx %0,0,%3\n\
175 andc %1,%0,%4\n\ 194 andc %1,%0,%4\n\
@@ -180,6 +199,7 @@ static inline unsigned long pte_update(pte_t *p,
180 : "=&r" (old), "=&r" (tmp), "=m" (*p) 199 : "=&r" (old), "=&r" (tmp), "=m" (*p)
181 : "r" (p), "r" (clr), "r" (set), "m" (*p) 200 : "r" (p), "r" (clr), "r" (set), "m" (*p)
182 : "cc" ); 201 : "cc" );
202#endif /* CONFIG_PPC_8xx */
183#else /* PTE_ATOMIC_UPDATES */ 203#else /* PTE_ATOMIC_UPDATES */
184 unsigned long old = pte_val(*p); 204 unsigned long old = pte_val(*p);
185 *p = __pte((old & ~clr) | set); 205 *p = __pte((old & ~clr) | set);
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index d44826e4ff97..daa4616e61c4 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -48,19 +48,22 @@
48 */ 48 */
49#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */ 49#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */
50#define _PAGE_USER 0x0800 /* msb PP bits */ 50#define _PAGE_USER 0x0800 /* msb PP bits */
51/* set when neither _PAGE_USER nor _PAGE_RW are set */
52#define _PAGE_KNLRO 0x0200
51 53
52#define _PMD_PRESENT 0x0001 54#define _PMD_PRESENT 0x0001
53#define _PMD_BAD 0x0ff0 55#define _PMD_BAD 0x0ff0
54#define _PMD_PAGE_MASK 0x000c 56#define _PMD_PAGE_MASK 0x000c
55#define _PMD_PAGE_8M 0x000c 57#define _PMD_PAGE_8M 0x000c
56 58
57#define _PTE_NONE_MASK _PAGE_ACCESSED 59#define _PTE_NONE_MASK _PAGE_KNLRO
58 60
59/* Until my rework is finished, 8xx still needs atomic PTE updates */ 61/* Until my rework is finished, 8xx still needs atomic PTE updates */
60#define PTE_ATOMIC_UPDATES 1 62#define PTE_ATOMIC_UPDATES 1
61 63
62/* We need to add _PAGE_SHARED to kernel pages */ 64/* We need to add _PAGE_SHARED to kernel pages */
63#define _PAGE_KERNEL_RO (_PAGE_SHARED) 65#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_KNLRO)
66#define _PAGE_KERNEL_ROX (_PAGE_EXEC | _PAGE_KNLRO)
64#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE) 67#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
65 68
66#endif /* __KERNEL__ */ 69#endif /* __KERNEL__ */