Merge remote-tracking branch 'scottwood/next' into next

Scott says:

"Highlights include a bunch of 8xx optimizations, device tree bindings
for Freescale BMan, QMan, and FMan datapath components, misc device tree
updates, and inbound rio window support."

4 files changed, 31 insertions, 3 deletions

diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index 77ced0b3d81d..43b6bb1a4a9c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -68,7 +68,10 @@ struct ccsr_guts {
         u8      res0b4[0xc0 - 0xb4];
         __be32  iovselsr;       /* 0x.00c0 - I/O voltage select status register
                                              Called 'elbcvselcr' on 86xx SOCs */
-        u8      res0c4[0x224 - 0xc4];
+        u8      res0c4[0x100 - 0xc4];
+        __be32  rcwsr[16];      /* 0x.0100 - Reset Control Word Status registers
+                                             There are 16 registers */
+        u8      res140[0x224 - 0x140];
         __be32  iodelay1;       /* 0x.0224 - IO delay control register 1 */
         __be32  iodelay2;       /* 0x.0228 - IO delay control register 2 */
         u8      res22c[0x604 - 0x22c];
diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
index 3d11d3ce79ec..986b9e1e1044 100644
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -56,6 +56,7 @@
  * additional information from the MI_EPN, and MI_TWC registers.
  */
 #define SPRN_MI_RPN     790
+#define MI_SPS16K       0x00000008      /* Small page size (0 = 4k, 1 = 16k) */
 
 /* Define an RPN value for mapping kernel memory to large virtual
  * pages for boot initialization.  This has real page number of 0,
@@ -129,6 +130,7 @@
  * additional information from the MD_EPN, and MD_TWC registers.
  */
 #define SPRN_MD_RPN     798
+#define MD_SPS16K       0x00000008      /* Small page size (0 = 4k, 1 = 16k) */
 
 /* This is a temporary storage register that could be used to save
  * a processor working register during a tablewalk.
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 945e47adf7db..234e07c47803 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -170,6 +170,25 @@ static inline unsigned long pte_update(pte_t *p,
 #ifdef PTE_ATOMIC_UPDATES
         unsigned long old, tmp;
 
+#ifdef CONFIG_PPC_8xx
+        unsigned long tmp2;
+
+        __asm__ __volatile__("\
+1:      lwarx   %0,0,%4\n\
+        andc    %1,%0,%5\n\
+        or      %1,%1,%6\n\
+        /* 0x200 == Extended encoding, bit 22 */ \
+        /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
+        rlwimi  %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
+        rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
+        or      %1,%3,%1\n\
+        xori    %1,%1,0x200\n"
+"       stwcx.  %1,0,%4\n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*p), "=&r" (tmp2)
+        : "r" (p), "r" (clr), "r" (set), "m" (*p)
+        : "cc" );
+#else /* CONFIG_PPC_8xx */
         __asm__ __volatile__("\
 1:      lwarx   %0,0,%3\n\
         andc    %1,%0,%4\n\
@@ -180,6 +199,7 @@ static inline unsigned long pte_update(pte_t *p,
         : "=&r" (old), "=&r" (tmp), "=m" (*p)
         : "r" (p), "r" (clr), "r" (set), "m" (*p)
         : "cc" );
+#endif /* CONFIG_PPC_8xx */
 #else /* PTE_ATOMIC_UPDATES */
         unsigned long old = pte_val(*p);
         *p = __pte((old & ~clr) | set);
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index d44826e4ff97..daa4616e61c4 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -48,19 +48,22 @@
  */
 #define _PAGE_RW        0x0400  /* lsb PP bits, inverted in HW */
 #define _PAGE_USER      0x0800  /* msb PP bits */
+/* set when neither _PAGE_USER nor _PAGE_RW are set */
+#define _PAGE_KNLRO     0x0200
 
 #define _PMD_PRESENT    0x0001
 #define _PMD_BAD        0x0ff0
 #define _PMD_PAGE_MASK  0x000c
 #define _PMD_PAGE_8M    0x000c
 
-#define _PTE_NONE_MASK _PAGE_ACCESSED
+#define _PTE_NONE_MASK _PAGE_KNLRO
 
 /* Until my rework is finished, 8xx still needs atomic PTE updates */
 #define PTE_ATOMIC_UPDATES      1
 
 /* We need to add _PAGE_SHARED to kernel pages */
-#define _PAGE_KERNEL_RO (_PAGE_SHARED)
+#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_KNLRO)
+#define _PAGE_KERNEL_ROX        (_PAGE_EXEC | _PAGE_KNLRO)
 #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
 
 #endif /* __KERNEL__ */