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Diffstat (limited to 'arch/powerpc/include/asm/vdso_datapage.h')
-rw-r--r--arch/powerpc/include/asm/vdso_datapage.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
index f01393224b52..13c2c283e178 100644
--- a/arch/powerpc/include/asm/vdso_datapage.h
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -39,6 +39,7 @@
39#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
40 40
41#include <linux/unistd.h> 41#include <linux/unistd.h>
42#include <linux/time.h>
42 43
43#define SYSCALL_MAP_SIZE ((__NR_syscalls + 31) / 32) 44#define SYSCALL_MAP_SIZE ((__NR_syscalls + 31) / 32)
44 45
@@ -83,6 +84,7 @@ struct vdso_data {
83 __u32 icache_log_block_size; /* L1 i-cache log block size */ 84 __u32 icache_log_block_size; /* L1 i-cache log block size */
84 __s32 wtom_clock_sec; /* Wall to monotonic clock */ 85 __s32 wtom_clock_sec; /* Wall to monotonic clock */
85 __s32 wtom_clock_nsec; 86 __s32 wtom_clock_nsec;
87 struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
86 __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */ 88 __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
87 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */ 89 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
88}; 90};
@@ -102,6 +104,7 @@ struct vdso_data {
102 __u32 tz_dsttime; /* Type of dst correction 0x5C */ 104 __u32 tz_dsttime; /* Type of dst correction 0x5C */
103 __s32 wtom_clock_sec; /* Wall to monotonic clock */ 105 __s32 wtom_clock_sec; /* Wall to monotonic clock */
104 __s32 wtom_clock_nsec; 106 __s32 wtom_clock_nsec;
107 struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
105 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */ 108 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
106 __u32 dcache_block_size; /* L1 d-cache block size */ 109 __u32 dcache_block_size; /* L1 d-cache block size */
107 __u32 icache_block_size; /* L1 i-cache block size */ 110 __u32 icache_block_size; /* L1 i-cache block size */
lass="hl opt">[SAS_ADDR_SIZE]; u8 max_sas_lrate; u8 min_sas_lrate; u8 max_sata_lrate; u8 min_sata_lrate; u8 flags; #define ASD_CRC_DIS 1 #define ASD_SATA_SPINUP_HOLD 2 u8 phy_control_0; /* mode 5 reg 0x160 */ u8 phy_control_1; /* mode 5 reg 0x161 */ u8 phy_control_2; /* mode 5 reg 0x162 */ u8 phy_control_3; /* mode 5 reg 0x163 */ }; struct asd_dma_tok { void *vaddr; dma_addr_t dma_handle; size_t size; }; struct hw_profile { struct bios_struct bios; struct unit_element_struct ue; struct flash_struct flash; u8 sas_addr[SAS_ADDR_SIZE]; char pcba_sn[ASD_PCBA_SN_SIZE+1]; u8 enabled_phys; /* mask of enabled phys */ struct asd_phy_desc phy_desc[ASD_MAX_PHYS]; u32 max_scbs; /* absolute sequencer scb queue size */ struct asd_dma_tok *scb_ext; u32 max_ddbs; struct asd_dma_tok *ddb_ext; spinlock_t ddb_lock; void *ddb_bitmap; int num_phys; /* ENABLEABLE */ int max_phys; /* REPORTED + ENABLEABLE */ unsigned addr_range; /* max # of addrs; max # of possible ports */ unsigned port_name_base; unsigned dev_name_base; unsigned sata_name_base; }; struct asd_ascb { struct list_head list; struct asd_ha_struct *ha; struct scb *scb; /* equals dma_scb->vaddr */ struct asd_dma_tok dma_scb; struct asd_dma_tok *sg_arr; void (*tasklet_complete)(struct asd_ascb *, struct done_list_struct *); u8 uldd_timer:1; /* internally generated command */ struct timer_list timer; struct completion *completion; u8 tag_valid:1; __be16 tag; /* error recovery only */ /* If this is an Empty SCB, index of first edb in seq->edb_arr. */ int edb_index; /* Used by the timer timeout function. */ int tc_index; void *uldd_task; }; #define ASD_DL_SIZE_BITS 0x8 #define ASD_DL_SIZE (1<<(2+ASD_DL_SIZE_BITS)) #define ASD_DEF_DL_TOGGLE 0x01 struct asd_seq_data { spinlock_t pend_q_lock; u16 scbpro; int pending; struct list_head pend_q; int can_queue; /* per adapter */ struct asd_dma_tok next_scb; /* next scb to be delivered to CSEQ */ spinlock_t tc_index_lock; void **tc_index_array; void *tc_index_bitmap; int tc_index_bitmap_bits; struct tasklet_struct dl_tasklet; struct done_list_struct *dl; /* array of done list entries, equals */ struct asd_dma_tok *actual_dl; /* actual_dl->vaddr */ int dl_toggle; int dl_next; int num_edbs; struct asd_dma_tok **edb_arr; int num_escbs; struct asd_ascb **escb_arr; /* array of pointers to escbs */ }; /* This is an internal port structure. These are used to get accurate * phy_mask for updating DDB 0. */ struct asd_port { u8 sas_addr[SAS_ADDR_SIZE]; u8 attached_sas_addr[SAS_ADDR_SIZE]; u32 phy_mask; int num_phys; }; /* This is the Host Adapter structure. It describes the hardware * SAS adapter. */ struct asd_ha_struct { struct pci_dev *pcidev; const char *name; struct sas_ha_struct sas_ha; u8 revision_id; int iospace; spinlock_t iolock; struct asd_ha_addrspace io_handle[2]; struct hw_profile hw_prof; struct asd_phy phys[ASD_MAX_PHYS]; spinlock_t asd_ports_lock; struct asd_port asd_ports[ASD_MAX_PHYS]; struct asd_sas_port ports[ASD_MAX_PHYS]; struct dma_pool *scb_pool; struct asd_seq_data seq; /* sequencer related */ u32 bios_status; const struct firmware *bios_image; }; /* ---------- Common macros ---------- */ #define ASD_BUSADDR_LO(__dma_handle) ((u32)(__dma_handle)) #define ASD_BUSADDR_HI(__dma_handle) (((sizeof(dma_addr_t))==8) \ ? ((u32)((__dma_handle) >> 32)) \ : ((u32)0)) #define dev_to_asd_ha(__dev) pci_get_drvdata(to_pci_dev(__dev)) #define SCB_SITE_VALID(__site_no) (((__site_no) & 0xF0FF) != 0x00FF \ && ((__site_no) & 0xF0FF) > 0x001F) /* For each bit set in __lseq_mask, set __lseq to equal the bit * position of the set bit and execute the statement following. * __mc is the temporary mask, used as a mask "counter". */ #define for_each_sequencer(__lseq_mask, __mc, __lseq) \ for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\ if (((__mc) & 1)) #define for_each_phy(__lseq_mask, __mc, __lseq) \ for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\ if (((__mc) & 1)) #define PHY_ENABLED(_HA, _I) ((_HA)->hw_prof.enabled_phys & (1<<(_I)))