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Diffstat (limited to 'arch/powerpc/include/asm/reg_booke.h')
-rw-r--r--arch/powerpc/include/asm/reg_booke.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 67453766bff1..597debe780bd 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -110,6 +110,7 @@
110#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 110#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
111#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 111#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
112#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */ 112#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
113#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
113#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 114#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
114#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ 115#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
115#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ 116#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */