diff options
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 43 |
1 files changed, 35 insertions, 8 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 62b114e079cf..90c06ec6eff5 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
| @@ -223,17 +223,26 @@ | |||
| 223 | #define CTRL_TE 0x00c00000 /* thread enable */ | 223 | #define CTRL_TE 0x00c00000 /* thread enable */ |
| 224 | #define CTRL_RUNLATCH 0x1 | 224 | #define CTRL_RUNLATCH 0x1 |
| 225 | #define SPRN_DAWR 0xB4 | 225 | #define SPRN_DAWR 0xB4 |
| 226 | #define SPRN_CIABR 0xBB | ||
| 227 | #define CIABR_PRIV 0x3 | ||
| 228 | #define CIABR_PRIV_USER 1 | ||
| 229 | #define CIABR_PRIV_SUPER 2 | ||
| 230 | #define CIABR_PRIV_HYPER 3 | ||
| 226 | #define SPRN_DAWRX 0xBC | 231 | #define SPRN_DAWRX 0xBC |
| 227 | #define DAWRX_USER (1UL << 0) | 232 | #define DAWRX_USER __MASK(0) |
| 228 | #define DAWRX_KERNEL (1UL << 1) | 233 | #define DAWRX_KERNEL __MASK(1) |
| 229 | #define DAWRX_HYP (1UL << 2) | 234 | #define DAWRX_HYP __MASK(2) |
| 235 | #define DAWRX_WTI __MASK(3) | ||
| 236 | #define DAWRX_WT __MASK(4) | ||
| 237 | #define DAWRX_DR __MASK(5) | ||
| 238 | #define DAWRX_DW __MASK(6) | ||
| 230 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ | 239 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ |
| 231 | #define SPRN_DABR2 0x13D /* e300 */ | 240 | #define SPRN_DABR2 0x13D /* e300 */ |
| 232 | #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ | 241 | #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ |
| 233 | #define DABRX_USER (1UL << 0) | 242 | #define DABRX_USER __MASK(0) |
| 234 | #define DABRX_KERNEL (1UL << 1) | 243 | #define DABRX_KERNEL __MASK(1) |
| 235 | #define DABRX_HYP (1UL << 2) | 244 | #define DABRX_HYP __MASK(2) |
| 236 | #define DABRX_BTI (1UL << 3) | 245 | #define DABRX_BTI __MASK(3) |
| 237 | #define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER) | 246 | #define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER) |
| 238 | #define SPRN_DAR 0x013 /* Data Address Register */ | 247 | #define SPRN_DAR 0x013 /* Data Address Register */ |
| 239 | #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ | 248 | #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ |
| @@ -260,6 +269,8 @@ | |||
| 260 | #define SPRN_HRMOR 0x139 /* Real mode offset register */ | 269 | #define SPRN_HRMOR 0x139 /* Real mode offset register */ |
| 261 | #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ | 270 | #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ |
| 262 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ | 271 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ |
| 272 | #define SPRN_IC 0x350 /* Virtual Instruction Count */ | ||
| 273 | #define SPRN_VTB 0x351 /* Virtual Time Base */ | ||
| 263 | /* HFSCR and FSCR bit numbers are the same */ | 274 | /* HFSCR and FSCR bit numbers are the same */ |
| 264 | #define FSCR_TAR_LG 8 /* Enable Target Address Register */ | 275 | #define FSCR_TAR_LG 8 /* Enable Target Address Register */ |
| 265 | #define FSCR_EBB_LG 7 /* Enable Event Based Branching */ | 276 | #define FSCR_EBB_LG 7 /* Enable Event Based Branching */ |
| @@ -298,9 +309,13 @@ | |||
| 298 | #define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ | 309 | #define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ |
| 299 | #define LPCR_RMLS_SH (63-37) | 310 | #define LPCR_RMLS_SH (63-37) |
| 300 | #define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ | 311 | #define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ |
| 312 | #define LPCR_AIL 0x01800000 /* Alternate interrupt location */ | ||
| 301 | #define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ | 313 | #define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ |
| 302 | #define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ | 314 | #define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ |
| 303 | #define LPCR_PECE 0x00007000 /* powersave exit cause enable */ | 315 | #define LPCR_ONL 0x00040000 /* online - PURR/SPURR count */ |
| 316 | #define LPCR_PECE 0x0001f000 /* powersave exit cause enable */ | ||
| 317 | #define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */ | ||
| 318 | #define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */ | ||
| 304 | #define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ | 319 | #define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ |
| 305 | #define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ | 320 | #define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ |
| 306 | #define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */ | 321 | #define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */ |
| @@ -322,6 +337,8 @@ | |||
| 322 | #define SPRN_PCR 0x152 /* Processor compatibility register */ | 337 | #define SPRN_PCR 0x152 /* Processor compatibility register */ |
| 323 | #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ | 338 | #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ |
| 324 | #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ | 339 | #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ |
| 340 | #define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */ | ||
| 341 | #define PCR_ARCH_206 0x4 /* Architecture 2.06 */ | ||
| 325 | #define PCR_ARCH_205 0x2 /* Architecture 2.05 */ | 342 | #define PCR_ARCH_205 0x2 /* Architecture 2.05 */ |
| 326 | #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ | 343 | #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ |
| 327 | #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ | 344 | #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ |
| @@ -368,6 +385,8 @@ | |||
| 368 | #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ | 385 | #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ |
| 369 | #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ | 386 | #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ |
| 370 | #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ | 387 | #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ |
| 388 | #define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */ | ||
| 389 | #define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */ | ||
| 371 | #define SPRN_EAR 0x11A /* External Address Register */ | 390 | #define SPRN_EAR 0x11A /* External Address Register */ |
| 372 | #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ | 391 | #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ |
| 373 | #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ | 392 | #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ |
| @@ -427,6 +446,7 @@ | |||
| 427 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ | 446 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ |
| 428 | #define SPRN_IABR2 0x3FA /* 83xx */ | 447 | #define SPRN_IABR2 0x3FA /* 83xx */ |
| 429 | #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ | 448 | #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ |
| 449 | #define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */ | ||
| 430 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ | 450 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ |
| 431 | #define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */ | 451 | #define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */ |
| 432 | #define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */ | 452 | #define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */ |
| @@ -541,6 +561,7 @@ | |||
| 541 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ | 561 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ |
| 542 | #endif | 562 | #endif |
| 543 | #define SPRN_TIR 0x1BE /* Thread Identification Register */ | 563 | #define SPRN_TIR 0x1BE /* Thread Identification Register */ |
| 564 | #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */ | ||
| 544 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ | 565 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ |
| 545 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ | 566 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ |
| 546 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ | 567 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ |
| @@ -682,6 +703,7 @@ | |||
| 682 | #define SPRN_EBBHR 804 /* Event based branch handler register */ | 703 | #define SPRN_EBBHR 804 /* Event based branch handler register */ |
| 683 | #define SPRN_EBBRR 805 /* Event based branch return register */ | 704 | #define SPRN_EBBRR 805 /* Event based branch return register */ |
| 684 | #define SPRN_BESCR 806 /* Branch event status and control register */ | 705 | #define SPRN_BESCR 806 /* Branch event status and control register */ |
| 706 | #define SPRN_WORT 895 /* Workload optimization register - thread */ | ||
| 685 | 707 | ||
| 686 | #define SPRN_PMC1 787 | 708 | #define SPRN_PMC1 787 |
| 687 | #define SPRN_PMC2 788 | 709 | #define SPRN_PMC2 788 |
| @@ -698,6 +720,11 @@ | |||
| 698 | #define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ | 720 | #define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ |
| 699 | #define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ | 721 | #define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ |
| 700 | #define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ | 722 | #define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ |
| 723 | #define SPRN_TACR 888 | ||
| 724 | #define SPRN_TCSCR 889 | ||
| 725 | #define SPRN_CSIGR 890 | ||
| 726 | #define SPRN_SPMC1 892 | ||
| 727 | #define SPRN_SPMC2 893 | ||
| 701 | 728 | ||
| 702 | /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */ | 729 | /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */ |
| 703 | #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO) | 730 | #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO) |