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-rw-r--r--arch/powerpc/include/asm/cpm1.h45
1 files changed, 0 insertions, 45 deletions
diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
index 7685ffde8821..81b01192f440 100644
--- a/arch/powerpc/include/asm/cpm1.h
+++ b/arch/powerpc/include/asm/cpm1.h
@@ -478,51 +478,6 @@ typedef struct iic {
478 char res2[2]; /* Reserved */ 478 char res2[2]; /* Reserved */
479} iic_t; 479} iic_t;
480 480
481/* SPI parameter RAM.
482*/
483typedef struct spi {
484 ushort spi_rbase; /* Rx Buffer descriptor base address */
485 ushort spi_tbase; /* Tx Buffer descriptor base address */
486 u_char spi_rfcr; /* Rx function code */
487 u_char spi_tfcr; /* Tx function code */
488 ushort spi_mrblr; /* Max receive buffer length */
489 uint spi_rstate; /* Internal */
490 uint spi_rdp; /* Internal */
491 ushort spi_rbptr; /* Internal */
492 ushort spi_rbc; /* Internal */
493 uint spi_rxtmp; /* Internal */
494 uint spi_tstate; /* Internal */
495 uint spi_tdp; /* Internal */
496 ushort spi_tbptr; /* Internal */
497 ushort spi_tbc; /* Internal */
498 uint spi_txtmp; /* Internal */
499 uint spi_res;
500 ushort spi_rpbase; /* Relocation pointer */
501 ushort spi_res2;
502} spi_t;
503
504/* SPI Mode register.
505*/
506#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
507#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
508#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
509#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
510#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
511#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
512#define SPMODE_EN ((ushort)0x0100) /* Enable */
513#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
514#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
515#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
516#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
517#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
518
519/* SPIE fields */
520#define SPIE_MME 0x20
521#define SPIE_TXE 0x10
522#define SPIE_BSY 0x04
523#define SPIE_TXB 0x02
524#define SPIE_RXB 0x01
525
526/* 481/*
527 * RISC Controller Configuration Register definitons 482 * RISC Controller Configuration Register definitons
528 */ 483 */