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-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts148
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts135
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts135
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts219
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts187
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts (renamed from arch/powerpc/boot/dts/mpc8349emds.dts)6
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts380
7 files changed, 1098 insertions, 112 deletions
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
new file mode 100644
index 000000000000..096e94ac415f
--- /dev/null
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -0,0 +1,148 @@
1/*
2 * Device Tree Souce for Buffalo KuroboxHD
3 *
4 * Choose CONFIG_LINKSTATION to build a kernel for KuroboxHD, or use
5 * the default configuration linkstation_defconfig.
6 *
7 * Based on sandpoint.dts
8 *
9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
10 *
11 * This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15
16XXXX add flash parts, rtc, ??
17
18build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
19
20
21 */
22
23/ {
24 linux,phandle = <1000>;
25 model = "KuroboxHD";
26 compatible = "linkstation";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 cpus {
31 linux,phandle = <2000>;
32 #cpus = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,603e { /* Really 8241 */
37 linux,phandle = <2100>;
38 linux,boot-cpu;
39 device_type = "cpu";
40 reg = <0>;
41 clock-frequency = <bebc200>; /* Fixed by bootwrapper */
42 timebase-frequency = <1743000>; /* Fixed by bootwrapper */
43 bus-frequency = <0>; /* From bootloader */
44 /* Following required by dtc but not used */
45 i-cache-line-size = <0>;
46 d-cache-line-size = <0>;
47 i-cache-size = <4000>;
48 d-cache-size = <4000>;
49 };
50 };
51
52 memory {
53 linux,phandle = <3000>;
54 device_type = "memory";
55 reg = <00000000 04000000>;
56 };
57
58 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
59 linux,phandle = <4000>;
60 #address-cells = <1>;
61 #size-cells = <1>;
62 #interrupt-cells = <2>;
63 device_type = "soc";
64 compatible = "mpc10x";
65 store-gathering = <0>; /* 0 == off, !0 == on */
66 reg = <80000000 00100000>;
67 ranges = <80000000 80000000 70000000 /* pci mem space */
68 fc000000 fc000000 00100000 /* EUMB */
69 fe000000 fe000000 00c00000 /* pci i/o space */
70 fec00000 fec00000 00300000 /* pci cfg regs */
71 fef00000 fef00000 00100000>; /* pci iack */
72
73 i2c@80003000 {
74 linux,phandle = <4300>;
75 device_type = "i2c";
76 compatible = "fsl-i2c";
77 reg = <80003000 1000>;
78 interrupts = <5 2>;
79 interrupt-parent = <4400>;
80 };
81
82 serial@80004500 {
83 linux,phandle = <4511>;
84 device_type = "serial";
85 compatible = "ns16550";
86 reg = <80004500 8>;
87 clock-frequency = <5d08d88>;
88 current-speed = <2580>;
89 interrupts = <9 2>;
90 interrupt-parent = <4400>;
91 };
92
93 serial@80004600 {
94 linux,phandle = <4512>;
95 device_type = "serial";
96 compatible = "ns16550";
97 reg = <80004600 8>;
98 clock-frequency = <5d08d88>;
99 current-speed = <e100>;
100 interrupts = <a 0>;
101 interrupt-parent = <4400>;
102 };
103
104 pic@80040000 {
105 linux,phandle = <4400>;
106 #interrupt-cells = <2>;
107 #address-cells = <0>;
108 device_type = "open-pic";
109 compatible = "chrp,open-pic";
110 interrupt-controller;
111 reg = <80040000 40000>;
112 built-in;
113 };
114
115 pci@fec00000 {
116 linux,phandle = <4500>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
120 device_type = "pci";
121 compatible = "mpc10x-pci";
122 reg = <fec00000 400000>;
123 ranges = <01000000 0 0 fe000000 0 00c00000
124 02000000 0 80000000 80000000 0 70000000>;
125 bus-range = <0 ff>;
126 clock-frequency = <7f28155>;
127 interrupt-parent = <4400>;
128 interrupt-map-mask = <f800 0 0 7>;
129 interrupt-map = <
130 /* IDSEL 0x11 - IRQ0 ETH */
131 5800 0 0 1 4400 0 1
132 5800 0 0 2 4400 1 1
133 5800 0 0 3 4400 2 1
134 5800 0 0 4 4400 3 1
135 /* IDSEL 0x12 - IRQ1 IDE0 */
136 6000 0 0 1 4400 1 1
137 6000 0 0 2 4400 2 1
138 6000 0 0 3 4400 3 1
139 6000 0 0 4 4400 0 1
140 /* IDSEL 0x14 - IRQ3 USB2.0 */
141 7000 0 0 1 4400 3 1
142 7000 0 0 2 4400 3 1
143 7000 0 0 3 4400 3 1
144 7000 0 0 4 4400 3 1
145 >;
146 };
147 };
148};
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 186870704ad9..c03103c63285 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Lite5200 board Device Tree Source 2 * Lite5200 board Device Tree Source
3 * 3 *
4 * Copyright 2006 Secret Lab Technologies Ltd. 4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca> 5 * Grant Likely <grant.likely@secretlab.ca>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -17,8 +17,9 @@
17 */ 17 */
18 18
19/ { 19/ {
20 model = "Lite5200"; 20 model = "fsl,lite5200";
21 compatible = "lite5200\0lite52xx\0mpc5200\0mpc52xx"; 21 // revision = "1.0";
22 compatible = "fsl,lite5200\0generic-mpc5200";
22 #address-cells = <1>; 23 #address-cells = <1>;
23 #size-cells = <1>; 24 #size-cells = <1>;
24 25
@@ -47,14 +48,17 @@
47 }; 48 };
48 49
49 soc5200@f0000000 { 50 soc5200@f0000000 {
51 model = "fsl,mpc5200";
52 revision = "" // from bootloader
50 #interrupt-cells = <3>; 53 #interrupt-cells = <3>;
51 device_type = "soc"; 54 device_type = "soc";
52 ranges = <0 f0000000 f0010000>; 55 ranges = <0 f0000000 f0010000>;
53 reg = <f0000000 00010000>; 56 reg = <f0000000 00010000>;
54 bus-frequency = <0>; // from bootloader 57 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader
55 59
56 cdm@200 { 60 cdm@200 {
57 compatible = "mpc5200-cdm\0mpc52xx-cdm"; 61 compatible = "mpc5200-cdm";
58 reg = <200 38>; 62 reg = <200 38>;
59 }; 63 };
60 64
@@ -64,77 +68,86 @@
64 interrupt-controller; 68 interrupt-controller;
65 #interrupt-cells = <3>; 69 #interrupt-cells = <3>;
66 device_type = "interrupt-controller"; 70 device_type = "interrupt-controller";
67 compatible = "mpc5200-pic\0mpc52xx-pic"; 71 compatible = "mpc5200-pic";
68 reg = <500 80>; 72 reg = <500 80>;
69 built-in; 73 built-in;
70 }; 74 };
71 75
72 gpt@600 { // General Purpose Timer 76 gpt@600 { // General Purpose Timer
73 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 77 compatible = "mpc5200-gpt";
74 device_type = "gpt"; 78 device_type = "gpt";
79 cell-index = <0>;
75 reg = <600 10>; 80 reg = <600 10>;
76 interrupts = <1 9 0>; 81 interrupts = <1 9 0>;
77 interrupt-parent = <500>; 82 interrupt-parent = <500>;
83 has-wdt;
78 }; 84 };
79 85
80 gpt@610 { // General Purpose Timer 86 gpt@610 { // General Purpose Timer
81 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 87 compatible = "mpc5200-gpt";
82 device_type = "gpt"; 88 device_type = "gpt";
89 cell-index = <1>;
83 reg = <610 10>; 90 reg = <610 10>;
84 interrupts = <1 a 0>; 91 interrupts = <1 a 0>;
85 interrupt-parent = <500>; 92 interrupt-parent = <500>;
86 }; 93 };
87 94
88 gpt@620 { // General Purpose Timer 95 gpt@620 { // General Purpose Timer
89 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 96 compatible = "mpc5200-gpt";
90 device_type = "gpt"; 97 device_type = "gpt";
98 cell-index = <2>;
91 reg = <620 10>; 99 reg = <620 10>;
92 interrupts = <1 b 0>; 100 interrupts = <1 b 0>;
93 interrupt-parent = <500>; 101 interrupt-parent = <500>;
94 }; 102 };
95 103
96 gpt@630 { // General Purpose Timer 104 gpt@630 { // General Purpose Timer
97 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 105 compatible = "mpc5200-gpt";
98 device_type = "gpt"; 106 device_type = "gpt";
107 cell-index = <3>;
99 reg = <630 10>; 108 reg = <630 10>;
100 interrupts = <1 c 0>; 109 interrupts = <1 c 0>;
101 interrupt-parent = <500>; 110 interrupt-parent = <500>;
102 }; 111 };
103 112
104 gpt@640 { // General Purpose Timer 113 gpt@640 { // General Purpose Timer
105 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 114 compatible = "mpc5200-gpt";
106 device_type = "gpt"; 115 device_type = "gpt";
116 cell-index = <4>;
107 reg = <640 10>; 117 reg = <640 10>;
108 interrupts = <1 d 0>; 118 interrupts = <1 d 0>;
109 interrupt-parent = <500>; 119 interrupt-parent = <500>;
110 }; 120 };
111 121
112 gpt@650 { // General Purpose Timer 122 gpt@650 { // General Purpose Timer
113 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 123 compatible = "mpc5200-gpt";
114 device_type = "gpt"; 124 device_type = "gpt";
125 cell-index = <5>;
115 reg = <650 10>; 126 reg = <650 10>;
116 interrupts = <1 e 0>; 127 interrupts = <1 e 0>;
117 interrupt-parent = <500>; 128 interrupt-parent = <500>;
118 }; 129 };
119 130
120 gpt@660 { // General Purpose Timer 131 gpt@660 { // General Purpose Timer
121 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 132 compatible = "mpc5200-gpt";
122 device_type = "gpt"; 133 device_type = "gpt";
134 cell-index = <6>;
123 reg = <660 10>; 135 reg = <660 10>;
124 interrupts = <1 f 0>; 136 interrupts = <1 f 0>;
125 interrupt-parent = <500>; 137 interrupt-parent = <500>;
126 }; 138 };
127 139
128 gpt@670 { // General Purpose Timer 140 gpt@670 { // General Purpose Timer
129 compatible = "mpc5200-gpt\0mpc52xx-gpt"; 141 compatible = "mpc5200-gpt";
130 device_type = "gpt"; 142 device_type = "gpt";
143 cell-index = <7>;
131 reg = <670 10>; 144 reg = <670 10>;
132 interrupts = <1 10 0>; 145 interrupts = <1 10 0>;
133 interrupt-parent = <500>; 146 interrupt-parent = <500>;
134 }; 147 };
135 148
136 rtc@800 { // Real time clock 149 rtc@800 { // Real time clock
137 compatible = "mpc5200-rtc\0mpc52xx-rtc"; 150 compatible = "mpc5200-rtc";
138 device_type = "rtc"; 151 device_type = "rtc";
139 reg = <800 100>; 152 reg = <800 100>;
140 interrupts = <1 5 0 1 6 0>; 153 interrupts = <1 5 0 1 6 0>;
@@ -143,7 +156,8 @@
143 156
144 mscan@900 { 157 mscan@900 {
145 device_type = "mscan"; 158 device_type = "mscan";
146 compatible = "mpc5200-mscan\0mpc52xx-mscan"; 159 compatible = "mpc5200-mscan";
160 cell-index = <0>;
147 interrupts = <2 11 0>; 161 interrupts = <2 11 0>;
148 interrupt-parent = <500>; 162 interrupt-parent = <500>;
149 reg = <900 80>; 163 reg = <900 80>;
@@ -151,21 +165,22 @@
151 165
152 mscan@980 { 166 mscan@980 {
153 device_type = "mscan"; 167 device_type = "mscan";
154 compatible = "mpc5200-mscan\0mpc52xx-mscan"; 168 compatible = "mpc5200-mscan";
169 cell-index = <1>;
155 interrupts = <1 12 0>; 170 interrupts = <1 12 0>;
156 interrupt-parent = <500>; 171 interrupt-parent = <500>;
157 reg = <980 80>; 172 reg = <980 80>;
158 }; 173 };
159 174
160 gpio@b00 { 175 gpio@b00 {
161 compatible = "mpc5200-gpio\0mpc52xx-gpio"; 176 compatible = "mpc5200-gpio";
162 reg = <b00 40>; 177 reg = <b00 40>;
163 interrupts = <1 7 0>; 178 interrupts = <1 7 0>;
164 interrupt-parent = <500>; 179 interrupt-parent = <500>;
165 }; 180 };
166 181
167 gpio-wkup@b00 { 182 gpio-wkup@b00 {
168 compatible = "mpc5200-gpio-wkup\0mpc52xx-gpio-wkup"; 183 compatible = "mpc5200-gpio-wkup";
169 reg = <c00 40>; 184 reg = <c00 40>;
170 interrupts = <1 8 0 0 3 0>; 185 interrupts = <1 8 0 0 3 0>;
171 interrupt-parent = <500>; 186 interrupt-parent = <500>;
@@ -176,7 +191,7 @@
176 #size-cells = <2>; 191 #size-cells = <2>;
177 #address-cells = <3>; 192 #address-cells = <3>;
178 device_type = "pci"; 193 device_type = "pci";
179 compatible = "mpc5200-pci\0mpc52xx-pci"; 194 compatible = "mpc5200-pci";
180 reg = <d00 100>; 195 reg = <d00 100>;
181 interrupt-map-mask = <f800 0 0 7>; 196 interrupt-map-mask = <f800 0 0 7>;
182 interrupt-map = <c000 0 0 1 500 0 0 3 197 interrupt-map = <c000 0 0 1 500 0 0 3
@@ -194,7 +209,7 @@
194 209
195 spi@f00 { 210 spi@f00 {
196 device_type = "spi"; 211 device_type = "spi";
197 compatible = "mpc5200-spi\0mpc52xx-spi"; 212 compatible = "mpc5200-spi";
198 reg = <f00 20>; 213 reg = <f00 20>;
199 interrupts = <2 d 0 2 e 0>; 214 interrupts = <2 d 0 2 e 0>;
200 interrupt-parent = <500>; 215 interrupt-parent = <500>;
@@ -202,7 +217,7 @@
202 217
203 usb@1000 { 218 usb@1000 {
204 device_type = "usb-ohci-be"; 219 device_type = "usb-ohci-be";
205 compatible = "mpc5200-ohci\0mpc52xx-ohci\0ohci-be"; 220 compatible = "mpc5200-ohci\0ohci-be";
206 reg = <1000 ff>; 221 reg = <1000 ff>;
207 interrupts = <2 6 0>; 222 interrupts = <2 6 0>;
208 interrupt-parent = <500>; 223 interrupt-parent = <500>;
@@ -210,7 +225,7 @@
210 225
211 bestcomm@1200 { 226 bestcomm@1200 {
212 device_type = "dma-controller"; 227 device_type = "dma-controller";
213 compatible = "mpc5200-bestcomm\0mpc52xx-bestcomm"; 228 compatible = "mpc5200-bestcomm";
214 reg = <1200 80>; 229 reg = <1200 80>;
215 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 230 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
216 3 4 0 3 5 0 3 6 0 3 7 0 231 3 4 0 3 5 0 3 6 0 3 7 0
@@ -220,67 +235,73 @@
220 }; 235 };
221 236
222 xlb@1f00 { 237 xlb@1f00 {
223 compatible = "mpc5200-xlb\0mpc52xx-xlb"; 238 compatible = "mpc5200-xlb";
224 reg = <1f00 100>; 239 reg = <1f00 100>;
225 }; 240 };
226 241
227 serial@2000 { // PSC1 242 serial@2000 { // PSC1
228 device_type = "serial"; 243 device_type = "serial";
229 compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart"; 244 compatible = "mpc5200-psc-uart";
230 port-number = <0>; // Logical port assignment 245 port-number = <0>; // Logical port assignment
246 cell-index = <0>;
231 reg = <2000 100>; 247 reg = <2000 100>;
232 interrupts = <2 1 0>; 248 interrupts = <2 1 0>;
233 interrupt-parent = <500>; 249 interrupt-parent = <500>;
234 }; 250 };
235 251
236 // PSC2 in spi mode example 252 // PSC2 in ac97 mode example
237 spi@2200 { // PSC2 253 //ac97@2200 { // PSC2
238 device_type = "spi"; 254 // device_type = "sound";
239 compatible = "mpc5200-psc-spi\0mpc52xx-psc-spi"; 255 // compatible = "mpc5200-psc-ac97";
240 reg = <2200 100>; 256 // cell-index = <1>;
241 interrupts = <2 2 0>; 257 // reg = <2200 100>;
242 interrupt-parent = <500>; 258 // interrupts = <2 2 0>;
243 }; 259 // interrupt-parent = <500>;
260 //};
244 261
245 // PSC3 in CODEC mode example 262 // PSC3 in CODEC mode example
246 i2s@2400 { // PSC3 263 //i2s@2400 { // PSC3
247 device_type = "sound"; 264 // device_type = "sound";
248 compatible = "mpc5200-psc-i2s\0mpc52xx-psc-i2s"; 265 // compatible = "mpc5200-psc-i2s";
249 reg = <2400 100>; 266 // cell-index = <2>;
250 interrupts = <2 3 0>; 267 // reg = <2400 100>;
251 interrupt-parent = <500>; 268 // interrupts = <2 3 0>;
252 }; 269 // interrupt-parent = <500>;
270 //};
253 271
254 // PSC4 unconfigured 272 // PSC4 in uart mode example
255 //serial@2600 { // PSC4 273 //serial@2600 { // PSC4
256 // device_type = "serial"; 274 // device_type = "serial";
257 // compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart"; 275 // compatible = "mpc5200-psc-uart";
276 // cell-index = <3>;
258 // reg = <2600 100>; 277 // reg = <2600 100>;
259 // interrupts = <2 b 0>; 278 // interrupts = <2 b 0>;
260 // interrupt-parent = <500>; 279 // interrupt-parent = <500>;
261 //}; 280 //};
262 281
263 // PSC5 unconfigured 282 // PSC5 in uart mode example
264 //serial@2800 { // PSC5 283 //serial@2800 { // PSC5
265 // device_type = "serial"; 284 // device_type = "serial";
266 // compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart"; 285 // compatible = "mpc5200-psc-uart";
286 // cell-index = <4>;
267 // reg = <2800 100>; 287 // reg = <2800 100>;
268 // interrupts = <2 c 0>; 288 // interrupts = <2 c 0>;
269 // interrupt-parent = <500>; 289 // interrupt-parent = <500>;
270 //}; 290 //};
271 291
272 // PSC6 in AC97 mode example 292 // PSC6 in spi mode example
273 ac97@2c00 { // PSC6 293 //spi@2c00 { // PSC6
274 device_type = "sound"; 294 // device_type = "spi";
275 compatible = "mpc5200-psc-ac97\0mpc52xx-psc-ac97"; 295 // compatible = "mpc5200-psc-spi";
276 reg = <2c00 100>; 296 // cell-index = <5>;
277 interrupts = <2 4 0>; 297 // reg = <2c00 100>;
278 interrupt-parent = <500>; 298 // interrupts = <2 4 0>;
279 }; 299 // interrupt-parent = <500>;
300 //};
280 301
281 ethernet@3000 { 302 ethernet@3000 {
282 device_type = "network"; 303 device_type = "network";
283 compatible = "mpc5200-fec\0mpc52xx-fec"; 304 compatible = "mpc5200-fec";
284 reg = <3000 800>; 305 reg = <3000 800>;
285 mac-address = [ 02 03 04 05 06 07 ]; // Bad! 306 mac-address = [ 02 03 04 05 06 07 ]; // Bad!
286 interrupts = <2 5 0>; 307 interrupts = <2 5 0>;
@@ -289,7 +310,7 @@
289 310
290 ata@3a00 { 311 ata@3a00 {
291 device_type = "ata"; 312 device_type = "ata";
292 compatible = "mpc5200-ata\0mpc52xx-ata"; 313 compatible = "mpc5200-ata";
293 reg = <3a00 100>; 314 reg = <3a00 100>;
294 interrupts = <2 7 0>; 315 interrupts = <2 7 0>;
295 interrupt-parent = <500>; 316 interrupt-parent = <500>;
@@ -297,7 +318,8 @@
297 318
298 i2c@3d00 { 319 i2c@3d00 {
299 device_type = "i2c"; 320 device_type = "i2c";
300 compatible = "mpc5200-i2c\0mpc52xx-i2c"; 321 compatible = "mpc5200-i2c";
322 cell-index = <0>;
301 reg = <3d00 40>; 323 reg = <3d00 40>;
302 interrupts = <2 f 0>; 324 interrupts = <2 f 0>;
303 interrupt-parent = <500>; 325 interrupt-parent = <500>;
@@ -305,14 +327,15 @@
305 327
306 i2c@3d40 { 328 i2c@3d40 {
307 device_type = "i2c"; 329 device_type = "i2c";
308 compatible = "mpc5200-i2c\0mpc52xx-i2c"; 330 compatible = "mpc5200-i2c";
331 cell-index = <1>;
309 reg = <3d40 40>; 332 reg = <3d40 40>;
310 interrupts = <2 10 0>; 333 interrupts = <2 10 0>;
311 interrupt-parent = <500>; 334 interrupt-parent = <500>;
312 }; 335 };
313 sram@8000 { 336 sram@8000 {
314 device_type = "sram"; 337 device_type = "sram";
315 compatible = "mpc5200-sram\0mpc52xx-sram\0sram"; 338 compatible = "mpc5200-sram\0sram";
316 reg = <8000 4000>; 339 reg = <8000 4000>;
317 }; 340 };
318 }; 341 };
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 5bb2760d7c30..3875ca9a9a62 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Lite5200B board Device Tree Source 2 * Lite5200B board Device Tree Source
3 * 3 *
4 * Copyright 2006 Secret Lab Technologies Ltd. 4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca> 5 * Grant Likely <grant.likely@secretlab.ca>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -17,8 +17,9 @@
17 */ 17 */
18 18
19/ { 19/ {
20 model = "Lite5200b"; 20 model = "fsl,lite5200b";
21 compatible = "lite5200b\0lite52xx\0mpc5200b\0mpc52xx"; 21 // revision = "1.0";
22 compatible = "fsl,lite5200b\0generic-mpc5200";
22 #address-cells = <1>; 23 #address-cells = <1>;
23 #size-cells = <1>; 24 #size-cells = <1>;
24 25
@@ -47,14 +48,17 @@
47 }; 48 };
48 49
49 soc5200@f0000000 { 50 soc5200@f0000000 {
51 model = "fsl,mpc5200b";
52 revision = ""; // from bootloader
50 #interrupt-cells = <3>; 53 #interrupt-cells = <3>;
51 device_type = "soc"; 54 device_type = "soc";
52 ranges = <0 f0000000 f0010000>; 55 ranges = <0 f0000000 f0010000>;
53 reg = <f0000000 00010000>; 56 reg = <f0000000 00010000>;
54 bus-frequency = <0>; // from bootloader 57 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader
55 59
56 cdm@200 { 60 cdm@200 {
57 compatible = "mpc5200b-cdm\0mpc52xx-cdm"; 61 compatible = "mpc5200b-cdm\0mpc5200-cdm";
58 reg = <200 38>; 62 reg = <200 38>;
59 }; 63 };
60 64
@@ -64,77 +68,86 @@
64 interrupt-controller; 68 interrupt-controller;
65 #interrupt-cells = <3>; 69 #interrupt-cells = <3>;
66 device_type = "interrupt-controller"; 70 device_type = "interrupt-controller";
67 compatible = "mpc5200b-pic\0mpc52xx-pic"; 71 compatible = "mpc5200b-pic\0mpc5200-pic";
68 reg = <500 80>; 72 reg = <500 80>;
69 built-in; 73 built-in;
70 }; 74 };
71 75
72 gpt@600 { // General Purpose Timer 76 gpt@600 { // General Purpose Timer
73 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 77 compatible = "mpc5200b-gpt\0mpc5200-gpt";
74 device_type = "gpt"; 78 device_type = "gpt";
79 cell-index = <0>;
75 reg = <600 10>; 80 reg = <600 10>;
76 interrupts = <1 9 0>; 81 interrupts = <1 9 0>;
77 interrupt-parent = <500>; 82 interrupt-parent = <500>;
83 has-wdt;
78 }; 84 };
79 85
80 gpt@610 { // General Purpose Timer 86 gpt@610 { // General Purpose Timer
81 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 87 compatible = "mpc5200b-gpt\0mpc5200-gpt";
82 device_type = "gpt"; 88 device_type = "gpt";
89 cell-index = <1>;
83 reg = <610 10>; 90 reg = <610 10>;
84 interrupts = <1 a 0>; 91 interrupts = <1 a 0>;
85 interrupt-parent = <500>; 92 interrupt-parent = <500>;
86 }; 93 };
87 94
88 gpt@620 { // General Purpose Timer 95 gpt@620 { // General Purpose Timer
89 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 96 compatible = "mpc5200b-gpt\0mpc5200-gpt";
90 device_type = "gpt"; 97 device_type = "gpt";
98 cell-index = <2>;
91 reg = <620 10>; 99 reg = <620 10>;
92 interrupts = <1 b 0>; 100 interrupts = <1 b 0>;
93 interrupt-parent = <500>; 101 interrupt-parent = <500>;
94 }; 102 };
95 103
96 gpt@630 { // General Purpose Timer 104 gpt@630 { // General Purpose Timer
97 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 105 compatible = "mpc5200b-gpt\0mpc5200-gpt";
98 device_type = "gpt"; 106 device_type = "gpt";
107 cell-index = <3>;
99 reg = <630 10>; 108 reg = <630 10>;
100 interrupts = <1 c 0>; 109 interrupts = <1 c 0>;
101 interrupt-parent = <500>; 110 interrupt-parent = <500>;
102 }; 111 };
103 112
104 gpt@640 { // General Purpose Timer 113 gpt@640 { // General Purpose Timer
105 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 114 compatible = "mpc5200b-gpt\0mpc5200-gpt";
106 device_type = "gpt"; 115 device_type = "gpt";
116 cell-index = <4>;
107 reg = <640 10>; 117 reg = <640 10>;
108 interrupts = <1 d 0>; 118 interrupts = <1 d 0>;
109 interrupt-parent = <500>; 119 interrupt-parent = <500>;
110 }; 120 };
111 121
112 gpt@650 { // General Purpose Timer 122 gpt@650 { // General Purpose Timer
113 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 123 compatible = "mpc5200b-gpt\0mpc5200-gpt";
114 device_type = "gpt"; 124 device_type = "gpt";
125 cell-index = <5>;
115 reg = <650 10>; 126 reg = <650 10>;
116 interrupts = <1 e 0>; 127 interrupts = <1 e 0>;
117 interrupt-parent = <500>; 128 interrupt-parent = <500>;
118 }; 129 };
119 130
120 gpt@660 { // General Purpose Timer 131 gpt@660 { // General Purpose Timer
121 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 132 compatible = "mpc5200b-gpt\0mpc5200-gpt";
122 device_type = "gpt"; 133 device_type = "gpt";
134 cell-index = <6>;
123 reg = <660 10>; 135 reg = <660 10>;
124 interrupts = <1 f 0>; 136 interrupts = <1 f 0>;
125 interrupt-parent = <500>; 137 interrupt-parent = <500>;
126 }; 138 };
127 139
128 gpt@670 { // General Purpose Timer 140 gpt@670 { // General Purpose Timer
129 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 141 compatible = "mpc5200b-gpt\0mpc5200-gpt";
130 device_type = "gpt"; 142 device_type = "gpt";
143 cell-index = <7>;
131 reg = <670 10>; 144 reg = <670 10>;
132 interrupts = <1 10 0>; 145 interrupts = <1 10 0>;
133 interrupt-parent = <500>; 146 interrupt-parent = <500>;
134 }; 147 };
135 148
136 rtc@800 { // Real time clock 149 rtc@800 { // Real time clock
137 compatible = "mpc5200b-rtc\0mpc52xx-rtc"; 150 compatible = "mpc5200b-rtc\0mpc5200-rtc";
138 device_type = "rtc"; 151 device_type = "rtc";
139 reg = <800 100>; 152 reg = <800 100>;
140 interrupts = <1 5 0 1 6 0>; 153 interrupts = <1 5 0 1 6 0>;
@@ -143,7 +156,8 @@
143 156
144 mscan@900 { 157 mscan@900 {
145 device_type = "mscan"; 158 device_type = "mscan";
146 compatible = "mpc5200b-mscan\0mpc52xx-mscan"; 159 compatible = "mpc5200b-mscan\0mpc5200-mscan";
160 cell-index = <0>;
147 interrupts = <2 11 0>; 161 interrupts = <2 11 0>;
148 interrupt-parent = <500>; 162 interrupt-parent = <500>;
149 reg = <900 80>; 163 reg = <900 80>;
@@ -151,21 +165,22 @@
151 165
152 mscan@980 { 166 mscan@980 {
153 device_type = "mscan"; 167 device_type = "mscan";
154 compatible = "mpc5200b-mscan\0mpc52xx-mscan"; 168 compatible = "mpc5200b-mscan\0mpc5200-mscan";
169 cell-index = <1>;
155 interrupts = <1 12 0>; 170 interrupts = <1 12 0>;
156 interrupt-parent = <500>; 171 interrupt-parent = <500>;
157 reg = <980 80>; 172 reg = <980 80>;
158 }; 173 };
159 174
160 gpio@b00 { 175 gpio@b00 {
161 compatible = "mpc5200b-gpio\0mpc52xx-gpio"; 176 compatible = "mpc5200b-gpio\0mpc5200-gpio";
162 reg = <b00 40>; 177 reg = <b00 40>;
163 interrupts = <1 7 0>; 178 interrupts = <1 7 0>;
164 interrupt-parent = <500>; 179 interrupt-parent = <500>;
165 }; 180 };
166 181
167 gpio-wkup@b00 { 182 gpio-wkup@b00 {
168 compatible = "mpc5200b-gpio-wkup\0mpc52xx-gpio-wkup"; 183 compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
169 reg = <c00 40>; 184 reg = <c00 40>;
170 interrupts = <1 8 0 0 3 0>; 185 interrupts = <1 8 0 0 3 0>;
171 interrupt-parent = <500>; 186 interrupt-parent = <500>;
@@ -176,7 +191,7 @@
176 #size-cells = <2>; 191 #size-cells = <2>;
177 #address-cells = <3>; 192 #address-cells = <3>;
178 device_type = "pci"; 193 device_type = "pci";
179 compatible = "mpc5200b-pci\0mpc52xx-pci"; 194 compatible = "mpc5200b-pci\0mpc5200-pci";
180 reg = <d00 100>; 195 reg = <d00 100>;
181 interrupt-map-mask = <f800 0 0 7>; 196 interrupt-map-mask = <f800 0 0 7>;
182 interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot 197 interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot
@@ -199,7 +214,7 @@
199 214
200 spi@f00 { 215 spi@f00 {
201 device_type = "spi"; 216 device_type = "spi";
202 compatible = "mpc5200b-spi\0mpc52xx-spi"; 217 compatible = "mpc5200b-spi\0mpc5200-spi";
203 reg = <f00 20>; 218 reg = <f00 20>;
204 interrupts = <2 d 0 2 e 0>; 219 interrupts = <2 d 0 2 e 0>;
205 interrupt-parent = <500>; 220 interrupt-parent = <500>;
@@ -207,7 +222,7 @@
207 222
208 usb@1000 { 223 usb@1000 {
209 device_type = "usb-ohci-be"; 224 device_type = "usb-ohci-be";
210 compatible = "mpc5200b-ohci\0mpc52xx-ohci\0ohci-be"; 225 compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
211 reg = <1000 ff>; 226 reg = <1000 ff>;
212 interrupts = <2 6 0>; 227 interrupts = <2 6 0>;
213 interrupt-parent = <500>; 228 interrupt-parent = <500>;
@@ -215,7 +230,7 @@
215 230
216 bestcomm@1200 { 231 bestcomm@1200 {
217 device_type = "dma-controller"; 232 device_type = "dma-controller";
218 compatible = "mpc5200b-bestcomm\0mpc52xx-bestcomm"; 233 compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm";
219 reg = <1200 80>; 234 reg = <1200 80>;
220 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 235 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
221 3 4 0 3 5 0 3 6 0 3 7 0 236 3 4 0 3 5 0 3 6 0 3 7 0
@@ -225,67 +240,73 @@
225 }; 240 };
226 241
227 xlb@1f00 { 242 xlb@1f00 {
228 compatible = "mpc5200b-xlb\0mpc52xx-xlb"; 243 compatible = "mpc5200b-xlb\0mpc5200-xlb";
229 reg = <1f00 100>; 244 reg = <1f00 100>;
230 }; 245 };
231 246
232 serial@2000 { // PSC1 247 serial@2000 { // PSC1
233 device_type = "serial"; 248 device_type = "serial";
234 compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; 249 compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
235 port-number = <0>; // Logical port assignment 250 port-number = <0>; // Logical port assignment
251 cell-index = <0>;
236 reg = <2000 100>; 252 reg = <2000 100>;
237 interrupts = <2 1 0>; 253 interrupts = <2 1 0>;
238 interrupt-parent = <500>; 254 interrupt-parent = <500>;
239 }; 255 };
240 256
241 // PSC2 in spi mode example 257 // PSC2 in ac97 mode example
242 spi@2200 { // PSC2 258 //ac97@2200 { // PSC2
243 device_type = "spi"; 259 // device_type = "sound";
244 compatible = "mpc5200b-psc-spi\0mpc52xx-psc-spi"; 260 // compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97";
245 reg = <2200 100>; 261 // cell-index = <1>;
246 interrupts = <2 2 0>; 262 // reg = <2200 100>;
247 interrupt-parent = <500>; 263 // interrupts = <2 2 0>;
248 }; 264 // interrupt-parent = <500>;
265 //};
249 266
250 // PSC3 in CODEC mode example 267 // PSC3 in CODEC mode example
251 i2s@2400 { // PSC3 268 //i2s@2400 { // PSC3
252 device_type = "sound"; 269 // device_type = "sound";
253 compatible = "mpc5200b-psc-i2s\0mpc52xx-psc-i2s"; 270 // compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
254 reg = <2400 100>; 271 // cell-index = <2>;
255 interrupts = <2 3 0>; 272 // reg = <2400 100>;
256 interrupt-parent = <500>; 273 // interrupts = <2 3 0>;
257 }; 274 // interrupt-parent = <500>;
275 //};
258 276
259 // PSC4 unconfigured 277 // PSC4 in uart mode example
260 //serial@2600 { // PSC4 278 //serial@2600 { // PSC4
261 // device_type = "serial"; 279 // device_type = "serial";
262 // compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; 280 // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
281 // cell-index = <3>;
263 // reg = <2600 100>; 282 // reg = <2600 100>;
264 // interrupts = <2 b 0>; 283 // interrupts = <2 b 0>;
265 // interrupt-parent = <500>; 284 // interrupt-parent = <500>;
266 //}; 285 //};
267 286
268 // PSC5 unconfigured 287 // PSC5 in uart mode example
269 //serial@2800 { // PSC5 288 //serial@2800 { // PSC5
270 // device_type = "serial"; 289 // device_type = "serial";
271 // compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; 290 // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
291 // cell-index = <4>;
272 // reg = <2800 100>; 292 // reg = <2800 100>;
273 // interrupts = <2 c 0>; 293 // interrupts = <2 c 0>;
274 // interrupt-parent = <500>; 294 // interrupt-parent = <500>;
275 //}; 295 //};
276 296
277 // PSC6 in AC97 mode example 297 // PSC6 in spi mode example
278 ac97@2c00 { // PSC6 298 //spi@2c00 { // PSC6
279 device_type = "sound"; 299 // device_type = "spi";
280 compatible = "mpc5200b-psc-ac97\0mpc52xx-psc-ac97"; 300 // compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi";
281 reg = <2c00 100>; 301 // cell-index = <5>;
282 interrupts = <2 4 0>; 302 // reg = <2c00 100>;
283 interrupt-parent = <500>; 303 // interrupts = <2 4 0>;
284 }; 304 // interrupt-parent = <500>;
305 //};
285 306
286 ethernet@3000 { 307 ethernet@3000 {
287 device_type = "network"; 308 device_type = "network";
288 compatible = "mpc5200b-fec\0mpc52xx-fec"; 309 compatible = "mpc5200b-fec\0mpc5200-fec";
289 reg = <3000 800>; 310 reg = <3000 800>;
290 mac-address = [ 02 03 04 05 06 07 ]; // Bad! 311 mac-address = [ 02 03 04 05 06 07 ]; // Bad!
291 interrupts = <2 5 0>; 312 interrupts = <2 5 0>;
@@ -294,7 +315,7 @@
294 315
295 ata@3a00 { 316 ata@3a00 {
296 device_type = "ata"; 317 device_type = "ata";
297 compatible = "mpc5200b-ata\0mpc52xx-ata"; 318 compatible = "mpc5200b-ata\0mpc5200-ata";
298 reg = <3a00 100>; 319 reg = <3a00 100>;
299 interrupts = <2 7 0>; 320 interrupts = <2 7 0>;
300 interrupt-parent = <500>; 321 interrupt-parent = <500>;
@@ -302,7 +323,8 @@
302 323
303 i2c@3d00 { 324 i2c@3d00 {
304 device_type = "i2c"; 325 device_type = "i2c";
305 compatible = "mpc5200b-i2c\0mpc52xx-i2c"; 326 compatible = "mpc5200b-i2c\0mpc5200-i2c";
327 cell-index = <0>;
306 reg = <3d00 40>; 328 reg = <3d00 40>;
307 interrupts = <2 f 0>; 329 interrupts = <2 f 0>;
308 interrupt-parent = <500>; 330 interrupt-parent = <500>;
@@ -310,14 +332,15 @@
310 332
311 i2c@3d40 { 333 i2c@3d40 {
312 device_type = "i2c"; 334 device_type = "i2c";
313 compatible = "mpc5200b-i2c\0mpc52xx-i2c"; 335 compatible = "mpc5200b-i2c\0mpc5200-i2c";
336 cell-index = <1>;
314 reg = <3d40 40>; 337 reg = <3d40 40>;
315 interrupts = <2 10 0>; 338 interrupts = <2 10 0>;
316 interrupt-parent = <500>; 339 interrupt-parent = <500>;
317 }; 340 };
318 sram@8000 { 341 sram@8000 {
319 device_type = "sram"; 342 device_type = "sram";
320 compatible = "mpc5200b-sram\0mpc52xx-sram\0sram"; 343 compatible = "mpc5200b-sram\0mpc5200-sram\0sram";
321 reg = <8000 4000>; 344 reg = <8000 4000>;
322 }; 345 };
323 }; 346 };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
new file mode 100644
index 000000000000..3d2f5a06df3f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -0,0 +1,219 @@
1/*
2 * MPC8313E RDB Device Tree Source
3 *
4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "MPC8313ERDB";
14 compatible = "MPC83xx";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #cpus = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,8313@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <4000>; // L1, 16K
29 i-cache-size = <4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
33 32-bit;
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <00000000 08000000>; // 128MB at 0
40 };
41
42 soc8313@e0000000 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc";
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00000200>;
49 bus-frequency = <0>;
50
51 wdt@200 {
52 device_type = "watchdog";
53 compatible = "mpc83xx_wdt";
54 reg = <200 100>;
55 };
56
57 i2c@3000 {
58 device_type = "i2c";
59 compatible = "fsl-i2c";
60 reg = <3000 100>;
61 interrupts = <e 8>;
62 interrupt-parent = <700>;
63 dfsrr;
64 };
65
66 i2c@3100 {
67 device_type = "i2c";
68 compatible = "fsl-i2c";
69 reg = <3100 100>;
70 interrupts = <f 8>;
71 interrupt-parent = <700>;
72 dfsrr;
73 };
74
75 spi@7000 {
76 device_type = "spi";
77 compatible = "mpc83xx_spi";
78 reg = <7000 1000>;
79 interrupts = <10 8>;
80 interrupt-parent = <700>;
81 mode = <0>;
82 };
83
84 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
85 usb@23000 {
86 device_type = "usb";
87 compatible = "fsl-usb2-dr";
88 reg = <23000 1000>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 interrupt-parent = <700>;
92 interrupts = <26 2>;
93 phy_type = "utmi_wide";
94 };
95
96 mdio@24520 {
97 device_type = "mdio";
98 compatible = "gianfar";
99 reg = <24520 20>;
100 #address-cells = <1>;
101 #size-cells = <0>;
102 linux,phandle = <24520>;
103 ethernet-phy@1 {
104 linux,phandle = <2452001>;
105 interrupt-parent = <700>;
106 interrupts = <13 2>;
107 reg = <1>;
108 device_type = "ethernet-phy";
109 };
110 ethernet-phy@4 {
111 linux,phandle = <2452004>;
112 interrupt-parent = <700>;
113 interrupts = <14 2>;
114 reg = <4>;
115 device_type = "ethernet-phy";
116 };
117 };
118
119 ethernet@24000 {
120 device_type = "network";
121 model = "eTSEC";
122 compatible = "gianfar";
123 reg = <24000 1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <25 8 24 8 23 8>;
126 interrupt-parent = <700>;
127 phy-handle = <2452001>;
128 };
129
130 ethernet@25000 {
131 device_type = "network";
132 model = "eTSEC";
133 compatible = "gianfar";
134 reg = <25000 1000>;
135 local-mac-address = [ 00 00 00 00 00 00 ];
136 interrupts = <22 8 21 8 20 8>;
137 interrupt-parent = <700>;
138 phy-handle = <2452004>;
139 };
140
141 serial@4500 {
142 device_type = "serial";
143 compatible = "ns16550";
144 reg = <4500 100>;
145 clock-frequency = <0>;
146 interrupts = <9 8>;
147 interrupt-parent = <700>;
148 };
149
150 serial@4600 {
151 device_type = "serial";
152 compatible = "ns16550";
153 reg = <4600 100>;
154 clock-frequency = <0>;
155 interrupts = <a 8>;
156 interrupt-parent = <700>;
157 };
158
159 pci@8500 {
160 interrupt-map-mask = <f800 0 0 7>;
161 interrupt-map = <
162
163 /* IDSEL 0x0E -mini PCI */
164 7000 0 0 1 700 12 8
165 7000 0 0 2 700 12 8
166 7000 0 0 3 700 12 8
167 7000 0 0 4 700 12 8
168
169 /* IDSEL 0x0F - PCI slot */
170 7800 0 0 1 700 11 8
171 7800 0 0 2 700 12 8
172 7800 0 0 3 700 11 8
173 7800 0 0 4 700 12 8>;
174 interrupt-parent = <700>;
175 interrupts = <42 8>;
176 bus-range = <0 0>;
177 ranges = <02000000 0 90000000 90000000 0 10000000
178 42000000 0 80000000 80000000 0 10000000
179 01000000 0 00000000 e2000000 0 00100000>;
180 clock-frequency = <3f940aa>;
181 #interrupt-cells = <1>;
182 #size-cells = <2>;
183 #address-cells = <3>;
184 reg = <8500 100>;
185 compatible = "83xx";
186 device_type = "pci";
187 };
188
189 crypto@30000 {
190 device_type = "crypto";
191 model = "SEC2";
192 compatible = "talitos";
193 reg = <30000 7000>;
194 interrupts = <b 8>;
195 interrupt-parent = <700>;
196 /* Rev. 2.2 */
197 num-channels = <1>;
198 channel-fifo-len = <18>;
199 exec-units-mask = <0000004c>;
200 descriptor-types-mask = <0122003f>;
201 };
202
203 /* IPIC
204 * interrupts cell = <intr #, sense>
205 * sense values match linux IORESOURCE_IRQ_* defines:
206 * sense == 8: Level, low assertion
207 * sense == 2: Edge, high-to-low change
208 */
209 pic@700 {
210 linux,phandle = <700>;
211 interrupt-controller;
212 #address-cells = <0>;
213 #interrupt-cells = <2>;
214 reg = <700 100>;
215 built-in;
216 device_type = "ipic";
217 };
218 };
219};
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
new file mode 100644
index 000000000000..3190774de1d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -0,0 +1,187 @@
1/*
2 * MPC8349E-mITX-GP Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11/ {
12 model = "MPC8349EMITXGP";
13 compatible = "MPC834xMITXGP";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 cpus {
18 #cpus = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,8349@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <20>;
26 i-cache-line-size = <20>;
27 d-cache-size = <8000>;
28 i-cache-size = <8000>;
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
32 32-bit;
33 };
34 };
35
36 memory {
37 device_type = "memory";
38 reg = <00000000 10000000>;
39 };
40
41 soc8349@e0000000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 #interrupt-cells = <2>;
45 device_type = "soc";
46 ranges = <0 e0000000 00100000>;
47 reg = <e0000000 00000200>;
48 bus-frequency = <0>; // from bootloader
49
50 wdt@200 {
51 device_type = "watchdog";
52 compatible = "mpc83xx_wdt";
53 reg = <200 100>;
54 };
55
56 i2c@3000 {
57 device_type = "i2c";
58 compatible = "fsl-i2c";
59 reg = <3000 100>;
60 interrupts = <e 8>;
61 interrupt-parent = <700>;
62 dfsrr;
63 };
64
65 i2c@3100 {
66 device_type = "i2c";
67 compatible = "fsl-i2c";
68 reg = <3100 100>;
69 interrupts = <f 8>;
70 interrupt-parent = <700>;
71 dfsrr;
72 };
73
74 spi@7000 {
75 device_type = "spi";
76 compatible = "mpc83xx_spi";
77 reg = <7000 1000>;
78 interrupts = <10 8>;
79 interrupt-parent = <700>;
80 mode = <0>;
81 };
82
83 usb@23000 {
84 device_type = "usb";
85 compatible = "fsl-usb2-dr";
86 reg = <23000 1000>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 interrupt-parent = <700>;
90 interrupts = <26 2>;
91 dr_mode = "otg";
92 phy_type = "ulpi";
93 };
94
95 mdio@24520 {
96 device_type = "mdio";
97 compatible = "gianfar";
98 reg = <24520 20>;
99 #address-cells = <1>;
100 #size-cells = <0>;
101 linux,phandle = <24520>;
102
103 /* Vitesse 8201 */
104 ethernet-phy@1c {
105 linux,phandle = <245201c>;
106 interrupt-parent = <700>;
107 interrupts = <12 2>;
108 reg = <1c>;
109 device_type = "ethernet-phy";
110 };
111 };
112
113 ethernet@24000 {
114 device_type = "network";
115 model = "TSEC";
116 compatible = "gianfar";
117 reg = <24000 1000>;
118 local-mac-address = [ 00 00 00 00 00 00 ];
119 interrupts = <20 8 21 8 22 8>;
120 interrupt-parent = <700>;
121 phy-handle = <245201c>;
122 };
123
124 serial@4500 {
125 device_type = "serial";
126 compatible = "ns16550";
127 reg = <4500 100>;
128 clock-frequency = <0>; // from bootloader
129 interrupts = <9 8>;
130 interrupt-parent = <700>;
131 };
132
133 serial@4600 {
134 device_type = "serial";
135 compatible = "ns16550";
136 reg = <4600 100>;
137 clock-frequency = <0>; // from bootloader
138 interrupts = <a 8>;
139 interrupt-parent = <700>;
140 };
141
142 pci@8600 {
143 interrupt-map-mask = <f800 0 0 7>;
144 interrupt-map = <
145 /* IDSEL 0x0F - PCI Slot */
146 7800 0 0 1 700 14 8 /* PCI_INTA */
147 7800 0 0 2 700 15 8 /* PCI_INTB */
148 >;
149 interrupt-parent = <700>;
150 interrupts = <43 8>;
151 bus-range = <1 1>;
152 ranges = <42000000 0 a0000000 a0000000 0 10000000
153 02000000 0 b0000000 b0000000 0 10000000
154 01000000 0 00000000 e3000000 0 01000000>;
155 clock-frequency = <3f940aa>;
156 #interrupt-cells = <1>;
157 #size-cells = <2>;
158 #address-cells = <3>;
159 reg = <8600 100>;
160 compatible = "83xx";
161 device_type = "pci";
162 };
163
164 crypto@30000 {
165 device_type = "crypto";
166 model = "SEC2";
167 compatible = "talitos";
168 reg = <30000 10000>;
169 interrupts = <b 8>;
170 interrupt-parent = <700>;
171 num-channels = <4>;
172 channel-fifo-len = <18>;
173 exec-units-mask = <0000007e>;
174 descriptor-types-mask = <01010ebf>;
175 };
176
177 pic@700 {
178 linux,phandle = <700>;
179 interrupt-controller;
180 #address-cells = <0>;
181 #interrupt-cells = <2>;
182 reg = <700 100>;
183 built-in;
184 device_type = "ipic";
185 };
186 };
187};
diff --git a/arch/powerpc/boot/dts/mpc8349emds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index efceb3432653..dc121b3cb4a9 100644
--- a/arch/powerpc/boot/dts/mpc8349emds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -39,6 +39,11 @@
39 reg = <00000000 10000000>; // 256MB at 0 39 reg = <00000000 10000000>; // 256MB at 0
40 }; 40 };
41 41
42 bcsr@e2400000 {
43 device_type = "board-control";
44 reg = <e2400000 8000>;
45 };
46
42 soc8349@e0000000 { 47 soc8349@e0000000 {
43 #address-cells = <1>; 48 #address-cells = <1>;
44 #size-cells = <1>; 49 #size-cells = <1>;
@@ -103,6 +108,7 @@
103 #size-cells = <0>; 108 #size-cells = <0>;
104 interrupt-parent = <700>; 109 interrupt-parent = <700>;
105 interrupts = <26 2>; 110 interrupts = <26 2>;
111 dr_mode = "otg";
106 phy_type = "ulpi"; 112 phy_type = "ulpi";
107 }; 113 };
108 114
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
new file mode 100644
index 000000000000..06d24653e422
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -0,0 +1,380 @@
1/*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/*
14/memreserve/ 00000000 1000000;
15*/
16
17/ {
18 model = "MPC8568EMDS";
19 compatible = "MPC85xxMDS";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 linux,phandle = <100>;
23
24 cpus {
25 #cpus = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
28 linux,phandle = <200>;
29
30 PowerPC,8568@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <20>; // 32 bytes
34 i-cache-line-size = <20>; // 32 bytes
35 d-cache-size = <8000>; // L1, 32K
36 i-cache-size = <8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 32-bit;
41 linux,phandle = <201>;
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 linux,phandle = <300>;
48 reg = <00000000 10000000>;
49 };
50
51 bcsr@f8000000 {
52 device_type = "board-control";
53 reg = <f8000000 8000>;
54 };
55
56 soc8568@e0000000 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 #interrupt-cells = <2>;
60 device_type = "soc";
61 ranges = <0 e0000000 00100000>;
62 reg = <e0000000 00100000>;
63 bus-frequency = <0>;
64
65 i2c@3000 {
66 device_type = "i2c";
67 compatible = "fsl-i2c";
68 reg = <3000 100>;
69 interrupts = <1b 2>;
70 interrupt-parent = <40000>;
71 dfsrr;
72 };
73
74 i2c@3100 {
75 device_type = "i2c";
76 compatible = "fsl-i2c";
77 reg = <3100 100>;
78 interrupts = <1b 2>;
79 interrupt-parent = <40000>;
80 dfsrr;
81 };
82
83 mdio@24520 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 device_type = "mdio";
87 compatible = "gianfar";
88 reg = <24520 20>;
89 linux,phandle = <24520>;
90 ethernet-phy@0 {
91 linux,phandle = <2452000>;
92 interrupt-parent = <40000>;
93 interrupts = <31 1>;
94 reg = <0>;
95 device_type = "ethernet-phy";
96 };
97 ethernet-phy@1 {
98 linux,phandle = <2452001>;
99 interrupt-parent = <40000>;
100 interrupts = <32 1>;
101 reg = <1>;
102 device_type = "ethernet-phy";
103 };
104
105 ethernet-phy@2 {
106 linux,phandle = <2452002>;
107 interrupt-parent = <40000>;
108 interrupts = <31 1>;
109 reg = <2>;
110 device_type = "ethernet-phy";
111 };
112 ethernet-phy@3 {
113 linux,phandle = <2452003>;
114 interrupt-parent = <40000>;
115 interrupts = <32 1>;
116 reg = <3>;
117 device_type = "ethernet-phy";
118 };
119 };
120
121 ethernet@24000 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 device_type = "network";
125 model = "eTSEC";
126 compatible = "gianfar";
127 reg = <24000 1000>;
128 mac-address = [ 00 00 00 00 00 00 ];
129 interrupts = <d 2 e 2 12 2>;
130 interrupt-parent = <40000>;
131 phy-handle = <2452002>;
132 };
133
134 ethernet@25000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 device_type = "network";
138 model = "eTSEC";
139 compatible = "gianfar";
140 reg = <25000 1000>;
141 mac-address = [ 00 00 00 00 00 00];
142 interrupts = <13 2 14 2 18 2>;
143 interrupt-parent = <40000>;
144 phy-handle = <2452003>;
145 };
146
147 serial@4500 {
148 device_type = "serial";
149 compatible = "ns16550";
150 reg = <4500 100>;
151 clock-frequency = <0>;
152 interrupts = <1a 2>;
153 interrupt-parent = <40000>;
154 };
155
156 serial@4600 {
157 device_type = "serial";
158 compatible = "ns16550";
159 reg = <4600 100>;
160 clock-frequency = <0>;
161 interrupts = <1a 2>;
162 interrupt-parent = <40000>;
163 };
164
165 crypto@30000 {
166 device_type = "crypto";
167 model = "SEC2";
168 compatible = "talitos";
169 reg = <30000 f000>;
170 interrupts = <1d 2>;
171 interrupt-parent = <40000>;
172 num-channels = <4>;
173 channel-fifo-len = <18>;
174 exec-units-mask = <000000fe>;
175 descriptor-types-mask = <012b0ebf>;
176 };
177
178 pic@40000 {
179 linux,phandle = <40000>;
180 clock-frequency = <0>;
181 interrupt-controller;
182 #address-cells = <0>;
183 #interrupt-cells = <2>;
184 reg = <40000 40000>;
185 built-in;
186 compatible = "chrp,open-pic";
187 device_type = "open-pic";
188 big-endian;
189 };
190 par_io@e0100 {
191 reg = <e0100 100>;
192 device_type = "par_io";
193 num-ports = <7>;
194
195 ucc_pin@01 {
196 linux,phandle = <e010001>;
197 pio-map = <
198 /* port pin dir open_drain assignment has_irq */
199 4 0a 1 0 2 0 /* TxD0 */
200 4 09 1 0 2 0 /* TxD1 */
201 4 08 1 0 2 0 /* TxD2 */
202 4 07 1 0 2 0 /* TxD3 */
203 4 17 1 0 2 0 /* TxD4 */
204 4 16 1 0 2 0 /* TxD5 */
205 4 15 1 0 2 0 /* TxD6 */
206 4 14 1 0 2 0 /* TxD7 */
207 4 0f 2 0 2 0 /* RxD0 */
208 4 0e 2 0 2 0 /* RxD1 */
209 4 0d 2 0 2 0 /* RxD2 */
210 4 0c 2 0 2 0 /* RxD3 */
211 4 1d 2 0 2 0 /* RxD4 */
212 4 1c 2 0 2 0 /* RxD5 */
213 4 1b 2 0 2 0 /* RxD6 */
214 4 1a 2 0 2 0 /* RxD7 */
215 4 0b 1 0 2 0 /* TX_EN */
216 4 18 1 0 2 0 /* TX_ER */
217 4 0f 2 0 2 0 /* RX_DV */
218 4 1e 2 0 2 0 /* RX_ER */
219 4 11 2 0 2 0 /* RX_CLK */
220 4 13 1 0 2 0 /* GTX_CLK */
221 1 1f 2 0 3 0>; /* GTX125 */
222 };
223 ucc_pin@02 {
224 linux,phandle = <e010002>;
225 pio-map = <
226 /* port pin dir open_drain assignment has_irq */
227 5 0a 1 0 2 0 /* TxD0 */
228 5 09 1 0 2 0 /* TxD1 */
229 5 08 1 0 2 0 /* TxD2 */
230 5 07 1 0 2 0 /* TxD3 */
231 5 17 1 0 2 0 /* TxD4 */
232 5 16 1 0 2 0 /* TxD5 */
233 5 15 1 0 2 0 /* TxD6 */
234 5 14 1 0 2 0 /* TxD7 */
235 5 0f 2 0 2 0 /* RxD0 */
236 5 0e 2 0 2 0 /* RxD1 */
237 5 0d 2 0 2 0 /* RxD2 */
238 5 0c 2 0 2 0 /* RxD3 */
239 5 1d 2 0 2 0 /* RxD4 */
240 5 1c 2 0 2 0 /* RxD5 */
241 5 1b 2 0 2 0 /* RxD6 */
242 5 1a 2 0 2 0 /* RxD7 */
243 5 0b 1 0 2 0 /* TX_EN */
244 5 18 1 0 2 0 /* TX_ER */
245 5 10 2 0 2 0 /* RX_DV */
246 5 1e 2 0 2 0 /* RX_ER */
247 5 11 2 0 2 0 /* RX_CLK */
248 5 13 1 0 2 0 /* GTX_CLK */
249 1 1f 2 0 3 0 /* GTX125 */
250 4 06 3 0 2 0 /* MDIO */
251 4 05 1 0 2 0>; /* MDC */
252 };
253 };
254 };
255
256 qe@e0080000 {
257 #address-cells = <1>;
258 #size-cells = <1>;
259 device_type = "qe";
260 model = "QE";
261 ranges = <0 e0080000 00040000>;
262 reg = <e0080000 480>;
263 brg-frequency = <0>;
264 bus-frequency = <179A7B00>;
265
266 muram@10000 {
267 device_type = "muram";
268 ranges = <0 00010000 0000c000>;
269
270 data-only@0{
271 reg = <0 c000>;
272 };
273 };
274
275 spi@4c0 {
276 device_type = "spi";
277 compatible = "fsl_spi";
278 reg = <4c0 40>;
279 interrupts = <2>;
280 interrupt-parent = <80>;
281 mode = "cpu";
282 };
283
284 spi@500 {
285 device_type = "spi";
286 compatible = "fsl_spi";
287 reg = <500 40>;
288 interrupts = <1>;
289 interrupt-parent = <80>;
290 mode = "cpu";
291 };
292
293 ucc@2000 {
294 device_type = "network";
295 compatible = "ucc_geth";
296 model = "UCC";
297 device-id = <1>;
298 reg = <2000 200>;
299 interrupts = <20>;
300 interrupt-parent = <80>;
301 mac-address = [ 00 04 9f 00 23 23 ];
302 rx-clock = <0>;
303 tx-clock = <19>;
304 phy-handle = <212000>;
305 pio-handle = <e010001>;
306 };
307
308 ucc@3000 {
309 device_type = "network";
310 compatible = "ucc_geth";
311 model = "UCC";
312 device-id = <2>;
313 reg = <3000 200>;
314 interrupts = <21>;
315 interrupt-parent = <80>;
316 mac-address = [ 00 11 22 33 44 55 ];
317 rx-clock = <0>;
318 tx-clock = <14>;
319 phy-handle = <212001>;
320 pio-handle = <e010002>;
321 };
322
323 mdio@2120 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 reg = <2120 18>;
327 device_type = "mdio";
328 compatible = "ucc_geth_phy";
329
330 /* These are the same PHYs as on
331 * gianfar's MDIO bus */
332 ethernet-phy@00 {
333 linux,phandle = <212000>;
334 interrupt-parent = <40000>;
335 interrupts = <31 1>;
336 reg = <0>;
337 device_type = "ethernet-phy";
338 interface = <6>; //ENET_1000_GMII
339 };
340 ethernet-phy@01 {
341 linux,phandle = <212001>;
342 interrupt-parent = <40000>;
343 interrupts = <32 1>;
344 reg = <1>;
345 device_type = "ethernet-phy";
346 interface = <6>;
347 };
348 ethernet-phy@02 {
349 linux,phandle = <212002>;
350 interrupt-parent = <40000>;
351 interrupts = <31 1>;
352 reg = <2>;
353 device_type = "ethernet-phy";
354 interface = <6>; //ENET_1000_GMII
355 };
356 ethernet-phy@03 {
357 linux,phandle = <212003>;
358 interrupt-parent = <40000>;
359 interrupts = <32 1>;
360 reg = <3>;
361 device_type = "ethernet-phy";
362 interface = <6>; //ENET_1000_GMII
363 };
364 };
365
366 qeic@80 {
367 linux,phandle = <80>;
368 interrupt-controller;
369 device_type = "qeic";
370 #address-cells = <0>;
371 #interrupt-cells = <1>;
372 reg = <80 80>;
373 built-in;
374 big-endian;
375 interrupts = <1e 2 1e 2>; //high:30 low:30
376 interrupt-parent = <40000>;
377 };
378
379 };
380};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 12:28:57 -0500