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-rw-r--r--arch/powerpc/boot/Makefile7
-rw-r--r--arch/powerpc/boot/dts/arches.dts12
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts2
-rw-r--r--arch/powerpc/boot/dts/eiger.dts6
-rw-r--r--arch/powerpc/boot/dts/gamecube.dts114
-rw-r--r--arch/powerpc/boot/dts/gef_ppc9a.dts26
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts29
-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts76
-rw-r--r--arch/powerpc/boot/dts/glacier.dts82
-rw-r--r--arch/powerpc/boot/dts/haleakala.dts2
-rw-r--r--arch/powerpc/boot/dts/katmai.dts157
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts4
-rw-r--r--arch/powerpc/boot/dts/kmeter1.dts9
-rw-r--r--arch/powerpc/boot/dts/makalu.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts55
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts27
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts9
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts9
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts82
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts9
-rw-r--r--arch/powerpc/boot/dts/mpc836x_rdk.dts9
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts184
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts158
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts26
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dts477
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts363
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts184
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts554
-rw-r--r--arch/powerpc/boot/dts/redwood.dts1
-rw-r--r--arch/powerpc/boot/dts/warp.dts2
-rw-r--r--arch/powerpc/boot/dts/wii.dts218
-rw-r--r--arch/powerpc/boot/dts/yosemite.dts14
-rw-r--r--arch/powerpc/boot/gamecube-head.S111
-rw-r--r--arch/powerpc/boot/gamecube.c35
-rw-r--r--arch/powerpc/boot/ugecon.c147
-rw-r--r--arch/powerpc/boot/ugecon.h24
-rw-r--r--arch/powerpc/boot/wii-head.S142
-rw-r--r--arch/powerpc/boot/wii.c158
-rwxr-xr-xarch/powerpc/boot/wrapper11
39 files changed, 3355 insertions, 184 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 7bfc8ad87798..bb2465bcb327 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -66,7 +66,7 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
66 gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \ 66 gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
67 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \ 67 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
68 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \ 68 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
69 fsl-soc.c mpc8xx.c pq2.c 69 fsl-soc.c mpc8xx.c pq2.c ugecon.c
70src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \ 70src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
71 cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \ 71 cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \
72 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ 72 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
@@ -76,7 +76,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
76 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ 76 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
77 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ 77 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
78 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ 78 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
79 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c 79 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
80 gamecube-head.S gamecube.c wii-head.S wii.c
80src-boot := $(src-wlib) $(src-plat) empty.c 81src-boot := $(src-wlib) $(src-plat) empty.c
81 82
82src-boot := $(addprefix $(obj)/, $(src-boot)) 83src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -254,6 +255,8 @@ image-$(CONFIG_KSI8560) += cuImage.ksi8560
254image-$(CONFIG_STORCENTER) += cuImage.storcenter 255image-$(CONFIG_STORCENTER) += cuImage.storcenter
255image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2 256image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
256image-$(CONFIG_PPC_C2K) += cuImage.c2k 257image-$(CONFIG_PPC_C2K) += cuImage.c2k
258image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
259image-$(CONFIG_WII) += dtbImage.wii
257 260
258# Board port in arch/powerpc/platform/amigaone/Kconfig 261# Board port in arch/powerpc/platform/amigaone/Kconfig
259image-$(CONFIG_AMIGAONE) += cuImage.amigaone 262image-$(CONFIG_AMIGAONE) += cuImage.amigaone
diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index 414ef8b7e575..30f41204acfa 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -60,6 +60,7 @@
60 d-cache-size = <32768>; 60 d-cache-size = <32768>;
61 dcr-controller; 61 dcr-controller;
62 dcr-access-method = "native"; 62 dcr-access-method = "native";
63 next-level-cache = <&L2C0>;
63 }; 64 };
64 }; 65 };
65 66
@@ -146,6 +147,13 @@
146 dcr-reg = <0x010 0x002>; 147 dcr-reg = <0x010 0x002>;
147 }; 148 };
148 149
150 CRYPTO: crypto@180000 {
151 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
152 reg = <4 0x00180000 0x80400>;
153 interrupt-parent = <&UIC0>;
154 interrupts = <0x1d 0x4>;
155 };
156
149 MAL0: mcmal { 157 MAL0: mcmal {
150 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 158 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
151 dcr-reg = <0x180 0x062>; 159 dcr-reg = <0x180 0x062>;
@@ -274,6 +282,7 @@
274 max-frame-size = <9000>; 282 max-frame-size = <9000>;
275 rx-fifo-size = <4096>; 283 rx-fifo-size = <4096>;
276 tx-fifo-size = <2048>; 284 tx-fifo-size = <2048>;
285 rx-fifo-size-gige = <16384>;
277 phy-mode = "sgmii"; 286 phy-mode = "sgmii";
278 phy-map = <0xffffffff>; 287 phy-map = <0xffffffff>;
279 gpcs-address = <0x0000000a>; 288 gpcs-address = <0x0000000a>;
@@ -302,6 +311,7 @@
302 max-frame-size = <9000>; 311 max-frame-size = <9000>;
303 rx-fifo-size = <4096>; 312 rx-fifo-size = <4096>;
304 tx-fifo-size = <2048>; 313 tx-fifo-size = <2048>;
314 rx-fifo-size-gige = <16384>;
305 phy-mode = "sgmii"; 315 phy-mode = "sgmii";
306 phy-map = <0x00000000>; 316 phy-map = <0x00000000>;
307 gpcs-address = <0x0000000b>; 317 gpcs-address = <0x0000000b>;
@@ -331,6 +341,8 @@
331 max-frame-size = <9000>; 341 max-frame-size = <9000>;
332 rx-fifo-size = <4096>; 342 rx-fifo-size = <4096>;
333 tx-fifo-size = <2048>; 343 tx-fifo-size = <2048>;
344 rx-fifo-size-gige = <16384>;
345 tx-fifo-size-gige = <16384>; /* emac2&3 only */
334 phy-mode = "sgmii"; 346 phy-mode = "sgmii";
335 phy-map = <0x00000001>; 347 phy-map = <0x00000001>;
336 gpcs-address = <0x0000000C>; 348 gpcs-address = <0x0000000C>;
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index c920170b7dfe..cd56bb5b347b 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -352,6 +352,7 @@
352 max-frame-size = <9000>; 352 max-frame-size = <9000>;
353 rx-fifo-size = <4096>; 353 rx-fifo-size = <4096>;
354 tx-fifo-size = <2048>; 354 tx-fifo-size = <2048>;
355 rx-fifo-size-gige = <16384>;
355 phy-mode = "rgmii"; 356 phy-mode = "rgmii";
356 phy-map = <0x00000000>; 357 phy-map = <0x00000000>;
357 rgmii-device = <&RGMII0>; 358 rgmii-device = <&RGMII0>;
@@ -381,6 +382,7 @@
381 max-frame-size = <9000>; 382 max-frame-size = <9000>;
382 rx-fifo-size = <4096>; 383 rx-fifo-size = <4096>;
383 tx-fifo-size = <2048>; 384 tx-fifo-size = <2048>;
385 rx-fifo-size-gige = <16384>;
384 phy-mode = "rgmii"; 386 phy-mode = "rgmii";
385 phy-map = <0x00000000>; 387 phy-map = <0x00000000>;
386 rgmii-device = <&RGMII0>; 388 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/eiger.dts b/arch/powerpc/boot/dts/eiger.dts
index c4a934f2e886..48bcf7187924 100644
--- a/arch/powerpc/boot/dts/eiger.dts
+++ b/arch/powerpc/boot/dts/eiger.dts
@@ -316,6 +316,7 @@
316 max-frame-size = <9000>; 316 max-frame-size = <9000>;
317 rx-fifo-size = <4096>; 317 rx-fifo-size = <4096>;
318 tx-fifo-size = <2048>; 318 tx-fifo-size = <2048>;
319 rx-fifo-size-gige = <16384>;
319 phy-mode = "rgmii"; 320 phy-mode = "rgmii";
320 phy-map = <0x00000000>; 321 phy-map = <0x00000000>;
321 rgmii-device = <&RGMII0>; 322 rgmii-device = <&RGMII0>;
@@ -345,6 +346,7 @@
345 max-frame-size = <9000>; 346 max-frame-size = <9000>;
346 rx-fifo-size = <4096>; 347 rx-fifo-size = <4096>;
347 tx-fifo-size = <2048>; 348 tx-fifo-size = <2048>;
349 rx-fifo-size-gige = <16384>;
348 phy-mode = "rgmii"; 350 phy-mode = "rgmii";
349 phy-map = <0x00000000>; 351 phy-map = <0x00000000>;
350 rgmii-device = <&RGMII0>; 352 rgmii-device = <&RGMII0>;
@@ -375,6 +377,8 @@
375 max-frame-size = <9000>; 377 max-frame-size = <9000>;
376 rx-fifo-size = <4096>; 378 rx-fifo-size = <4096>;
377 tx-fifo-size = <2048>; 379 tx-fifo-size = <2048>;
380 rx-fifo-size-gige = <16384>;
381 tx-fifo-size-gige = <16384>; /* emac2&3 only */
378 phy-mode = "rgmii"; 382 phy-mode = "rgmii";
379 phy-map = <0x00000000>; 383 phy-map = <0x00000000>;
380 rgmii-device = <&RGMII1>; 384 rgmii-device = <&RGMII1>;
@@ -403,6 +407,8 @@
403 max-frame-size = <9000>; 407 max-frame-size = <9000>;
404 rx-fifo-size = <4096>; 408 rx-fifo-size = <4096>;
405 tx-fifo-size = <2048>; 409 tx-fifo-size = <2048>;
410 rx-fifo-size-gige = <16384>;
411 tx-fifo-size-gige = <16384>; /* emac2&3 only */
406 phy-mode = "rgmii"; 412 phy-mode = "rgmii";
407 phy-map = <0x00000000>; 413 phy-map = <0x00000000>;
408 rgmii-device = <&RGMII1>; 414 rgmii-device = <&RGMII1>;
diff --git a/arch/powerpc/boot/dts/gamecube.dts b/arch/powerpc/boot/dts/gamecube.dts
new file mode 100644
index 000000000000..ef3be0e58b02
--- /dev/null
+++ b/arch/powerpc/boot/dts/gamecube.dts
@@ -0,0 +1,114 @@
1/*
2 * arch/powerpc/boot/dts/gamecube.dts
3 *
4 * Nintendo GameCube platform device tree source
5 * Copyright (C) 2007-2009 The GameCube Linux Team
6 * Copyright (C) 2007,2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15/dts-v1/;
16
17/ {
18 model = "nintendo,gamecube";
19 compatible = "nintendo,gamecube";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 chosen {
24 bootargs = "root=/dev/gcnsda2 rootwait udbg-immortal";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x01800000>;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,gekko@0 {
37 device_type = "cpu";
38 reg = <0>;
39 clock-frequency = <486000000>; /* 486MHz */
40 bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
41 timebase-frequency = <40500000>; /* 162MHz / 4 */
42 i-cache-line-size = <32>;
43 d-cache-line-size = <32>;
44 i-cache-size = <32768>;
45 d-cache-size = <32768>;
46 };
47 };
48
49 /* devices contained int the flipper chipset */
50 flipper {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "nintendo,flipper";
54 ranges = <0x0c000000 0x0c000000 0x00010000>;
55 interrupt-parent = <&PIC>;
56
57 video@0c002000 {
58 compatible = "nintendo,flipper-vi";
59 reg = <0x0c002000 0x100>;
60 interrupts = <8>;
61 };
62
63 processor-interface@0c003000 {
64 compatible = "nintendo,flipper-pi";
65 reg = <0x0c003000 0x100>;
66
67 PIC: pic {
68 #interrupt-cells = <1>;
69 compatible = "nintendo,flipper-pic";
70 interrupt-controller;
71 };
72 };
73
74 dsp@0c005000 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "nintendo,flipper-dsp";
78 reg = <0x0c005000 0x200>;
79 interrupts = <6>;
80
81 memory@0 {
82 compatible = "nintendo,flipper-aram";
83 reg = <0 0x1000000>; /* 16MB */
84 };
85 };
86
87 disk@0c006000 {
88 compatible = "nintendo,flipper-di";
89 reg = <0x0c006000 0x40>;
90 interrupts = <2>;
91 };
92
93 audio@0c006c00 {
94 compatible = "nintendo,flipper-ai";
95 reg = <0x0c006c00 0x20>;
96 interrupts = <6>;
97 };
98
99 gamepad-controller@0c006400 {
100 compatible = "nintendo,flipper-si";
101 reg = <0x0c006400 0x100>;
102 interrupts = <3>;
103 };
104
105 /* External Interface bus */
106 exi@0c006800 {
107 compatible = "nintendo,flipper-exi";
108 reg = <0x0c006800 0x40>;
109 virtual-reg = <0x0c006800>;
110 interrupts = <4>;
111 };
112 };
113};
114
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 910944edd886..83f4b79dff85 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * GE Fanuc PPC9A Device Tree Source 2 * GE PPC9A Device Tree Source
3 * 3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. 4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -118,6 +118,12 @@
118 }; 118 };
119 }; 119 };
120 120
121 nvram@3,0 {
122 device_type = "nvram";
123 compatible = "simtek,stk14ca8";
124 reg = <0x3 0x0 0x20000>;
125 };
126
121 fpga@4,0 { 127 fpga@4,0 {
122 compatible = "gef,ppc9a-fpga-regs"; 128 compatible = "gef,ppc9a-fpga-regs";
123 reg = <0x4 0x0 0x40>; 129 reg = <0x4 0x0 0x40>;
@@ -335,6 +341,22 @@
335 device_type = "open-pic"; 341 device_type = "open-pic";
336 }; 342 };
337 343
344 msi@41600 {
345 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
346 reg = <0x41600 0x80>;
347 msi-available-ranges = <0 0x100>;
348 interrupts = <
349 0xe0 0
350 0xe1 0
351 0xe2 0
352 0xe3 0
353 0xe4 0
354 0xe5 0
355 0xe6 0
356 0xe7 0>;
357 interrupt-parent = <&mpic>;
358 };
359
338 global-utilities@e0000 { 360 global-utilities@e0000 {
339 compatible = "fsl,mpc8641-guts"; 361 compatible = "fsl,mpc8641-guts";
340 reg = <0xe0000 0x1000>; 362 reg = <0xe0000 0x1000>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 2107d3c7cfe1..fc3a331dd392 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * GE Fanuc SBC310 Device Tree Source 2 * GE SBC310 Device Tree Source
3 * 3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. 4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -32,6 +32,7 @@
32 serial0 = &serial0; 32 serial0 = &serial0;
33 serial1 = &serial1; 33 serial1 = &serial1;
34 pci0 = &pci0; 34 pci0 = &pci0;
35 pci1 = &pci1;
35 }; 36 };
36 37
37 cpus { 38 cpus {
@@ -115,6 +116,12 @@
115 }; 116 };
116 }; 117 };
117 118
119 nvram@3,0 {
120 device_type = "nvram";
121 compatible = "simtek,stk14ca8";
122 reg = <0x3 0x0 0x20000>;
123 };
124
118 fpga@4,0 { 125 fpga@4,0 {
119 compatible = "gef,fpga-regs"; 126 compatible = "gef,fpga-regs";
120 reg = <0x4 0x0 0x40>; 127 reg = <0x4 0x0 0x40>;
@@ -332,6 +339,22 @@
332 device_type = "open-pic"; 339 device_type = "open-pic";
333 }; 340 };
334 341
342 msi@41600 {
343 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
344 reg = <0x41600 0x80>;
345 msi-available-ranges = <0 0x100>;
346 interrupts = <
347 0xe0 0
348 0xe1 0
349 0xe2 0
350 0xe3 0
351 0xe4 0
352 0xe5 0
353 0xe6 0
354 0xe7 0>;
355 interrupt-parent = <&mpic>;
356 };
357
335 global-utilities@e0000 { 358 global-utilities@e0000 {
336 compatible = "fsl,mpc8641-guts"; 359 compatible = "fsl,mpc8641-guts";
337 reg = <0xe0000 0x1000>; 360 reg = <0xe0000 0x1000>;
@@ -352,7 +375,7 @@
352 clock-frequency = <33333333>; 375 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>; 376 interrupt-parent = <&mpic>;
354 interrupts = <0x18 0x2>; 377 interrupts = <0x18 0x2>;
355 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 378 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
356 interrupt-map = < 379 interrupt-map = <
357 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 380 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
358 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 381 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 35a63183eecc..c0671cc98125 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * GE Fanuc SBC610 Device Tree Source 2 * GE SBC610 Device Tree Source
3 * 3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. 4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -75,14 +75,54 @@
75 interrupts = <19 2>; 75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 77
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0 79 1 0 0xe8000000 0x08000000 // Paged Flash 0
80 2 0 0xe0000000 0x08000000 // Paged Flash 1 80 2 0 0xe0000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM 81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00008000 // FPGA 82 4 0 0xfc000000 0x00008000 // FPGA
83 5 0 0xfc008000 0x00008000 // AFIX FPGA 83 5 0 0xfc008000 0x00008000 // AFIX FPGA
84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) 84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) 85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
86
87 /* flash@0,0 is a mirror of part of the memory in flash@1,0
88 flash@0,0 {
89 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
90 reg = <0x0 0x0 0x1000000>;
91 bank-width = <4>;
92 device-width = <2>;
93 #address-cells = <1>;
94 #size-cells = <1>;
95 partition@0 {
96 label = "firmware";
97 reg = <0x0 0x1000000>;
98 read-only;
99 };
100 };
101 */
102
103 flash@1,0 {
104 compatible = "gef,sbc610-paged-flash", "cfi-flash";
105 reg = <0x1 0x0 0x8000000>;
106 bank-width = <4>;
107 device-width = <2>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 partition@0 {
111 label = "user";
112 reg = <0x0 0x7800000>;
113 };
114 partition@7800000 {
115 label = "firmware";
116 reg = <0x7800000 0x800000>;
117 read-only;
118 };
119 };
120
121 nvram@3,0 {
122 device_type = "nvram";
123 compatible = "simtek,stk14ca8";
124 reg = <0x3 0x0 0x20000>;
125 };
86 126
87 fpga@4,0 { 127 fpga@4,0 {
88 compatible = "gef,fpga-regs"; 128 compatible = "gef,fpga-regs";
@@ -299,6 +339,22 @@
299 device_type = "open-pic"; 339 device_type = "open-pic";
300 }; 340 };
301 341
342 msi@41600 {
343 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
344 reg = <0x41600 0x80>;
345 msi-available-ranges = <0 0x100>;
346 interrupts = <
347 0xe0 0
348 0xe1 0
349 0xe2 0
350 0xe3 0
351 0xe4 0
352 0xe5 0
353 0xe6 0
354 0xe7 0>;
355 interrupt-parent = <&mpic>;
356 };
357
302 global-utilities@e0000 { 358 global-utilities@e0000 {
303 compatible = "fsl,mpc8641-guts"; 359 compatible = "fsl,mpc8641-guts";
304 reg = <0xe0000 0x1000>; 360 reg = <0xe0000 0x1000>;
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index f3787a27f634..d62a4fb6f93c 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree Source for AMCC Glacier (460GT) 2 * Device Tree Source for AMCC Glacier (460GT)
3 * 3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without 7 * License version 2. This program is licensed "as is" without
@@ -42,6 +42,7 @@
42 d-cache-size = <32768>; 42 d-cache-size = <32768>;
43 dcr-controller; 43 dcr-controller;
44 dcr-access-method = "native"; 44 dcr-access-method = "native";
45 next-level-cache = <&L2C0>;
45 }; 46 };
46 }; 47 };
47 48
@@ -106,6 +107,16 @@
106 dcr-reg = <0x00c 0x002>; 107 dcr-reg = <0x00c 0x002>;
107 }; 108 };
108 109
110 L2C0: l2c {
111 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
112 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
113 0x030 0x008>; /* L2 cache DCR's */
114 cache-line-size = <32>; /* 32 bytes */
115 cache-size = <262144>; /* L2, 256K */
116 interrupt-parent = <&UIC1>;
117 interrupts = <11 1>;
118 };
119
109 plb { 120 plb {
110 compatible = "ibm,plb-460gt", "ibm,plb4"; 121 compatible = "ibm,plb-460gt", "ibm,plb4";
111 #address-cells = <2>; 122 #address-cells = <2>;
@@ -118,6 +129,13 @@
118 dcr-reg = <0x010 0x002>; 129 dcr-reg = <0x010 0x002>;
119 }; 130 };
120 131
132 CRYPTO: crypto@180000 {
133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
134 reg = <4 0x00180000 0x80400>;
135 interrupt-parent = <&UIC0>;
136 interrupts = <0x1d 0x4>;
137 };
138
121 MAL0: mcmal { 139 MAL0: mcmal {
122 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 140 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
123 dcr-reg = <0x180 0x062>; 141 dcr-reg = <0x180 0x062>;
@@ -186,6 +204,29 @@
186 reg = <0x03fa0000 0x00060000>; 204 reg = <0x03fa0000 0x00060000>;
187 }; 205 };
188 }; 206 };
207
208 ndfc@3,0 {
209 compatible = "ibm,ndfc";
210 reg = <0x00000003 0x00000000 0x00002000>;
211 ccr = <0x00001000>;
212 bank-settings = <0x80002222>;
213 #address-cells = <1>;
214 #size-cells = <1>;
215
216 nand {
217 #address-cells = <1>;
218 #size-cells = <1>;
219
220 partition@0 {
221 label = "u-boot";
222 reg = <0x00000000 0x00100000>;
223 };
224 partition@100000 {
225 label = "user";
226 reg = <0x00000000 0x03f00000>;
227 };
228 };
229 };
189 }; 230 };
190 231
191 UART0: serial@ef600300 { 232 UART0: serial@ef600300 {
@@ -237,6 +278,20 @@
237 reg = <0xef600700 0x00000014>; 278 reg = <0xef600700 0x00000014>;
238 interrupt-parent = <&UIC0>; 279 interrupt-parent = <&UIC0>;
239 interrupts = <0x2 0x4>; 280 interrupts = <0x2 0x4>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 rtc@68 {
284 compatible = "stm,m41t80";
285 reg = <0x68>;
286 interrupt-parent = <&UIC2>;
287 interrupts = <0x19 0x8>;
288 };
289 sttm@48 {
290 compatible = "ad,ad7414";
291 reg = <0x48>;
292 interrupt-parent = <&UIC1>;
293 interrupts = <0x14 0x8>;
294 };
240 }; 295 };
241 296
242 IIC1: i2c@ef600800 { 297 IIC1: i2c@ef600800 {
@@ -275,7 +330,7 @@
275 330
276 EMAC0: ethernet@ef600e00 { 331 EMAC0: ethernet@ef600e00 {
277 device_type = "network"; 332 device_type = "network";
278 compatible = "ibm,emac-460gt", "ibm,emac4"; 333 compatible = "ibm,emac-460gt", "ibm,emac4sync";
279 interrupt-parent = <&EMAC0>; 334 interrupt-parent = <&EMAC0>;
280 interrupts = <0x0 0x1>; 335 interrupts = <0x0 0x1>;
281 #interrupt-cells = <1>; 336 #interrupt-cells = <1>;
@@ -283,7 +338,7 @@
283 #size-cells = <0>; 338 #size-cells = <0>;
284 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 339 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
285 /*Wake*/ 0x1 &UIC2 0x14 0x4>; 340 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
286 reg = <0xef600e00 0x00000074>; 341 reg = <0xef600e00 0x000000c4>;
287 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 342 local-mac-address = [000000000000]; /* Filled in by U-Boot */
288 mal-device = <&MAL0>; 343 mal-device = <&MAL0>;
289 mal-tx-channel = <0>; 344 mal-tx-channel = <0>;
@@ -292,6 +347,7 @@
292 max-frame-size = <9000>; 347 max-frame-size = <9000>;
293 rx-fifo-size = <4096>; 348 rx-fifo-size = <4096>;
294 tx-fifo-size = <2048>; 349 tx-fifo-size = <2048>;
350 rx-fifo-size-gige = <16384>;
295 phy-mode = "rgmii"; 351 phy-mode = "rgmii";
296 phy-map = <0x00000000>; 352 phy-map = <0x00000000>;
297 rgmii-device = <&RGMII0>; 353 rgmii-device = <&RGMII0>;
@@ -304,7 +360,7 @@
304 360
305 EMAC1: ethernet@ef600f00 { 361 EMAC1: ethernet@ef600f00 {
306 device_type = "network"; 362 device_type = "network";
307 compatible = "ibm,emac-460gt", "ibm,emac4"; 363 compatible = "ibm,emac-460gt", "ibm,emac4sync";
308 interrupt-parent = <&EMAC1>; 364 interrupt-parent = <&EMAC1>;
309 interrupts = <0x0 0x1>; 365 interrupts = <0x0 0x1>;
310 #interrupt-cells = <1>; 366 #interrupt-cells = <1>;
@@ -312,7 +368,7 @@
312 #size-cells = <0>; 368 #size-cells = <0>;
313 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 369 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
314 /*Wake*/ 0x1 &UIC2 0x15 0x4>; 370 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
315 reg = <0xef600f00 0x00000074>; 371 reg = <0xef600f00 0x000000c4>;
316 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 372 local-mac-address = [000000000000]; /* Filled in by U-Boot */
317 mal-device = <&MAL0>; 373 mal-device = <&MAL0>;
318 mal-tx-channel = <1>; 374 mal-tx-channel = <1>;
@@ -321,6 +377,7 @@
321 max-frame-size = <9000>; 377 max-frame-size = <9000>;
322 rx-fifo-size = <4096>; 378 rx-fifo-size = <4096>;
323 tx-fifo-size = <2048>; 379 tx-fifo-size = <2048>;
380 rx-fifo-size-gige = <16384>;
324 phy-mode = "rgmii"; 381 phy-mode = "rgmii";
325 phy-map = <0x00000000>; 382 phy-map = <0x00000000>;
326 rgmii-device = <&RGMII0>; 383 rgmii-device = <&RGMII0>;
@@ -334,7 +391,7 @@
334 391
335 EMAC2: ethernet@ef601100 { 392 EMAC2: ethernet@ef601100 {
336 device_type = "network"; 393 device_type = "network";
337 compatible = "ibm,emac-460gt", "ibm,emac4"; 394 compatible = "ibm,emac-460gt", "ibm,emac4sync";
338 interrupt-parent = <&EMAC2>; 395 interrupt-parent = <&EMAC2>;
339 interrupts = <0x0 0x1>; 396 interrupts = <0x0 0x1>;
340 #interrupt-cells = <1>; 397 #interrupt-cells = <1>;
@@ -342,7 +399,7 @@
342 #size-cells = <0>; 399 #size-cells = <0>;
343 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 400 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
344 /*Wake*/ 0x1 &UIC2 0x16 0x4>; 401 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
345 reg = <0xef601100 0x00000074>; 402 reg = <0xef601100 0x000000c4>;
346 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 403 local-mac-address = [000000000000]; /* Filled in by U-Boot */
347 mal-device = <&MAL0>; 404 mal-device = <&MAL0>;
348 mal-tx-channel = <2>; 405 mal-tx-channel = <2>;
@@ -351,6 +408,8 @@
351 max-frame-size = <9000>; 408 max-frame-size = <9000>;
352 rx-fifo-size = <4096>; 409 rx-fifo-size = <4096>;
353 tx-fifo-size = <2048>; 410 tx-fifo-size = <2048>;
411 rx-fifo-size-gige = <16384>;
412 tx-fifo-size-gige = <16384>; /* emac2&3 only */
354 phy-mode = "rgmii"; 413 phy-mode = "rgmii";
355 phy-map = <0x00000000>; 414 phy-map = <0x00000000>;
356 rgmii-device = <&RGMII1>; 415 rgmii-device = <&RGMII1>;
@@ -362,7 +421,7 @@
362 421
363 EMAC3: ethernet@ef601200 { 422 EMAC3: ethernet@ef601200 {
364 device_type = "network"; 423 device_type = "network";
365 compatible = "ibm,emac-460gt", "ibm,emac4"; 424 compatible = "ibm,emac-460gt", "ibm,emac4sync";
366 interrupt-parent = <&EMAC3>; 425 interrupt-parent = <&EMAC3>;
367 interrupts = <0x0 0x1>; 426 interrupts = <0x0 0x1>;
368 #interrupt-cells = <1>; 427 #interrupt-cells = <1>;
@@ -370,7 +429,7 @@
370 #size-cells = <0>; 429 #size-cells = <0>;
371 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 430 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
372 /*Wake*/ 0x1 &UIC2 0x17 0x4>; 431 /*Wake*/ 0x1 &UIC2 0x17 0x4>;
373 reg = <0xef601200 0x00000074>; 432 reg = <0xef601200 0x000000c4>;
374 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 433 local-mac-address = [000000000000]; /* Filled in by U-Boot */
375 mal-device = <&MAL0>; 434 mal-device = <&MAL0>;
376 mal-tx-channel = <3>; 435 mal-tx-channel = <3>;
@@ -379,6 +438,8 @@
379 max-frame-size = <9000>; 438 max-frame-size = <9000>;
380 rx-fifo-size = <4096>; 439 rx-fifo-size = <4096>;
381 tx-fifo-size = <2048>; 440 tx-fifo-size = <2048>;
441 rx-fifo-size-gige = <16384>;
442 tx-fifo-size-gige = <16384>; /* emac2&3 only */
382 phy-mode = "rgmii"; 443 phy-mode = "rgmii";
383 phy-map = <0x00000000>; 444 phy-map = <0x00000000>;
384 rgmii-device = <&RGMII1>; 445 rgmii-device = <&RGMII1>;
@@ -408,6 +469,7 @@
408 * later cannot be changed 469 * later cannot be changed
409 */ 470 */
410 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 471 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
472 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
411 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 473 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
412 474
413 /* Inbound 2GB range starting at 0 */ 475 /* Inbound 2GB range starting at 0 */
@@ -438,6 +500,7 @@
438 * later cannot be changed 500 * later cannot be changed
439 */ 501 */
440 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 502 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
503 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
441 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 504 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
442 505
443 /* Inbound 2GB range starting at 0 */ 506 /* Inbound 2GB range starting at 0 */
@@ -479,6 +542,7 @@
479 * later cannot be changed 542 * later cannot be changed
480 */ 543 */
481 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 544 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
545 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
482 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 546 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
483 547
484 /* Inbound 2GB range starting at 0 */ 548 /* Inbound 2GB range starting at 0 */
diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts
index 5b2a4947bf82..2b256694eca6 100644
--- a/arch/powerpc/boot/dts/haleakala.dts
+++ b/arch/powerpc/boot/dts/haleakala.dts
@@ -226,6 +226,8 @@
226 max-frame-size = <9000>; 226 max-frame-size = <9000>;
227 rx-fifo-size = <4096>; 227 rx-fifo-size = <4096>;
228 tx-fifo-size = <2048>; 228 tx-fifo-size = <2048>;
229 rx-fifo-size-gige = <16384>;
230 tx-fifo-size-gige = <16384>;
229 phy-mode = "rgmii"; 231 phy-mode = "rgmii";
230 phy-map = <0x00000000>; 232 phy-map = <0x00000000>;
231 rgmii-device = <&RGMII0>; 233 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 077819bc3cbd..8cf2c0c88c05 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -16,7 +16,7 @@
16 16
17/ { 17/ {
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <1>; 19 #size-cells = <2>;
20 model = "amcc,katmai"; 20 model = "amcc,katmai";
21 compatible = "amcc,katmai"; 21 compatible = "amcc,katmai";
22 dcr-parent = <&{/cpus/cpu@0}>; 22 dcr-parent = <&{/cpus/cpu@0}>;
@@ -49,7 +49,7 @@
49 49
50 memory { 50 memory {
51 device_type = "memory"; 51 device_type = "memory";
52 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ 52 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
53 }; 53 };
54 54
55 UIC0: interrupt-controller0 { 55 UIC0: interrupt-controller0 {
@@ -108,11 +108,26 @@
108 dcr-reg = <0x00c 0x002>; 108 dcr-reg = <0x00c 0x002>;
109 }; 109 };
110 110
111 MQ0: mq {
112 compatible = "ibm,mq-440spe";
113 dcr-reg = <0x040 0x020>;
114 };
115
111 plb { 116 plb {
112 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; 117 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
113 #address-cells = <2>; 118 #address-cells = <2>;
114 #size-cells = <1>; 119 #size-cells = <1>;
115 ranges; 120 /* addr-child addr-parent size */
121 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
122 0x4 0x00200000 0x4 0x00200000 0x00000400
123 0x4 0xe0000000 0x4 0xe0000000 0x20000000
124 0xc 0x00000000 0xc 0x00000000 0x20000000
125 0xd 0x00000000 0xd 0x00000000 0x80000000
126 0xd 0x80000000 0xd 0x80000000 0x80000000
127 0xe 0x00000000 0xe 0x00000000 0x80000000
128 0xe 0x80000000 0xe 0x80000000 0x80000000
129 0xf 0x00000000 0xf 0x00000000 0x80000000
130 0xf 0x80000000 0xf 0x80000000 0x80000000>;
116 clock-frequency = <0>; /* Filled in by zImage */ 131 clock-frequency = <0>; /* Filled in by zImage */
117 132
118 SDRAM0: sdram { 133 SDRAM0: sdram {
@@ -141,7 +156,7 @@
141 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; 156 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
142 #address-cells = <1>; 157 #address-cells = <1>;
143 #size-cells = <1>; 158 #size-cells = <1>;
144 ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>; 159 ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
145 clock-frequency = <0>; /* Filled in by zImage */ 160 clock-frequency = <0>; /* Filled in by zImage */
146 161
147 EBC0: ebc { 162 EBC0: ebc {
@@ -150,14 +165,47 @@
150 #address-cells = <2>; 165 #address-cells = <2>;
151 #size-cells = <1>; 166 #size-cells = <1>;
152 clock-frequency = <0>; /* Filled in by zImage */ 167 clock-frequency = <0>; /* Filled in by zImage */
168 /* ranges property is supplied by U-Boot */
153 interrupts = <0x5 0x1>; 169 interrupts = <0x5 0x1>;
154 interrupt-parent = <&UIC1>; 170 interrupt-parent = <&UIC1>;
171
172 nor_flash@0,0 {
173 compatible = "cfi-flash";
174 bank-width = <2>;
175 reg = <0x00000000 0x00000000 0x01000000>;
176 #address-cells = <1>;
177 #size-cells = <1>;
178 partition@0 {
179 label = "kernel";
180 reg = <0x00000000 0x001e0000>;
181 };
182 partition@1e0000 {
183 label = "dtb";
184 reg = <0x001e0000 0x00020000>;
185 };
186 partition@200000 {
187 label = "root";
188 reg = <0x00200000 0x00200000>;
189 };
190 partition@400000 {
191 label = "user";
192 reg = <0x00400000 0x00b60000>;
193 };
194 partition@f60000 {
195 label = "env";
196 reg = <0x00f60000 0x00040000>;
197 };
198 partition@fa0000 {
199 label = "u-boot";
200 reg = <0x00fa0000 0x00060000>;
201 };
202 };
155 }; 203 };
156 204
157 UART0: serial@10000200 { 205 UART0: serial@f0000200 {
158 device_type = "serial"; 206 device_type = "serial";
159 compatible = "ns16550"; 207 compatible = "ns16550";
160 reg = <0x10000200 0x00000008>; 208 reg = <0xf0000200 0x00000008>;
161 virtual-reg = <0xa0000200>; 209 virtual-reg = <0xa0000200>;
162 clock-frequency = <0>; /* Filled in by zImage */ 210 clock-frequency = <0>; /* Filled in by zImage */
163 current-speed = <115200>; 211 current-speed = <115200>;
@@ -165,10 +213,10 @@
165 interrupts = <0x0 0x4>; 213 interrupts = <0x0 0x4>;
166 }; 214 };
167 215
168 UART1: serial@10000300 { 216 UART1: serial@f0000300 {
169 device_type = "serial"; 217 device_type = "serial";
170 compatible = "ns16550"; 218 compatible = "ns16550";
171 reg = <0x10000300 0x00000008>; 219 reg = <0xf0000300 0x00000008>;
172 virtual-reg = <0xa0000300>; 220 virtual-reg = <0xa0000300>;
173 clock-frequency = <0>; 221 clock-frequency = <0>;
174 current-speed = <0>; 222 current-speed = <0>;
@@ -177,10 +225,10 @@
177 }; 225 };
178 226
179 227
180 UART2: serial@10000600 { 228 UART2: serial@f0000600 {
181 device_type = "serial"; 229 device_type = "serial";
182 compatible = "ns16550"; 230 compatible = "ns16550";
183 reg = <0x10000600 0x00000008>; 231 reg = <0xf0000600 0x00000008>;
184 virtual-reg = <0xa0000600>; 232 virtual-reg = <0xa0000600>;
185 clock-frequency = <0>; 233 clock-frequency = <0>;
186 current-speed = <0>; 234 current-speed = <0>;
@@ -188,27 +236,27 @@
188 interrupts = <0x5 0x4>; 236 interrupts = <0x5 0x4>;
189 }; 237 };
190 238
191 IIC0: i2c@10000400 { 239 IIC0: i2c@f0000400 {
192 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 240 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
193 reg = <0x10000400 0x00000014>; 241 reg = <0xf0000400 0x00000014>;
194 interrupt-parent = <&UIC0>; 242 interrupt-parent = <&UIC0>;
195 interrupts = <0x2 0x4>; 243 interrupts = <0x2 0x4>;
196 }; 244 };
197 245
198 IIC1: i2c@10000500 { 246 IIC1: i2c@f0000500 {
199 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 247 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
200 reg = <0x10000500 0x00000014>; 248 reg = <0xf0000500 0x00000014>;
201 interrupt-parent = <&UIC0>; 249 interrupt-parent = <&UIC0>;
202 interrupts = <0x3 0x4>; 250 interrupts = <0x3 0x4>;
203 }; 251 };
204 252
205 EMAC0: ethernet@10000800 { 253 EMAC0: ethernet@f0000800 {
206 linux,network-index = <0x0>; 254 linux,network-index = <0x0>;
207 device_type = "network"; 255 device_type = "network";
208 compatible = "ibm,emac-440spe", "ibm,emac4"; 256 compatible = "ibm,emac-440spe", "ibm,emac4";
209 interrupt-parent = <&UIC1>; 257 interrupt-parent = <&UIC1>;
210 interrupts = <0x1c 0x4 0x1d 0x4>; 258 interrupts = <0x1c 0x4 0x1d 0x4>;
211 reg = <0x10000800 0x00000074>; 259 reg = <0xf0000800 0x00000074>;
212 local-mac-address = [000000000000]; 260 local-mac-address = [000000000000];
213 mal-device = <&MAL0>; 261 mal-device = <&MAL0>;
214 mal-tx-channel = <0>; 262 mal-tx-channel = <0>;
@@ -233,11 +281,11 @@
233 primary; 281 primary;
234 large-inbound-windows; 282 large-inbound-windows;
235 enable-msi-hole; 283 enable-msi-hole;
236 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 284 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
237 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 285 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
238 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 286 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
239 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 287 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
240 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 288 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
241 289
242 /* Outbound ranges, one memory and one IO, 290 /* Outbound ranges, one memory and one IO,
243 * later cannot be changed 291 * later cannot be changed
@@ -245,8 +293,8 @@
245 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 293 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
246 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 294 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
247 295
248 /* Inbound 2GB range starting at 0 */ 296 /* Inbound 4GB range starting at 0 */
249 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 297 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
250 298
251 /* This drives busses 0 to 0xf */ 299 /* This drives busses 0 to 0xf */
252 bus-range = <0x0 0xf>; 300 bus-range = <0x0 0xf>;
@@ -289,10 +337,10 @@
289 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 337 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
290 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 338 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
291 339
292 /* Inbound 2GB range starting at 0 */ 340 /* Inbound 4GB range starting at 0 */
293 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 341 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
294 342
295 /* This drives busses 10 to 0x1f */ 343 /* This drives busses 0x10 to 0x1f */
296 bus-range = <0x10 0x1f>; 344 bus-range = <0x10 0x1f>;
297 345
298 /* Legacy interrupts (note the weird polarity, the bridge seems 346 /* Legacy interrupts (note the weird polarity, the bridge seems
@@ -330,10 +378,10 @@
330 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 378 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
331 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 379 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
332 380
333 /* Inbound 2GB range starting at 0 */ 381 /* Inbound 4GB range starting at 0 */
334 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 382 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
335 383
336 /* This drives busses 10 to 0x1f */ 384 /* This drives busses 0x20 to 0x2f */
337 bus-range = <0x20 0x2f>; 385 bus-range = <0x20 0x2f>;
338 386
339 /* Legacy interrupts (note the weird polarity, the bridge seems 387 /* Legacy interrupts (note the weird polarity, the bridge seems
@@ -371,10 +419,10 @@
371 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 419 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
372 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; 420 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
373 421
374 /* Inbound 2GB range starting at 0 */ 422 /* Inbound 4GB range starting at 0 */
375 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 423 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
376 424
377 /* This drives busses 10 to 0x1f */ 425 /* This drives busses 0x30 to 0x3f */
378 bus-range = <0x30 0x3f>; 426 bus-range = <0x30 0x3f>;
379 427
380 /* Legacy interrupts (note the weird polarity, the bridge seems 428 /* Legacy interrupts (note the weird polarity, the bridge seems
@@ -392,9 +440,52 @@
392 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ 440 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
393 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; 441 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
394 }; 442 };
443
444 I2O: i2o@400100000 {
445 compatible = "ibm,i2o-440spe";
446 reg = <0x00000004 0x00100000 0x100>;
447 dcr-reg = <0x060 0x020>;
448 };
449
450 DMA0: dma0@400100100 {
451 compatible = "ibm,dma-440spe";
452 cell-index = <0>;
453 reg = <0x00000004 0x00100100 0x100>;
454 dcr-reg = <0x060 0x020>;
455 interrupt-parent = <&DMA0>;
456 interrupts = <0 1>;
457 #interrupt-cells = <1>;
458 #address-cells = <0>;
459 #size-cells = <0>;
460 interrupt-map = <
461 0 &UIC0 0x14 4
462 1 &UIC1 0x16 4>;
463 };
464
465 DMA1: dma1@400100200 {
466 compatible = "ibm,dma-440spe";
467 cell-index = <1>;
468 reg = <0x00000004 0x00100200 0x100>;
469 dcr-reg = <0x060 0x020>;
470 interrupt-parent = <&DMA1>;
471 interrupts = <0 1>;
472 #interrupt-cells = <1>;
473 #address-cells = <0>;
474 #size-cells = <0>;
475 interrupt-map = <
476 0 &UIC0 0x16 4
477 1 &UIC1 0x16 4>;
478 };
479
480 xor-accel@400200000 {
481 compatible = "amcc,xor-accelerator";
482 reg = <0x00000004 0x00200000 0x400>;
483 interrupt-parent = <&UIC1>;
484 interrupts = <0x1f 4>;
485 };
395 }; 486 };
396 487
397 chosen { 488 chosen {
398 linux,stdout-path = "/plb/opb/serial@10000200"; 489 linux,stdout-path = "/plb/opb/serial@f0000200";
399 }; 490 };
400}; 491};
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index c46561456ede..083e68eeaca4 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -272,6 +272,8 @@
272 max-frame-size = <9000>; 272 max-frame-size = <9000>;
273 rx-fifo-size = <4096>; 273 rx-fifo-size = <4096>;
274 tx-fifo-size = <2048>; 274 tx-fifo-size = <2048>;
275 rx-fifo-size-gige = <16384>;
276 tx-fifo-size-gige = <16384>;
275 phy-mode = "rgmii"; 277 phy-mode = "rgmii";
276 phy-map = <0x00000000>; 278 phy-map = <0x00000000>;
277 rgmii-device = <&RGMII0>; 279 rgmii-device = <&RGMII0>;
@@ -300,6 +302,8 @@
300 max-frame-size = <9000>; 302 max-frame-size = <9000>;
301 rx-fifo-size = <4096>; 303 rx-fifo-size = <4096>;
302 tx-fifo-size = <2048>; 304 tx-fifo-size = <2048>;
305 rx-fifo-size-gige = <16384>;
306 tx-fifo-size-gige = <16384>;
303 phy-mode = "rgmii"; 307 phy-mode = "rgmii";
304 phy-map = <0x00000000>; 308 phy-map = <0x00000000>;
305 rgmii-device = <&RGMII0>; 309 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index 167044f7de1d..d8b5d12fb663 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -59,6 +59,13 @@
59 reg = <0xe0000000 0x00000200>; 59 reg = <0xe0000000 0x00000200>;
60 bus-frequency = <0>; /* Filled in by U-Boot */ 60 bus-frequency = <0>; /* Filled in by U-Boot */
61 61
62 pmc: power@b00 {
63 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
64 reg = <0xb00 0x100 0xa00 0x100>;
65 interrupts = <80 0x8>;
66 interrupt-parent = <&ipic>;
67 };
68
62 i2c@3000 { 69 i2c@3000 {
63 #address-cells = <1>; 70 #address-cells = <1>;
64 #size-cells = <0>; 71 #size-cells = <0>;
@@ -483,7 +490,7 @@
483 compatible = "cfi-flash"; 490 compatible = "cfi-flash";
484 /* 491 /*
485 * The Intel P30 chip has 2 non-identical chips on 492 * The Intel P30 chip has 2 non-identical chips on
486 * one die, so we need to define 2 seperate regions 493 * one die, so we need to define 2 separate regions
487 * that are scanned by physmap_of independantly. 494 * that are scanned by physmap_of independantly.
488 */ 495 */
489 reg = <0 0x00000000 0x02000000 496 reg = <0 0x00000000 0x02000000
diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts
index ffc246e72670..63d48b632c84 100644
--- a/arch/powerpc/boot/dts/makalu.dts
+++ b/arch/powerpc/boot/dts/makalu.dts
@@ -227,6 +227,8 @@
227 max-frame-size = <9000>; 227 max-frame-size = <9000>;
228 rx-fifo-size = <4096>; 228 rx-fifo-size = <4096>;
229 tx-fifo-size = <2048>; 229 tx-fifo-size = <2048>;
230 rx-fifo-size-gige = <16384>;
231 tx-fifo-size-gige = <16384>;
230 phy-mode = "rgmii"; 232 phy-mode = "rgmii";
231 phy-map = <0x0000003f>; /* Start at 6 */ 233 phy-map = <0x0000003f>; /* Start at 6 */
232 rgmii-device = <&RGMII0>; 234 rgmii-device = <&RGMII0>;
@@ -255,6 +257,8 @@
255 max-frame-size = <9000>; 257 max-frame-size = <9000>;
256 rx-fifo-size = <4096>; 258 rx-fifo-size = <4096>;
257 tx-fifo-size = <2048>; 259 tx-fifo-size = <2048>;
260 rx-fifo-size-gige = <16384>;
261 tx-fifo-size-gige = <16384>;
258 phy-mode = "rgmii"; 262 phy-mode = "rgmii";
259 phy-map = <0x00000000>; 263 phy-map = <0x00000000>;
260 rgmii-device = <&RGMII0>; 264 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c353dac33416..c9ef6bbe26cf 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -62,17 +62,12 @@
62 interrupt-parent = < &ipic >; 62 interrupt-parent = < &ipic >;
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <1>; 64 #size-cells = <1>;
65 bank-width = <1>;
66 // ADS has two Hynix 512MB Nand flash chips in a single 65 // ADS has two Hynix 512MB Nand flash chips in a single
67 // stacked package . 66 // stacked package.
68 chips = <2>; 67 chips = <2>;
69 nand0@0 { 68 nand@0 {
70 label = "nand0"; 69 label = "nand";
71 reg = <0x00000000 0x02000000>; // first 32 MB of chip 0 70 reg = <0x00000000 0x40000000>; // 512MB + 512MB
72 };
73 nand1@20000000 {
74 label = "nand1";
75 reg = <0x20000000 0x02000000>; // first 32 MB of chip 1
76 }; 71 };
77 }; 72 };
78 73
@@ -166,6 +161,11 @@
166 interrupt-parent = < &ipic >; 161 interrupt-parent = < &ipic >;
167 }; 162 };
168 163
164 reset@e00 { // Reset module
165 compatible = "fsl,mpc5121-reset";
166 reg = <0xe00 0x100>;
167 };
168
169 clock@f00 { // Clock control 169 clock@f00 { // Clock control
170 compatible = "fsl,mpc5121-clock"; 170 compatible = "fsl,mpc5121-clock";
171 reg = <0xf00 0x100>; 171 reg = <0xf00 0x100>;
@@ -185,17 +185,15 @@
185 interrupt-parent = < &ipic >; 185 interrupt-parent = < &ipic >;
186 }; 186 };
187 187
188 mscan@1300 { 188 can@1300 {
189 compatible = "fsl,mpc5121-mscan"; 189 compatible = "fsl,mpc5121-mscan";
190 cell-index = <0>;
191 interrupts = <12 0x8>; 190 interrupts = <12 0x8>;
192 interrupt-parent = < &ipic >; 191 interrupt-parent = < &ipic >;
193 reg = <0x1300 0x80>; 192 reg = <0x1300 0x80>;
194 }; 193 };
195 194
196 mscan@1380 { 195 can@1380 {
197 compatible = "fsl,mpc5121-mscan"; 196 compatible = "fsl,mpc5121-mscan";
198 cell-index = <1>;
199 interrupts = <13 0x8>; 197 interrupts = <13 0x8>;
200 interrupt-parent = < &ipic >; 198 interrupt-parent = < &ipic >;
201 reg = <0x1380 0x80>; 199 reg = <0x1380 0x80>;
@@ -205,17 +203,31 @@
205 #address-cells = <1>; 203 #address-cells = <1>;
206 #size-cells = <0>; 204 #size-cells = <0>;
207 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 205 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
208 cell-index = <0>;
209 reg = <0x1700 0x20>; 206 reg = <0x1700 0x20>;
210 interrupts = <9 0x8>; 207 interrupts = <9 0x8>;
211 interrupt-parent = < &ipic >; 208 interrupt-parent = < &ipic >;
209 fsl,preserve-clocking;
210
211 hwmon@4a {
212 compatible = "adi,ad7414";
213 reg = <0x4a>;
214 };
215
216 eeprom@50 {
217 compatible = "at,24c32";
218 reg = <0x50>;
219 };
220
221 rtc@68 {
222 compatible = "stm,m41t62";
223 reg = <0x68>;
224 };
212 }; 225 };
213 226
214 i2c@1720 { 227 i2c@1720 {
215 #address-cells = <1>; 228 #address-cells = <1>;
216 #size-cells = <0>; 229 #size-cells = <0>;
217 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 230 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
218 cell-index = <1>;
219 reg = <0x1720 0x20>; 231 reg = <0x1720 0x20>;
220 interrupts = <10 0x8>; 232 interrupts = <10 0x8>;
221 interrupt-parent = < &ipic >; 233 interrupt-parent = < &ipic >;
@@ -225,7 +237,6 @@
225 #address-cells = <1>; 237 #address-cells = <1>;
226 #size-cells = <0>; 238 #size-cells = <0>;
227 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 239 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
228 cell-index = <2>;
229 reg = <0x1740 0x20>; 240 reg = <0x1740 0x20>;
230 interrupts = <11 0x8>; 241 interrupts = <11 0x8>;
231 interrupt-parent = < &ipic >; 242 interrupt-parent = < &ipic >;
@@ -244,7 +255,7 @@
244 }; 255 };
245 256
246 display@2100 { 257 display@2100 {
247 compatible = "fsl,mpc5121-diu", "fsl-diu"; 258 compatible = "fsl,mpc5121-diu";
248 reg = <0x2100 0x100>; 259 reg = <0x2100 0x100>;
249 interrupts = <64 0x8>; 260 interrupts = <64 0x8>;
250 interrupt-parent = < &ipic >; 261 interrupt-parent = < &ipic >;
@@ -277,7 +288,7 @@
277 288
278 // USB1 using external ULPI PHY 289 // USB1 using external ULPI PHY
279 //usb@3000 { 290 //usb@3000 {
280 // compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; 291 // compatible = "fsl,mpc5121-usb2-dr";
281 // reg = <0x3000 0x1000>; 292 // reg = <0x3000 0x1000>;
282 // #address-cells = <1>; 293 // #address-cells = <1>;
283 // #size-cells = <0>; 294 // #size-cells = <0>;
@@ -285,12 +296,11 @@
285 // interrupts = <43 0x8>; 296 // interrupts = <43 0x8>;
286 // dr_mode = "otg"; 297 // dr_mode = "otg";
287 // phy_type = "ulpi"; 298 // phy_type = "ulpi";
288 // port1;
289 //}; 299 //};
290 300
291 // USB0 using internal UTMI PHY 301 // USB0 using internal UTMI PHY
292 usb@4000 { 302 usb@4000 {
293 compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; 303 compatible = "fsl,mpc5121-usb2-dr";
294 reg = <0x4000 0x1000>; 304 reg = <0x4000 0x1000>;
295 #address-cells = <1>; 305 #address-cells = <1>;
296 #size-cells = <0>; 306 #size-cells = <0>;
@@ -298,7 +308,8 @@
298 interrupts = <44 0x8>; 308 interrupts = <44 0x8>;
299 dr_mode = "otg"; 309 dr_mode = "otg";
300 phy_type = "utmi_wide"; 310 phy_type = "utmi_wide";
301 port0; 311 fsl,invert-drvvbus;
312 fsl,invert-pwr-fault;
302 }; 313 };
303 314
304 // IO control 315 // IO control
@@ -365,7 +376,7 @@
365 }; 376 };
366 377
367 dma@14000 { 378 dma@14000 {
368 compatible = "fsl,mpc5121-dma2"; 379 compatible = "fsl,mpc5121-dma";
369 reg = <0x14000 0x1800>; 380 reg = <0x14000 0x1800>;
370 interrupts = <65 0x8>; 381 interrupts = <65 0x8>;
371 interrupt-parent = < &ipic >; 382 interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 32e10f588c1d..8a3a4f3ef831 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -204,6 +204,7 @@
204 interrupt-parent = <&ipic>; 204 interrupt-parent = <&ipic>;
205 tbi-handle = <&tbi0>; 205 tbi-handle = <&tbi0>;
206 phy-handle = < &phy0 >; 206 phy-handle = < &phy0 >;
207 fsl,magic-packet;
207 208
208 mdio@520 { 209 mdio@520 {
209 #address-cells = <1>; 210 #address-cells = <1>;
@@ -246,6 +247,7 @@
246 interrupt-parent = <&ipic>; 247 interrupt-parent = <&ipic>;
247 tbi-handle = <&tbi1>; 248 tbi-handle = <&tbi1>;
248 phy-handle = < &phy1 >; 249 phy-handle = < &phy1 >;
250 fsl,magic-packet;
249 251
250 mdio@520 { 252 mdio@520 {
251 #address-cells = <1>; 253 #address-cells = <1>;
@@ -309,6 +311,22 @@
309 interrupt-parent = <&ipic>; 311 interrupt-parent = <&ipic>;
310 }; 312 };
311 313
314 gtm1: timer@500 {
315 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
316 reg = <0x500 0x100>;
317 interrupts = <90 8 78 8 84 8 72 8>;
318 interrupt-parent = <&ipic>;
319 clock-frequency = <133333333>;
320 };
321
322 timer@600 {
323 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
324 reg = <0x600 0x100>;
325 interrupts = <91 8 79 8 85 8 73 8>;
326 interrupt-parent = <&ipic>;
327 clock-frequency = <133333333>;
328 };
329
312 /* IPIC 330 /* IPIC
313 * interrupts cell = <intr #, sense> 331 * interrupts cell = <intr #, sense>
314 * sense values match linux IORESOURCE_IRQ_* defines: 332 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -337,6 +355,15 @@
337 0x59 0x8>; 355 0x59 0x8>;
338 interrupt-parent = < &ipic >; 356 interrupt-parent = < &ipic >;
339 }; 357 };
358
359 pmc: power@b00 {
360 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
361 "fsl,mpc8349-pmc";
362 reg = <0xb00 0x100 0xa00 0x100>;
363 interrupts = <80 8>;
364 interrupt-parent = <&ipic>;
365 fsl,mpc8313-wakeup-timer = <&gtm1>;
366 };
340 }; 367 };
341 368
342 pci0: pci@e0008500 { 369 pci0: pci@e0008500 {
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 436c9c671dd9..05ad8c98e527 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -79,6 +79,13 @@
79 reg = <0x200 0x100>; 79 reg = <0x200 0x100>;
80 }; 80 };
81 81
82 pmc: power@b00 {
83 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
84 reg = <0xb00 0x100 0xa00 0x100>;
85 interrupts = <80 0x8>;
86 interrupt-parent = <&ipic>;
87 };
88
82 i2c@3000 { 89 i2c@3000 {
83 #address-cells = <1>; 90 #address-cells = <1>;
84 #size-cells = <0>; 91 #size-cells = <0>;
@@ -163,6 +170,7 @@
163 fsl,channel-fifo-len = <24>; 170 fsl,channel-fifo-len = <24>;
164 fsl,exec-units-mask = <0x4c>; 171 fsl,exec-units-mask = <0x4c>;
165 fsl,descriptor-types-mask = <0x0122003f>; 172 fsl,descriptor-types-mask = <0x0122003f>;
173 sleep = <&pmc 0x03000000>;
166 }; 174 };
167 175
168 ipic: pic@700 { 176 ipic: pic@700 {
@@ -428,5 +436,6 @@
428 0xe0008300 0x8>; /* config space access registers */ 436 0xe0008300 0x8>; /* config space access registers */
429 compatible = "fsl,mpc8349-pci"; 437 compatible = "fsl,mpc8349-pci";
430 device_type = "pci"; 438 device_type = "pci";
439 sleep = <&pmc 0x00010000>;
431 }; 440 };
432}; 441};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 9a0952f74b81..f4fadb23ad6f 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -62,6 +62,13 @@
62 reg = <0x200 0x100>; 62 reg = <0x200 0x100>;
63 }; 63 };
64 64
65 pmc: power@b00 {
66 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
67 reg = <0xb00 0x100 0xa00 0x100>;
68 interrupts = <80 0x8>;
69 interrupt-parent = <&ipic>;
70 };
71
65 i2c@3000 { 72 i2c@3000 {
66 #address-cells = <1>; 73 #address-cells = <1>;
67 #size-cells = <0>; 74 #size-cells = <0>;
@@ -141,6 +148,7 @@
141 fsl,channel-fifo-len = <24>; 148 fsl,channel-fifo-len = <24>;
142 fsl,exec-units-mask = <0x4c>; 149 fsl,exec-units-mask = <0x4c>;
143 fsl,descriptor-types-mask = <0x0122003f>; 150 fsl,descriptor-types-mask = <0x0122003f>;
151 sleep = <&pmc 0x03000000>;
144 }; 152 };
145 153
146 ipic:pic@700 { 154 ipic:pic@700 {
@@ -360,5 +368,6 @@
360 0xe0008300 0x8>; /* config space access registers */ 368 0xe0008300 0x8>; /* config space access registers */
361 compatible = "fsl,mpc8349-pci"; 369 compatible = "fsl,mpc8349-pci";
362 device_type = "pci"; 370 device_type = "pci";
371 sleep = <&pmc 0x00010000>;
363 }; 372 };
364}; 373};
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index feeeb7f9d609..b53d1df11e2d 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -63,6 +63,24 @@
63 reg = <0x200 0x100>; 63 reg = <0x200 0x100>;
64 }; 64 };
65 65
66 gpio1: gpio-controller@c00 {
67 #gpio-cells = <2>;
68 compatible = "fsl,mpc8349-gpio";
69 reg = <0xc00 0x100>;
70 interrupts = <74 0x8>;
71 interrupt-parent = <&ipic>;
72 gpio-controller;
73 };
74
75 gpio2: gpio-controller@d00 {
76 #gpio-cells = <2>;
77 compatible = "fsl,mpc8349-gpio";
78 reg = <0xd00 0x100>;
79 interrupts = <75 0x8>;
80 interrupt-parent = <&ipic>;
81 gpio-controller;
82 };
83
66 i2c@3000 { 84 i2c@3000 {
67 #address-cells = <1>; 85 #address-cells = <1>;
68 #size-cells = <0>; 86 #size-cells = <0>;
@@ -72,6 +90,12 @@
72 interrupts = <14 0x8>; 90 interrupts = <14 0x8>;
73 interrupt-parent = <&ipic>; 91 interrupt-parent = <&ipic>;
74 dfsrr; 92 dfsrr;
93
94 eeprom: at24@50 {
95 compatible = "st-micro,24c256";
96 reg = <0x50>;
97 };
98
75 }; 99 };
76 100
77 i2c@3100 { 101 i2c@3100 {
@@ -91,6 +115,25 @@
91 interrupt-parent = <&ipic>; 115 interrupt-parent = <&ipic>;
92 }; 116 };
93 117
118 pcf1: iexp@38 {
119 #gpio-cells = <2>;
120 compatible = "ti,pcf8574a";
121 reg = <0x38>;
122 gpio-controller;
123 };
124
125 pcf2: iexp@39 {
126 #gpio-cells = <2>;
127 compatible = "ti,pcf8574a";
128 reg = <0x39>;
129 gpio-controller;
130 };
131
132 spd: at24@51 {
133 compatible = "at24,spd";
134 reg = <0x51>;
135 };
136
94 mcu_pio: mcu@a { 137 mcu_pio: mcu@a {
95 #gpio-cells = <2>; 138 #gpio-cells = <2>;
96 compatible = "fsl,mc9s08qg8-mpc8349emitx", 139 compatible = "fsl,mc9s08qg8-mpc8349emitx",
@@ -275,6 +318,24 @@
275 reg = <0x700 0x100>; 318 reg = <0x700 0x100>;
276 device_type = "ipic"; 319 device_type = "ipic";
277 }; 320 };
321
322 gpio-leds {
323 compatible = "gpio-leds";
324
325 green {
326 label = "Green";
327 gpios = <&pcf1 0 1>;
328 linux,default-trigger = "heartbeat";
329 };
330
331 yellow {
332 label = "Yellow";
333 gpios = <&pcf1 1 1>;
334 /* linux,default-trigger = "heartbeat"; */
335 default-state = "on";
336 };
337 };
338
278 }; 339 };
279 340
280 pci0: pci@e0008500 { 341 pci0: pci@e0008500 {
@@ -331,7 +392,26 @@
331 compatible = "fsl,mpc8349e-localbus", 392 compatible = "fsl,mpc8349e-localbus",
332 "fsl,pq2pro-localbus"; 393 "fsl,pq2pro-localbus";
333 reg = <0xe0005000 0xd8>; 394 reg = <0xe0005000 0xd8>;
334 ranges = <0x3 0x0 0xf0000000 0x210>; 395 ranges = <0x0 0x0 0xfe000000 0x1000000 /* flash */
396 0x1 0x0 0xf8000000 0x20000 /* VSC 7385 */
397 0x2 0x0 0xf9000000 0x200000 /* exp slot */
398 0x3 0x0 0xf0000000 0x210>; /* CF slot */
399
400 flash@0,0 {
401 compatible = "cfi-flash";
402 reg = <0x0 0x0 0x800000>;
403 bank-width = <2>;
404 device-width = <1>;
405 };
406
407 flash@0,800000 {
408 #address-cells = <1>;
409 #size-cells = <1>;
410 compatible = "cfi-flash";
411 reg = <0x0 0x800000 0x800000>;
412 bank-width = <2>;
413 device-width = <1>;
414 };
335 415
336 pata@3,0 { 416 pata@3,0 {
337 compatible = "fsl,mpc8349emitx-pata", "ata-generic"; 417 compatible = "fsl,mpc8349emitx-pata", "ata-generic";
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 39ff4c829caf..45cfa1c50a2a 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -99,6 +99,13 @@
99 reg = <0x200 0x100>; 99 reg = <0x200 0x100>;
100 }; 100 };
101 101
102 pmc: power@b00 {
103 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
104 reg = <0xb00 0x100 0xa00 0x100>;
105 interrupts = <80 0x8>;
106 interrupt-parent = <&ipic>;
107 };
108
102 i2c@3000 { 109 i2c@3000 {
103 #address-cells = <1>; 110 #address-cells = <1>;
104 #size-cells = <0>; 111 #size-cells = <0>;
@@ -194,6 +201,7 @@
194 fsl,channel-fifo-len = <24>; 201 fsl,channel-fifo-len = <24>;
195 fsl,exec-units-mask = <0x7e>; 202 fsl,exec-units-mask = <0x7e>;
196 fsl,descriptor-types-mask = <0x01010ebf>; 203 fsl,descriptor-types-mask = <0x01010ebf>;
204 sleep = <&pmc 0x03000000>;
197 }; 205 };
198 206
199 ipic: pic@700 { 207 ipic: pic@700 {
@@ -470,5 +478,6 @@
470 0xe0008300 0x8>; /* config space access registers */ 478 0xe0008300 0x8>; /* config space access registers */
471 compatible = "fsl,mpc8349-pci"; 479 compatible = "fsl,mpc8349-pci";
472 device_type = "pci"; 480 device_type = "pci";
481 sleep = <&pmc 0x00010000>;
473 }; 482 };
474}; 483};
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 6315d6fcc58a..bdf4459677b1 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -71,6 +71,13 @@
71 reg = <0x200 0x100>; 71 reg = <0x200 0x100>;
72 }; 72 };
73 73
74 pmc: power@b00 {
75 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
76 reg = <0xb00 0x100 0xa00 0x100>;
77 interrupts = <80 0x8>;
78 interrupt-parent = <&ipic>;
79 };
80
74 i2c@3000 { 81 i2c@3000 {
75 #address-cells = <1>; 82 #address-cells = <1>;
76 #size-cells = <0>; 83 #size-cells = <0>;
@@ -161,6 +168,7 @@
161 fsl,channel-fifo-len = <24>; 168 fsl,channel-fifo-len = <24>;
162 fsl,exec-units-mask = <0x7e>; 169 fsl,exec-units-mask = <0x7e>;
163 fsl,descriptor-types-mask = <0x01010ebf>; 170 fsl,descriptor-types-mask = <0x01010ebf>;
171 sleep = <&pmc 0x03000000>;
164 }; 172 };
165 173
166 ipic: interrupt-controller@700 { 174 ipic: interrupt-controller@700 {
@@ -455,6 +463,7 @@
455 0xa800 0 0 2 &ipic 20 8 463 0xa800 0 0 2 &ipic 20 8
456 0xa800 0 0 3 &ipic 21 8 464 0xa800 0 0 3 &ipic 21 8
457 0xa800 0 0 4 &ipic 18 8>; 465 0xa800 0 0 4 &ipic 18 8>;
466 sleep = <&pmc 0x00010000>;
458 /* filled by u-boot */ 467 /* filled by u-boot */
459 bus-range = <0 0>; 468 bus-range = <0 0>;
460 clock-frequency = <0>; 469 clock-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 00c2bbda7013..92fb17876e7d 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -40,6 +40,8 @@
40 i-cache-line-size = <32>; // 32 bytes 40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K 41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K 42 i-cache-size = <0x8000>; // L1, 32K
43 sleep = <&pmc 0x00008000 // core
44 &pmc 0x00004000>; // timebase
43 timebase-frequency = <0>; 45 timebase-frequency = <0>;
44 bus-frequency = <0>; 46 bus-frequency = <0>;
45 clock-frequency = <0>; 47 clock-frequency = <0>;
@@ -52,9 +54,52 @@
52 reg = <0x0 0x10000000>; 54 reg = <0x0 0x10000000>;
53 }; 55 };
54 56
55 bcsr@f8000000 { 57 localbus@e0005000 {
56 compatible = "fsl,mpc8568mds-bcsr"; 58 #address-cells = <2>;
57 reg = <0xf8000000 0x8000>; 59 #size-cells = <1>;
60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
61 "simple-bus";
62 reg = <0xe0005000 0x1000>;
63
64 ranges = <0x0 0x0 0xfe000000 0x02000000
65 0x1 0x0 0xf8000000 0x00008000
66 0x2 0x0 0xf0000000 0x04000000
67 0x4 0x0 0xf8008000 0x00008000
68 0x5 0x0 0xf8010000 0x00008000>;
69
70 nor@0,0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "cfi-flash";
74 reg = <0x0 0x0 0x02000000>;
75 bank-width = <2>;
76 device-width = <2>;
77 };
78
79 bcsr@1,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,mpc8568mds-bcsr";
83 reg = <1 0 0x8000>;
84 ranges = <0 1 0 0x8000>;
85
86 bcsr5: gpio-controller@11 {
87 #gpio-cells = <2>;
88 compatible = "fsl,mpc8568mds-bcsr-gpio";
89 reg = <0x5 0x1>;
90 gpio-controller;
91 };
92 };
93
94 pib@4,0 {
95 compatible = "fsl,mpc8568mds-pib";
96 reg = <4 0 0x8000>;
97 };
98
99 pib@5,0 {
100 compatible = "fsl,mpc8568mds-pib";
101 reg = <5 0 0x8000>;
102 };
58 }; 103 };
59 104
60 soc8568@e0000000 { 105 soc8568@e0000000 {
@@ -94,31 +139,41 @@
94 interrupts = <16 2>; 139 interrupts = <16 2>;
95 }; 140 };
96 141
97 i2c@3000 { 142 i2c-sleep-nexus {
98 #address-cells = <1>; 143 #address-cells = <1>;
99 #size-cells = <0>; 144 #size-cells = <1>;
100 cell-index = <0>; 145 compatible = "simple-bus";
101 compatible = "fsl-i2c"; 146 sleep = <&pmc 0x00000004>;
102 reg = <0x3000 0x100>; 147 ranges;
103 interrupts = <43 2>; 148
104 interrupt-parent = <&mpic>; 149 i2c@3000 {
105 dfsrr; 150 #address-cells = <1>;
151 #size-cells = <0>;
152 cell-index = <0>;
153 compatible = "fsl-i2c";
154 reg = <0x3000 0x100>;
155 interrupts = <43 2>;
156 interrupt-parent = <&mpic>;
157 dfsrr;
106 158
107 rtc@68 { 159 rtc@68 {
108 compatible = "dallas,ds1374"; 160 compatible = "dallas,ds1374";
109 reg = <0x68>; 161 reg = <0x68>;
162 interrupts = <3 1>;
163 interrupt-parent = <&mpic>;
164 };
110 }; 165 };
111 };
112 166
113 i2c@3100 { 167 i2c@3100 {
114 #address-cells = <1>; 168 #address-cells = <1>;
115 #size-cells = <0>; 169 #size-cells = <0>;
116 cell-index = <1>; 170 cell-index = <1>;
117 compatible = "fsl-i2c"; 171 compatible = "fsl-i2c";
118 reg = <0x3100 0x100>; 172 reg = <0x3100 0x100>;
119 interrupts = <43 2>; 173 interrupts = <43 2>;
120 interrupt-parent = <&mpic>; 174 interrupt-parent = <&mpic>;
121 dfsrr; 175 dfsrr;
176 };
122 }; 177 };
123 178
124 dma@21300 { 179 dma@21300 {
@@ -128,6 +183,8 @@
128 reg = <0x21300 0x4>; 183 reg = <0x21300 0x4>;
129 ranges = <0x0 0x21100 0x200>; 184 ranges = <0x0 0x21100 0x200>;
130 cell-index = <0>; 185 cell-index = <0>;
186 sleep = <&pmc 0x00000400>;
187
131 dma-channel@0 { 188 dma-channel@0 {
132 compatible = "fsl,mpc8568-dma-channel", 189 compatible = "fsl,mpc8568-dma-channel",
133 "fsl,eloplus-dma-channel"; 190 "fsl,eloplus-dma-channel";
@@ -176,6 +233,7 @@
176 interrupt-parent = <&mpic>; 233 interrupt-parent = <&mpic>;
177 tbi-handle = <&tbi0>; 234 tbi-handle = <&tbi0>;
178 phy-handle = <&phy2>; 235 phy-handle = <&phy2>;
236 sleep = <&pmc 0x00000080>;
179 237
180 mdio@520 { 238 mdio@520 {
181 #address-cells = <1>; 239 #address-cells = <1>;
@@ -228,6 +286,7 @@
228 interrupt-parent = <&mpic>; 286 interrupt-parent = <&mpic>;
229 tbi-handle = <&tbi1>; 287 tbi-handle = <&tbi1>;
230 phy-handle = <&phy3>; 288 phy-handle = <&phy3>;
289 sleep = <&pmc 0x00000040>;
231 290
232 mdio@520 { 291 mdio@520 {
233 #address-cells = <1>; 292 #address-cells = <1>;
@@ -242,30 +301,47 @@
242 }; 301 };
243 }; 302 };
244 303
245 serial0: serial@4500 { 304 duart-sleep-nexus {
246 cell-index = <0>; 305 #address-cells = <1>;
247 device_type = "serial"; 306 #size-cells = <1>;
248 compatible = "ns16550"; 307 compatible = "simple-bus";
249 reg = <0x4500 0x100>; 308 sleep = <&pmc 0x00000002>;
250 clock-frequency = <0>; 309 ranges;
251 interrupts = <42 2>; 310
252 interrupt-parent = <&mpic>; 311 serial0: serial@4500 {
312 cell-index = <0>;
313 device_type = "serial";
314 compatible = "ns16550";
315 reg = <0x4500 0x100>;
316 clock-frequency = <0>;
317 interrupts = <42 2>;
318 interrupt-parent = <&mpic>;
319 };
320
321 serial1: serial@4600 {
322 cell-index = <1>;
323 device_type = "serial";
324 compatible = "ns16550";
325 reg = <0x4600 0x100>;
326 clock-frequency = <0>;
327 interrupts = <42 2>;
328 interrupt-parent = <&mpic>;
329 };
253 }; 330 };
254 331
255 global-utilities@e0000 { //global utilities block 332 global-utilities@e0000 {
256 compatible = "fsl,mpc8548-guts"; 333 #address-cells = <1>;
334 #size-cells = <1>;
335 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
257 reg = <0xe0000 0x1000>; 336 reg = <0xe0000 0x1000>;
337 ranges = <0 0xe0000 0x1000>;
258 fsl,has-rstcr; 338 fsl,has-rstcr;
259 };
260 339
261 serial1: serial@4600 { 340 pmc: power@70 {
262 cell-index = <1>; 341 compatible = "fsl,mpc8568-pmc",
263 device_type = "serial"; 342 "fsl,mpc8548-pmc";
264 compatible = "ns16550"; 343 reg = <0x70 0x20>;
265 reg = <0x4600 0x100>; 344 };
266 clock-frequency = <0>;
267 interrupts = <42 2>;
268 interrupt-parent = <&mpic>;
269 }; 345 };
270 346
271 crypto@30000 { 347 crypto@30000 {
@@ -277,6 +353,7 @@
277 fsl,channel-fifo-len = <24>; 353 fsl,channel-fifo-len = <24>;
278 fsl,exec-units-mask = <0xfe>; 354 fsl,exec-units-mask = <0xfe>;
279 fsl,descriptor-types-mask = <0x12b0ebf>; 355 fsl,descriptor-types-mask = <0x12b0ebf>;
356 sleep = <&pmc 0x01000000>;
280 }; 357 };
281 358
282 mpic: pic@40000 { 359 mpic: pic@40000 {
@@ -376,6 +453,7 @@
376 compatible = "fsl,qe"; 453 compatible = "fsl,qe";
377 ranges = <0x0 0xe0080000 0x40000>; 454 ranges = <0x0 0xe0080000 0x40000>;
378 reg = <0xe0080000 0x480>; 455 reg = <0xe0080000 0x480>;
456 sleep = <&pmc 0x00000800>;
379 brg-frequency = <0>; 457 brg-frequency = <0>;
380 bus-frequency = <396000000>; 458 bus-frequency = <396000000>;
381 fsl,qe-num-riscs = <2>; 459 fsl,qe-num-riscs = <2>;
@@ -509,6 +587,7 @@
509 bus-range = <0 255>; 587 bus-range = <0 255>;
510 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 588 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
511 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>; 589 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
590 sleep = <&pmc 0x80000000>;
512 clock-frequency = <66666666>; 591 clock-frequency = <66666666>;
513 #interrupt-cells = <1>; 592 #interrupt-cells = <1>;
514 #size-cells = <2>; 593 #size-cells = <2>;
@@ -534,6 +613,7 @@
534 bus-range = <0 255>; 613 bus-range = <0 255>;
535 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 614 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
536 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>; 615 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
616 sleep = <&pmc 0x20000000>;
537 clock-frequency = <33333333>; 617 clock-frequency = <33333333>;
538 #interrupt-cells = <1>; 618 #interrupt-cells = <1>;
539 #size-cells = <2>; 619 #size-cells = <2>;
@@ -570,5 +650,23 @@
570 55 2 /* msg2_tx */ 650 55 2 /* msg2_tx */
571 56 2 /* msg2_rx */>; 651 56 2 /* msg2_rx */>;
572 interrupt-parent = <&mpic>; 652 interrupt-parent = <&mpic>;
653 sleep = <&pmc 0x00080000 /* controller */
654 &pmc 0x00040000>; /* message unit */
655 };
656
657 leds {
658 compatible = "gpio-leds";
659
660 green {
661 gpios = <&bcsr5 1 0>;
662 };
663
664 amber {
665 gpios = <&bcsr5 2 0>;
666 };
667
668 red {
669 gpios = <&bcsr5 3 0>;
670 };
573 }; 671 };
574}; 672};
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 1e3ec8f059bf..8b72eaff5b03 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -41,6 +41,8 @@
41 i-cache-line-size = <32>; // 32 bytes 41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K 42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K 43 i-cache-size = <0x8000>; // L1, 32K
44 sleep = <&pmc 0x00008000 // core
45 &pmc 0x00004000>; // timebase
44 timebase-frequency = <0>; 46 timebase-frequency = <0>;
45 bus-frequency = <0>; 47 bus-frequency = <0>;
46 clock-frequency = <0>; 48 clock-frequency = <0>;
@@ -59,6 +61,7 @@
59 reg = <0xe0005000 0x1000>; 61 reg = <0xe0005000 0x1000>;
60 interrupts = <19 2>; 62 interrupts = <19 2>;
61 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 sleep = <&pmc 0x08000000>;
62 65
63 ranges = <0x0 0x0 0xfe000000 0x02000000 66 ranges = <0x0 0x0 0xfe000000 0x02000000
64 0x1 0x0 0xf8000000 0x00008000 67 0x1 0x0 0xf8000000 0x00008000
@@ -158,51 +161,69 @@
158 interrupts = <18 2>; 161 interrupts = <18 2>;
159 }; 162 };
160 163
161 i2c@3000 { 164 i2c-sleep-nexus {
162 #address-cells = <1>; 165 #address-cells = <1>;
163 #size-cells = <0>; 166 #size-cells = <1>;
164 cell-index = <0>; 167 compatible = "simple-bus";
165 compatible = "fsl-i2c"; 168 sleep = <&pmc 0x00000004>;
166 reg = <0x3000 0x100>; 169 ranges;
167 interrupts = <43 2>;
168 interrupt-parent = <&mpic>;
169 dfsrr;
170 170
171 rtc@68 { 171 i2c@3000 {
172 compatible = "dallas,ds1374"; 172 #address-cells = <1>;
173 reg = <0x68>; 173 #size-cells = <0>;
174 cell-index = <0>;
175 compatible = "fsl-i2c";
176 reg = <0x3000 0x100>;
177 interrupts = <43 2>;
178 interrupt-parent = <&mpic>;
179 dfsrr;
180
181 rtc@68 {
182 compatible = "dallas,ds1374";
183 reg = <0x68>;
184 interrupts = <3 1>;
185 interrupt-parent = <&mpic>;
186 };
187 };
188
189 i2c@3100 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 cell-index = <1>;
193 compatible = "fsl-i2c";
194 reg = <0x3100 0x100>;
195 interrupts = <43 2>;
196 interrupt-parent = <&mpic>;
197 dfsrr;
174 }; 198 };
175 }; 199 };
176 200
177 i2c@3100 { 201 duart-sleep-nexus {
178 #address-cells = <1>; 202 #address-cells = <1>;
179 #size-cells = <0>; 203 #size-cells = <1>;
180 cell-index = <1>; 204 compatible = "simple-bus";
181 compatible = "fsl-i2c"; 205 sleep = <&pmc 0x00000002>;
182 reg = <0x3100 0x100>; 206 ranges;
183 interrupts = <43 2>;
184 interrupt-parent = <&mpic>;
185 dfsrr;
186 };
187 207
188 serial0: serial@4500 { 208 serial0: serial@4500 {
189 cell-index = <0>; 209 cell-index = <0>;
190 device_type = "serial"; 210 device_type = "serial";
191 compatible = "ns16550"; 211 compatible = "ns16550";
192 reg = <0x4500 0x100>; 212 reg = <0x4500 0x100>;
193 clock-frequency = <0>; 213 clock-frequency = <0>;
194 interrupts = <42 2>; 214 interrupts = <42 2>;
195 interrupt-parent = <&mpic>; 215 interrupt-parent = <&mpic>;
196 }; 216 };
197 217
198 serial1: serial@4600 { 218 serial1: serial@4600 {
199 cell-index = <1>; 219 cell-index = <1>;
200 device_type = "serial"; 220 device_type = "serial";
201 compatible = "ns16550"; 221 compatible = "ns16550";
202 reg = <0x4600 0x100>; 222 reg = <0x4600 0x100>;
203 clock-frequency = <0>; 223 clock-frequency = <0>;
204 interrupts = <42 2>; 224 interrupts = <42 2>;
205 interrupt-parent = <&mpic>; 225 interrupt-parent = <&mpic>;
226 };
206 }; 227 };
207 228
208 L2: l2-cache-controller@20000 { 229 L2: l2-cache-controller@20000 {
@@ -260,6 +281,7 @@
260 reg = <0x2e000 0x1000>; 281 reg = <0x2e000 0x1000>;
261 interrupts = <72 0x8>; 282 interrupts = <72 0x8>;
262 interrupt-parent = <&mpic>; 283 interrupt-parent = <&mpic>;
284 sleep = <&pmc 0x00200000>;
263 /* Filled in by U-Boot */ 285 /* Filled in by U-Boot */
264 clock-frequency = <0>; 286 clock-frequency = <0>;
265 status = "disabled"; 287 status = "disabled";
@@ -276,6 +298,7 @@
276 fsl,channel-fifo-len = <24>; 298 fsl,channel-fifo-len = <24>;
277 fsl,exec-units-mask = <0xbfe>; 299 fsl,exec-units-mask = <0xbfe>;
278 fsl,descriptor-types-mask = <0x3ab0ebf>; 300 fsl,descriptor-types-mask = <0x3ab0ebf>;
301 sleep = <&pmc 0x01000000>;
279 }; 302 };
280 303
281 mpic: pic@40000 { 304 mpic: pic@40000 {
@@ -304,9 +327,18 @@
304 }; 327 };
305 328
306 global-utilities@e0000 { 329 global-utilities@e0000 {
307 compatible = "fsl,mpc8569-guts"; 330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
308 reg = <0xe0000 0x1000>; 333 reg = <0xe0000 0x1000>;
334 ranges = <0 0xe0000 0x1000>;
309 fsl,has-rstcr; 335 fsl,has-rstcr;
336
337 pmc: power@70 {
338 compatible = "fsl,mpc8569-pmc",
339 "fsl,mpc8548-pmc";
340 reg = <0x70 0x20>;
341 };
310 }; 342 };
311 343
312 par_io@e0100 { 344 par_io@e0100 {
@@ -422,6 +454,7 @@
422 compatible = "fsl,qe"; 454 compatible = "fsl,qe";
423 ranges = <0x0 0xe0080000 0x40000>; 455 ranges = <0x0 0xe0080000 0x40000>;
424 reg = <0xe0080000 0x480>; 456 reg = <0xe0080000 0x480>;
457 sleep = <&pmc 0x00000800>;
425 brg-frequency = <0>; 458 brg-frequency = <0>;
426 bus-frequency = <0>; 459 bus-frequency = <0>;
427 fsl,qe-num-riscs = <4>; 460 fsl,qe-num-riscs = <4>;
@@ -502,6 +535,7 @@
502 rx-clock-name = "none"; 535 rx-clock-name = "none";
503 tx-clock-name = "clk12"; 536 tx-clock-name = "clk12";
504 pio-handle = <&pio1>; 537 pio-handle = <&pio1>;
538 tbi-handle = <&tbi1>;
505 phy-handle = <&qe_phy0>; 539 phy-handle = <&qe_phy0>;
506 phy-connection-type = "rgmii-id"; 540 phy-connection-type = "rgmii-id";
507 }; 541 };
@@ -546,7 +580,7 @@
546 reg = <0x6>; 580 reg = <0x6>;
547 device_type = "ethernet-phy"; 581 device_type = "ethernet-phy";
548 }; 582 };
549 tbi-phy@11 { 583 tbi1: tbi-phy@11 {
550 reg = <0x11>; 584 reg = <0x11>;
551 device_type = "tbi-phy"; 585 device_type = "tbi-phy";
552 }; 586 };
@@ -557,7 +591,7 @@
557 reg = <0x3520 0x18>; 591 reg = <0x3520 0x18>;
558 compatible = "fsl,ucc-mdio"; 592 compatible = "fsl,ucc-mdio";
559 593
560 tbi0: tbi-phy@15 { 594 tbi6: tbi-phy@15 {
561 reg = <0x15>; 595 reg = <0x15>;
562 device_type = "tbi-phy"; 596 device_type = "tbi-phy";
563 }; 597 };
@@ -567,7 +601,7 @@
567 #size-cells = <0>; 601 #size-cells = <0>;
568 reg = <0x3720 0x38>; 602 reg = <0x3720 0x38>;
569 compatible = "fsl,ucc-mdio"; 603 compatible = "fsl,ucc-mdio";
570 tbi1: tbi-phy@17 { 604 tbi8: tbi-phy@17 {
571 reg = <0x17>; 605 reg = <0x17>;
572 device_type = "tbi-phy"; 606 device_type = "tbi-phy";
573 }; 607 };
@@ -584,10 +618,22 @@
584 rx-clock-name = "none"; 618 rx-clock-name = "none";
585 tx-clock-name = "clk12"; 619 tx-clock-name = "clk12";
586 pio-handle = <&pio3>; 620 pio-handle = <&pio3>;
621 tbi-handle = <&tbi3>;
587 phy-handle = <&qe_phy2>; 622 phy-handle = <&qe_phy2>;
588 phy-connection-type = "rgmii-id"; 623 phy-connection-type = "rgmii-id";
589 }; 624 };
590 625
626 mdio@2320 {
627 #address-cells = <1>;
628 #size-cells = <0>;
629 reg = <0x2320 0x18>;
630 compatible = "fsl,ucc-mdio";
631 tbi3: tbi-phy@11 {
632 reg = <0x11>;
633 device_type = "tbi-phy";
634 };
635 };
636
591 enet1: ucc@3000 { 637 enet1: ucc@3000 {
592 device_type = "network"; 638 device_type = "network";
593 compatible = "ucc_geth"; 639 compatible = "ucc_geth";
@@ -599,10 +645,22 @@
599 rx-clock-name = "none"; 645 rx-clock-name = "none";
600 tx-clock-name = "clk17"; 646 tx-clock-name = "clk17";
601 pio-handle = <&pio2>; 647 pio-handle = <&pio2>;
648 tbi-handle = <&tbi2>;
602 phy-handle = <&qe_phy1>; 649 phy-handle = <&qe_phy1>;
603 phy-connection-type = "rgmii-id"; 650 phy-connection-type = "rgmii-id";
604 }; 651 };
605 652
653 mdio@3120 {
654 #address-cells = <1>;
655 #size-cells = <0>;
656 reg = <0x3120 0x18>;
657 compatible = "fsl,ucc-mdio";
658 tbi2: tbi-phy@11 {
659 reg = <0x11>;
660 device_type = "tbi-phy";
661 };
662 };
663
606 enet3: ucc@3200 { 664 enet3: ucc@3200 {
607 device_type = "network"; 665 device_type = "network";
608 compatible = "ucc_geth"; 666 compatible = "ucc_geth";
@@ -614,10 +672,22 @@
614 rx-clock-name = "none"; 672 rx-clock-name = "none";
615 tx-clock-name = "clk17"; 673 tx-clock-name = "clk17";
616 pio-handle = <&pio4>; 674 pio-handle = <&pio4>;
675 tbi-handle = <&tbi4>;
617 phy-handle = <&qe_phy3>; 676 phy-handle = <&qe_phy3>;
618 phy-connection-type = "rgmii-id"; 677 phy-connection-type = "rgmii-id";
619 }; 678 };
620 679
680 mdio@3320 {
681 #address-cells = <1>;
682 #size-cells = <0>;
683 reg = <0x3320 0x18>;
684 compatible = "fsl,ucc-mdio";
685 tbi4: tbi-phy@11 {
686 reg = <0x11>;
687 device_type = "tbi-phy";
688 };
689 };
690
621 enet5: ucc@3400 { 691 enet5: ucc@3400 {
622 device_type = "network"; 692 device_type = "network";
623 compatible = "ucc_geth"; 693 compatible = "ucc_geth";
@@ -628,7 +698,7 @@
628 local-mac-address = [ 00 00 00 00 00 00 ]; 698 local-mac-address = [ 00 00 00 00 00 00 ];
629 rx-clock-name = "none"; 699 rx-clock-name = "none";
630 tx-clock-name = "none"; 700 tx-clock-name = "none";
631 tbi-handle = <&tbi0>; 701 tbi-handle = <&tbi6>;
632 phy-handle = <&qe_phy5>; 702 phy-handle = <&qe_phy5>;
633 phy-connection-type = "sgmii"; 703 phy-connection-type = "sgmii";
634 }; 704 };
@@ -643,7 +713,7 @@
643 local-mac-address = [ 00 00 00 00 00 00 ]; 713 local-mac-address = [ 00 00 00 00 00 00 ];
644 rx-clock-name = "none"; 714 rx-clock-name = "none";
645 tx-clock-name = "none"; 715 tx-clock-name = "none";
646 tbi-handle = <&tbi1>; 716 tbi-handle = <&tbi8>;
647 phy-handle = <&qe_phy7>; 717 phy-handle = <&qe_phy7>;
648 phy-connection-type = "sgmii"; 718 phy-connection-type = "sgmii";
649 }; 719 };
@@ -684,6 +754,7 @@
684 bus-range = <0 255>; 754 bus-range = <0 255>;
685 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 755 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
686 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>; 756 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
757 sleep = <&pmc 0x20000000>;
687 clock-frequency = <33333333>; 758 clock-frequency = <33333333>;
688 pcie@0 { 759 pcie@0 {
689 reg = <0x0 0x0 0x0 0x0 0x0>; 760 reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -714,5 +785,6 @@
714 55 2 /* msg2_tx */ 785 55 2 /* msg2_tx */
715 56 2 /* msg2_rx */>; 786 56 2 /* msg2_rx */>;
716 interrupt-parent = <&mpic>; 787 interrupt-parent = <&mpic>;
788 sleep = <&pmc 0x00080000>;
717 }; 789 };
718}; 790};
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index f468d215f716..9535ce68caae 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -35,6 +35,8 @@
35 i-cache-line-size = <32>; 35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; // L1 36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1 37 i-cache-size = <32768>; // L1
38 sleep = <&pmc 0x00008000 0 // core
39 &pmc 0x00004000 0>; // timebase
38 timebase-frequency = <0>; // From uboot 40 timebase-frequency = <0>; // From uboot
39 bus-frequency = <0>; // From uboot 41 bus-frequency = <0>; // From uboot
40 clock-frequency = <0>; // From uboot 42 clock-frequency = <0>; // From uboot
@@ -60,6 +62,7 @@
60 5 0 0xe8480000 0x00008000 62 5 0 0xe8480000 0x00008000
61 6 0 0xe84c0000 0x00008000 63 6 0 0xe84c0000 0x00008000
62 3 0 0xe8000000 0x00000020>; 64 3 0 0xe8000000 0x00000020>;
65 sleep = <&pmc 0x08000000 0>;
63 66
64 flash@0,0 { 67 flash@0,0 {
65 compatible = "cfi-flash"; 68 compatible = "cfi-flash";
@@ -105,6 +108,8 @@
105 compatible = "fsl,fpga-pixis"; 108 compatible = "fsl,fpga-pixis";
106 reg = <3 0 0x20>; 109 reg = <3 0 0x20>;
107 ranges = <0 3 0 0x20>; 110 ranges = <0 3 0 0x20>;
111 interrupt-parent = <&mpic>;
112 interrupts = <8 8>;
108 113
109 sdcsr_pio: gpio-controller@a { 114 sdcsr_pio: gpio-controller@a {
110 #gpio-cells = <2>; 115 #gpio-cells = <2>;
@@ -163,6 +168,7 @@
163 reg = <0x3100 0x100>; 168 reg = <0x3100 0x100>;
164 interrupts = <43 2>; 169 interrupts = <43 2>;
165 interrupt-parent = <&mpic>; 170 interrupt-parent = <&mpic>;
171 sleep = <&pmc 0x00000004 0>;
166 dfsrr; 172 dfsrr;
167 }; 173 };
168 174
@@ -174,6 +180,7 @@
174 clock-frequency = <0>; 180 clock-frequency = <0>;
175 interrupts = <42 2>; 181 interrupts = <42 2>;
176 interrupt-parent = <&mpic>; 182 interrupt-parent = <&mpic>;
183 sleep = <&pmc 0x00000002 0>;
177 }; 184 };
178 185
179 serial1: serial@4600 { 186 serial1: serial@4600 {
@@ -184,6 +191,7 @@
184 clock-frequency = <0>; 191 clock-frequency = <0>;
185 interrupts = <42 2>; 192 interrupts = <42 2>;
186 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
194 sleep = <&pmc 0x00000008 0>;
187 }; 195 };
188 196
189 spi@7000 { 197 spi@7000 {
@@ -196,6 +204,7 @@
196 interrupt-parent = <&mpic>; 204 interrupt-parent = <&mpic>;
197 mode = "cpu"; 205 mode = "cpu";
198 gpios = <&sdcsr_pio 7 0>; 206 gpios = <&sdcsr_pio 7 0>;
207 sleep = <&pmc 0x00000800 0>;
199 208
200 mmc-slot@0 { 209 mmc-slot@0 {
201 compatible = "fsl,mpc8610hpcd-mmc-slot", 210 compatible = "fsl,mpc8610hpcd-mmc-slot",
@@ -213,6 +222,7 @@
213 reg = <0x2c000 100>; 222 reg = <0x2c000 100>;
214 interrupts = <72 2>; 223 interrupts = <72 2>;
215 interrupt-parent = <&mpic>; 224 interrupt-parent = <&mpic>;
225 sleep = <&pmc 0x04000000 0>;
216 }; 226 };
217 227
218 mpic: interrupt-controller@40000 { 228 mpic: interrupt-controller@40000 {
@@ -241,9 +251,18 @@
241 }; 251 };
242 252
243 global-utilities@e0000 { 253 global-utilities@e0000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
244 compatible = "fsl,mpc8610-guts"; 256 compatible = "fsl,mpc8610-guts";
245 reg = <0xe0000 0x1000>; 257 reg = <0xe0000 0x1000>;
258 ranges = <0 0xe0000 0x1000>;
246 fsl,has-rstcr; 259 fsl,has-rstcr;
260
261 pmc: power@70 {
262 compatible = "fsl,mpc8610-pmc",
263 "fsl,mpc8641d-pmc";
264 reg = <0x70 0x20>;
265 };
247 }; 266 };
248 267
249 wdt@e4000 { 268 wdt@e4000 {
@@ -262,6 +281,7 @@
262 fsl,playback-dma = <&dma00>; 281 fsl,playback-dma = <&dma00>;
263 fsl,capture-dma = <&dma01>; 282 fsl,capture-dma = <&dma01>;
264 fsl,fifo-depth = <8>; 283 fsl,fifo-depth = <8>;
284 sleep = <&pmc 0 0x08000000>;
265 }; 285 };
266 286
267 ssi@16100 { 287 ssi@16100 {
@@ -271,6 +291,7 @@
271 interrupt-parent = <&mpic>; 291 interrupt-parent = <&mpic>;
272 interrupts = <63 2>; 292 interrupts = <63 2>;
273 fsl,fifo-depth = <8>; 293 fsl,fifo-depth = <8>;
294 sleep = <&pmc 0 0x04000000>;
274 }; 295 };
275 296
276 dma@21300 { 297 dma@21300 {
@@ -280,6 +301,7 @@
280 cell-index = <0>; 301 cell-index = <0>;
281 reg = <0x21300 0x4>; /* DMA general status register */ 302 reg = <0x21300 0x4>; /* DMA general status register */
282 ranges = <0x0 0x21100 0x200>; 303 ranges = <0x0 0x21100 0x200>;
304 sleep = <&pmc 0x00000400 0>;
283 305
284 dma00: dma-channel@0 { 306 dma00: dma-channel@0 {
285 compatible = "fsl,mpc8610-dma-channel", 307 compatible = "fsl,mpc8610-dma-channel",
@@ -322,6 +344,7 @@
322 cell-index = <1>; 344 cell-index = <1>;
323 reg = <0xc300 0x4>; /* DMA general status register */ 345 reg = <0xc300 0x4>; /* DMA general status register */
324 ranges = <0x0 0xc100 0x200>; 346 ranges = <0x0 0xc100 0x200>;
347 sleep = <&pmc 0x00000200 0>;
325 348
326 dma-channel@0 { 349 dma-channel@0 {
327 compatible = "fsl,mpc8610-dma-channel", 350 compatible = "fsl,mpc8610-dma-channel",
@@ -369,6 +392,7 @@
369 bus-range = <0 0>; 392 bus-range = <0 0>;
370 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 393 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
371 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>; 394 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
395 sleep = <&pmc 0x80000000 0>;
372 clock-frequency = <33333333>; 396 clock-frequency = <33333333>;
373 interrupt-parent = <&mpic>; 397 interrupt-parent = <&mpic>;
374 interrupts = <24 2>; 398 interrupts = <24 2>;
@@ -398,6 +422,7 @@
398 bus-range = <1 3>; 422 bus-range = <1 3>;
399 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 423 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
400 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; 424 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
425 sleep = <&pmc 0x40000000 0>;
401 clock-frequency = <33333333>; 426 clock-frequency = <33333333>;
402 interrupt-parent = <&mpic>; 427 interrupt-parent = <&mpic>;
403 interrupts = <26 2>; 428 interrupts = <26 2>;
@@ -474,6 +499,7 @@
474 0x0000 0 0 4 &mpic 7 1>; 499 0x0000 0 0 4 &mpic 7 1>;
475 interrupt-parent = <&mpic>; 500 interrupt-parent = <&mpic>;
476 interrupts = <25 2>; 501 interrupts = <25 2>;
502 sleep = <&pmc 0x20000000 0>;
477 clock-frequency = <33333333>; 503 clock-frequency = <33333333>;
478 }; 504 };
479}; 505};
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000000000000..df5269093af8
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
1/*
2 * P1020 RDB Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P1020";
15 compatible = "fsl,P1020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 pci0 = &pci0;
23 pci1 = &pci1;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,P1020@0 {
31 device_type = "cpu";
32 reg = <0x0>;
33 next-level-cache = <&L2>;
34 };
35
36 PowerPC,P1020@1 {
37 device_type = "cpu";
38 reg = <0x1>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 };
46
47 localbus@ffe05000 {
48 #address-cells = <2>;
49 #size-cells = <1>;
50 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
51 reg = <0 0xffe05000 0 0x1000>;
52 interrupts = <19 2>;
53 interrupt-parent = <&mpic>;
54
55 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
56 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
57 0x1 0x0 0x0 0xffa00000 0x00040000
58 0x2 0x0 0x0 0xffb00000 0x00020000>;
59
60 nor@0,0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "cfi-flash";
64 reg = <0x0 0x0 0x1000000>;
65 bank-width = <2>;
66 device-width = <1>;
67
68 partition@0 {
69 /* This location must not be altered */
70 /* 256KB for Vitesse 7385 Switch firmware */
71 reg = <0x0 0x00040000>;
72 label = "NOR (RO) Vitesse-7385 Firmware";
73 read-only;
74 };
75
76 partition@40000 {
77 /* 256KB for DTB Image */
78 reg = <0x00040000 0x00040000>;
79 label = "NOR (RO) DTB Image";
80 read-only;
81 };
82
83 partition@80000 {
84 /* 3.5 MB for Linux Kernel Image */
85 reg = <0x00080000 0x00380000>;
86 label = "NOR (RO) Linux Kernel Image";
87 read-only;
88 };
89
90 partition@400000 {
91 /* 11MB for JFFS2 based Root file System */
92 reg = <0x00400000 0x00b00000>;
93 label = "NOR (RW) JFFS2 Root File System";
94 };
95
96 partition@f00000 {
97 /* This location must not be altered */
98 /* 512KB for u-boot Bootloader Image */
99 /* 512KB for u-boot Environment Variables */
100 reg = <0x00f00000 0x00100000>;
101 label = "NOR (RO) U-Boot Image";
102 read-only;
103 };
104 };
105
106 nand@1,0 {
107 #address-cells = <1>;
108 #size-cells = <1>;
109 compatible = "fsl,p1020-fcm-nand",
110 "fsl,elbc-fcm-nand";
111 reg = <0x1 0x0 0x40000>;
112
113 partition@0 {
114 /* This location must not be altered */
115 /* 1MB for u-boot Bootloader Image */
116 reg = <0x0 0x00100000>;
117 label = "NAND (RO) U-Boot Image";
118 read-only;
119 };
120
121 partition@100000 {
122 /* 1MB for DTB Image */
123 reg = <0x00100000 0x00100000>;
124 label = "NAND (RO) DTB Image";
125 read-only;
126 };
127
128 partition@200000 {
129 /* 4MB for Linux Kernel Image */
130 reg = <0x00200000 0x00400000>;
131 label = "NAND (RO) Linux Kernel Image";
132 read-only;
133 };
134
135 partition@600000 {
136 /* 4MB for Compressed Root file System Image */
137 reg = <0x00600000 0x00400000>;
138 label = "NAND (RO) Compressed RFS Image";
139 read-only;
140 };
141
142 partition@a00000 {
143 /* 7MB for JFFS2 based Root file System */
144 reg = <0x00a00000 0x00700000>;
145 label = "NAND (RW) JFFS2 Root File System";
146 };
147
148 partition@1100000 {
149 /* 15MB for JFFS2 based Root file System */
150 reg = <0x01100000 0x00f00000>;
151 label = "NAND (RW) Writable User area";
152 };
153 };
154
155 L2switch@2,0 {
156 #address-cells = <1>;
157 #size-cells = <1>;
158 compatible = "vitesse-7385";
159 reg = <0x2 0x0 0x20000>;
160 };
161
162 };
163
164 soc@ffe00000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 device_type = "soc";
168 compatible = "fsl,p1020-immr", "simple-bus";
169 ranges = <0x0 0x0 0xffe00000 0x100000>;
170 bus-frequency = <0>; // Filled out by uboot.
171
172 ecm-law@0 {
173 compatible = "fsl,ecm-law";
174 reg = <0x0 0x1000>;
175 fsl,num-laws = <12>;
176 };
177
178 ecm@1000 {
179 compatible = "fsl,p1020-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>;
181 interrupts = <16 2>;
182 interrupt-parent = <&mpic>;
183 };
184
185 memory-controller@2000 {
186 compatible = "fsl,p1020-memory-controller";
187 reg = <0x2000 0x1000>;
188 interrupt-parent = <&mpic>;
189 interrupts = <16 2>;
190 };
191
192 i2c@3000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 cell-index = <0>;
196 compatible = "fsl-i2c";
197 reg = <0x3000 0x100>;
198 interrupts = <43 2>;
199 interrupt-parent = <&mpic>;
200 dfsrr;
201 rtc@68 {
202 compatible = "dallas,ds1339";
203 reg = <0x68>;
204 };
205 };
206
207 i2c@3100 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 cell-index = <1>;
211 compatible = "fsl-i2c";
212 reg = <0x3100 0x100>;
213 interrupts = <43 2>;
214 interrupt-parent = <&mpic>;
215 dfsrr;
216 };
217
218 serial0: serial@4500 {
219 cell-index = <0>;
220 device_type = "serial";
221 compatible = "ns16550";
222 reg = <0x4500 0x100>;
223 clock-frequency = <0>;
224 interrupts = <42 2>;
225 interrupt-parent = <&mpic>;
226 };
227
228 serial1: serial@4600 {
229 cell-index = <1>;
230 device_type = "serial";
231 compatible = "ns16550";
232 reg = <0x4600 0x100>;
233 clock-frequency = <0>;
234 interrupts = <42 2>;
235 interrupt-parent = <&mpic>;
236 };
237
238 spi@7000 {
239 cell-index = <0>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,espi";
243 reg = <0x7000 0x1000>;
244 interrupts = <59 0x2>;
245 interrupt-parent = <&mpic>;
246 mode = "cpu";
247
248 fsl_m25p80@0 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 compatible = "fsl,espi-flash";
252 reg = <0>;
253 linux,modalias = "fsl_m25p80";
254 modal = "s25sl128b";
255 spi-max-frequency = <50000000>;
256 mode = <0>;
257
258 partition@0 {
259 /* 512KB for u-boot Bootloader Image */
260 reg = <0x0 0x00080000>;
261 label = "SPI (RO) U-Boot Image";
262 read-only;
263 };
264
265 partition@80000 {
266 /* 512KB for DTB Image */
267 reg = <0x00080000 0x00080000>;
268 label = "SPI (RO) DTB Image";
269 read-only;
270 };
271
272 partition@100000 {
273 /* 4MB for Linux Kernel Image */
274 reg = <0x00100000 0x00400000>;
275 label = "SPI (RO) Linux Kernel Image";
276 read-only;
277 };
278
279 partition@500000 {
280 /* 4MB for Compressed RFS Image */
281 reg = <0x00500000 0x00400000>;
282 label = "SPI (RO) Compressed RFS Image";
283 read-only;
284 };
285
286 partition@900000 {
287 /* 7MB for JFFS2 based RFS */
288 reg = <0x00900000 0x00700000>;
289 label = "SPI (RW) JFFS2 RFS";
290 };
291 };
292 };
293
294 gpio: gpio-controller@f000 {
295 #gpio-cells = <2>;
296 compatible = "fsl,mpc8572-gpio";
297 reg = <0xf000 0x100>;
298 interrupts = <47 0x2>;
299 interrupt-parent = <&mpic>;
300 gpio-controller;
301 };
302
303 L2: l2-cache-controller@20000 {
304 compatible = "fsl,p1020-l2-cache-controller";
305 reg = <0x20000 0x1000>;
306 cache-line-size = <32>; // 32 bytes
307 cache-size = <0x40000>; // L2,256K
308 interrupt-parent = <&mpic>;
309 interrupts = <16 2>;
310 };
311
312 dma@21300 {
313 #address-cells = <1>;
314 #size-cells = <1>;
315 compatible = "fsl,eloplus-dma";
316 reg = <0x21300 0x4>;
317 ranges = <0x0 0x21100 0x200>;
318 cell-index = <0>;
319 dma-channel@0 {
320 compatible = "fsl,eloplus-dma-channel";
321 reg = <0x0 0x80>;
322 cell-index = <0>;
323 interrupt-parent = <&mpic>;
324 interrupts = <20 2>;
325 };
326 dma-channel@80 {
327 compatible = "fsl,eloplus-dma-channel";
328 reg = <0x80 0x80>;
329 cell-index = <1>;
330 interrupt-parent = <&mpic>;
331 interrupts = <21 2>;
332 };
333 dma-channel@100 {
334 compatible = "fsl,eloplus-dma-channel";
335 reg = <0x100 0x80>;
336 cell-index = <2>;
337 interrupt-parent = <&mpic>;
338 interrupts = <22 2>;
339 };
340 dma-channel@180 {
341 compatible = "fsl,eloplus-dma-channel";
342 reg = <0x180 0x80>;
343 cell-index = <3>;
344 interrupt-parent = <&mpic>;
345 interrupts = <23 2>;
346 };
347 };
348
349 usb@22000 {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 compatible = "fsl-usb2-dr";
353 reg = <0x22000 0x1000>;
354 interrupt-parent = <&mpic>;
355 interrupts = <28 0x2>;
356 phy_type = "ulpi";
357 };
358
359 usb@23000 {
360 #address-cells = <1>;
361 #size-cells = <0>;
362 compatible = "fsl-usb2-dr";
363 reg = <0x23000 0x1000>;
364 interrupt-parent = <&mpic>;
365 interrupts = <46 0x2>;
366 phy_type = "ulpi";
367 };
368
369 sdhci@2e000 {
370 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
371 reg = <0x2e000 0x1000>;
372 interrupts = <72 0x2>;
373 interrupt-parent = <&mpic>;
374 /* Filled in by U-Boot */
375 clock-frequency = <0>;
376 };
377
378 crypto@30000 {
379 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
380 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
381 reg = <0x30000 0x10000>;
382 interrupts = <45 2 58 2>;
383 interrupt-parent = <&mpic>;
384 fsl,num-channels = <4>;
385 fsl,channel-fifo-len = <24>;
386 fsl,exec-units-mask = <0xbfe>;
387 fsl,descriptor-types-mask = <0x3ab0ebf>;
388 };
389
390 mpic: pic@40000 {
391 interrupt-controller;
392 #address-cells = <0>;
393 #interrupt-cells = <2>;
394 reg = <0x40000 0x40000>;
395 compatible = "chrp,open-pic";
396 device_type = "open-pic";
397 };
398
399 msi@41600 {
400 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
401 reg = <0x41600 0x80>;
402 msi-available-ranges = <0 0x100>;
403 interrupts = <
404 0xe0 0
405 0xe1 0
406 0xe2 0
407 0xe3 0
408 0xe4 0
409 0xe5 0
410 0xe6 0
411 0xe7 0>;
412 interrupt-parent = <&mpic>;
413 };
414
415 global-utilities@e0000 { //global utilities block
416 compatible = "fsl,p1020-guts";
417 reg = <0xe0000 0x1000>;
418 fsl,has-rstcr;
419 };
420 };
421
422 pci0: pcie@ffe09000 {
423 compatible = "fsl,mpc8548-pcie";
424 device_type = "pci";
425 #interrupt-cells = <1>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 reg = <0 0xffe09000 0 0x1000>;
429 bus-range = <0 255>;
430 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
431 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
432 clock-frequency = <33333333>;
433 interrupt-parent = <&mpic>;
434 interrupts = <16 2>;
435 pcie@0 {
436 reg = <0x0 0x0 0x0 0x0 0x0>;
437 #size-cells = <2>;
438 #address-cells = <3>;
439 device_type = "pci";
440 ranges = <0x2000000 0x0 0xa0000000
441 0x2000000 0x0 0xa0000000
442 0x0 0x20000000
443
444 0x1000000 0x0 0x0
445 0x1000000 0x0 0x0
446 0x0 0x100000>;
447 };
448 };
449
450 pci1: pcie@ffe0a000 {
451 compatible = "fsl,mpc8548-pcie";
452 device_type = "pci";
453 #interrupt-cells = <1>;
454 #size-cells = <2>;
455 #address-cells = <3>;
456 reg = <0 0xffe0a000 0 0x1000>;
457 bus-range = <0 255>;
458 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
459 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
460 clock-frequency = <33333333>;
461 interrupt-parent = <&mpic>;
462 interrupts = <16 2>;
463 pcie@0 {
464 reg = <0x0 0x0 0x0 0x0 0x0>;
465 #size-cells = <2>;
466 #address-cells = <3>;
467 device_type = "pci";
468 ranges = <0x2000000 0x0 0xc0000000
469 0x2000000 0x0 0xc0000000
470 0x0 0x20000000
471
472 0x1000000 0x0 0x0
473 0x1000000 0x0 0x0
474 0x0 0x100000>;
475 };
476 };
477};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
new file mode 100644
index 000000000000..0fe93d0c8b2e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -0,0 +1,363 @@
1/*
2 * P2020 RDB Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
7 * eth1, eth2, sdhc, crypto, global-util, pci0.
8 *
9 * Copyright 2009 Freescale Semiconductor Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/dts-v1/;
18/ {
19 model = "fsl,P2020";
20 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {
25 ethernet1 = &enet1;
26 ethernet2 = &enet2;
27 serial0 = &serial0;
28 pci0 = &pci0;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P2020@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 };
45
46 soc@ffe00000 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 device_type = "soc";
50 compatible = "fsl,p2020-immr", "simple-bus";
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 bus-frequency = <0>; // Filled out by uboot.
53
54 ecm-law@0 {
55 compatible = "fsl,ecm-law";
56 reg = <0x0 0x1000>;
57 fsl,num-laws = <12>;
58 };
59
60 ecm@1000 {
61 compatible = "fsl,p2020-ecm", "fsl,ecm";
62 reg = <0x1000 0x1000>;
63 interrupts = <17 2>;
64 interrupt-parent = <&mpic>;
65 };
66
67 memory-controller@2000 {
68 compatible = "fsl,p2020-memory-controller";
69 reg = <0x2000 0x1000>;
70 interrupt-parent = <&mpic>;
71 interrupts = <18 2>;
72 };
73
74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <43 2>;
81 interrupt-parent = <&mpic>;
82 dfsrr;
83 rtc@68 {
84 compatible = "dallas,ds1339";
85 reg = <0x68>;
86 };
87 };
88
89 i2c@3100 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 cell-index = <1>;
93 compatible = "fsl-i2c";
94 reg = <0x3100 0x100>;
95 interrupts = <43 2>;
96 interrupt-parent = <&mpic>;
97 dfsrr;
98 };
99
100 serial0: serial@4500 {
101 cell-index = <0>;
102 device_type = "serial";
103 compatible = "ns16550";
104 reg = <0x4500 0x100>;
105 clock-frequency = <0>;
106 };
107
108 spi@7000 {
109 cell-index = <0>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "fsl,espi";
113 reg = <0x7000 0x1000>;
114 interrupts = <59 0x2>;
115 interrupt-parent = <&mpic>;
116 mode = "cpu";
117
118 fsl_m25p80@0 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,espi-flash";
122 reg = <0>;
123 linux,modalias = "fsl_m25p80";
124 modal = "s25sl128b";
125 spi-max-frequency = <50000000>;
126 mode = <0>;
127
128 partition@0 {
129 /* 512KB for u-boot Bootloader Image */
130 reg = <0x0 0x00080000>;
131 label = "SPI (RO) U-Boot Image";
132 read-only;
133 };
134
135 partition@80000 {
136 /* 512KB for DTB Image */
137 reg = <0x00080000 0x00080000>;
138 label = "SPI (RO) DTB Image";
139 read-only;
140 };
141
142 partition@100000 {
143 /* 4MB for Linux Kernel Image */
144 reg = <0x00100000 0x00400000>;
145 label = "SPI (RO) Linux Kernel Image";
146 read-only;
147 };
148
149 partition@500000 {
150 /* 4MB for Compressed RFS Image */
151 reg = <0x00500000 0x00400000>;
152 label = "SPI (RO) Compressed RFS Image";
153 read-only;
154 };
155
156 partition@900000 {
157 /* 7MB for JFFS2 based RFS */
158 reg = <0x00900000 0x00700000>;
159 label = "SPI (RW) JFFS2 RFS";
160 };
161 };
162 };
163
164 gpio: gpio-controller@f000 {
165 #gpio-cells = <2>;
166 compatible = "fsl,mpc8572-gpio";
167 reg = <0xf000 0x100>;
168 interrupts = <47 0x2>;
169 interrupt-parent = <&mpic>;
170 gpio-controller;
171 };
172
173 L2: l2-cache-controller@20000 {
174 compatible = "fsl,p2020-l2-cache-controller";
175 reg = <0x20000 0x1000>;
176 cache-line-size = <32>; // 32 bytes
177 cache-size = <0x80000>; // L2,512K
178 interrupt-parent = <&mpic>;
179 interrupts = <16 2>;
180 };
181
182 dma@21300 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "fsl,eloplus-dma";
186 reg = <0x21300 0x4>;
187 ranges = <0x0 0x21100 0x200>;
188 cell-index = <0>;
189 dma-channel@0 {
190 compatible = "fsl,eloplus-dma-channel";
191 reg = <0x0 0x80>;
192 cell-index = <0>;
193 interrupt-parent = <&mpic>;
194 interrupts = <20 2>;
195 };
196 dma-channel@80 {
197 compatible = "fsl,eloplus-dma-channel";
198 reg = <0x80 0x80>;
199 cell-index = <1>;
200 interrupt-parent = <&mpic>;
201 interrupts = <21 2>;
202 };
203 dma-channel@100 {
204 compatible = "fsl,eloplus-dma-channel";
205 reg = <0x100 0x80>;
206 cell-index = <2>;
207 interrupt-parent = <&mpic>;
208 interrupts = <22 2>;
209 };
210 dma-channel@180 {
211 compatible = "fsl,eloplus-dma-channel";
212 reg = <0x180 0x80>;
213 cell-index = <3>;
214 interrupt-parent = <&mpic>;
215 interrupts = <23 2>;
216 };
217 };
218
219 usb@22000 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl-usb2-dr";
223 reg = <0x22000 0x1000>;
224 interrupt-parent = <&mpic>;
225 interrupts = <28 0x2>;
226 phy_type = "ulpi";
227 };
228
229 mdio@24520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-mdio";
233 reg = <0x24520 0x20>;
234
235 phy0: ethernet-phy@0 {
236 interrupt-parent = <&mpic>;
237 interrupts = <3 1>;
238 reg = <0x0>;
239 };
240 phy1: ethernet-phy@1 {
241 interrupt-parent = <&mpic>;
242 interrupts = <3 1>;
243 reg = <0x1>;
244 };
245 };
246
247 mdio@25520 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,gianfar-tbi";
251 reg = <0x26520 0x20>;
252
253 tbi0: tbi-phy@11 {
254 reg = <0x11>;
255 device_type = "tbi-phy";
256 };
257 };
258
259 enet1: ethernet@25000 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 cell-index = <1>;
263 device_type = "network";
264 model = "eTSEC";
265 compatible = "gianfar";
266 reg = <0x25000 0x1000>;
267 ranges = <0x0 0x25000 0x1000>;
268 local-mac-address = [ 00 00 00 00 00 00 ];
269 interrupts = <35 2 36 2 40 2>;
270 interrupt-parent = <&mpic>;
271 tbi-handle = <&tbi0>;
272 phy-handle = <&phy0>;
273 phy-connection-type = "sgmii";
274
275 };
276
277 enet2: ethernet@26000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 ranges = <0x0 0x26000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <31 2 32 2 33 2>;
288 interrupt-parent = <&mpic>;
289 phy-handle = <&phy1>;
290 phy-connection-type = "rgmii-id";
291 };
292
293 sdhci@2e000 {
294 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
295 reg = <0x2e000 0x1000>;
296 interrupts = <72 0x2>;
297 interrupt-parent = <&mpic>;
298 /* Filled in by U-Boot */
299 clock-frequency = <0>;
300 };
301
302 crypto@30000 {
303 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
304 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
305 reg = <0x30000 0x10000>;
306 interrupts = <45 2 58 2>;
307 interrupt-parent = <&mpic>;
308 fsl,num-channels = <4>;
309 fsl,channel-fifo-len = <24>;
310 fsl,exec-units-mask = <0xbfe>;
311 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 };
313
314 mpic: pic@40000 {
315 interrupt-controller;
316 #address-cells = <0>;
317 #interrupt-cells = <2>;
318 reg = <0x40000 0x40000>;
319 compatible = "chrp,open-pic";
320 device_type = "open-pic";
321 protected-sources = <
322 42 76 77 78 79 /* serial1 , dma2 */
323 29 30 34 26 /* enet0, pci1 */
324 0xe0 0xe1 0xe2 0xe3 /* msi */
325 0xe4 0xe5 0xe6 0xe7
326 >;
327 };
328
329 global-utilities@e0000 {
330 compatible = "fsl,p2020-guts";
331 reg = <0xe0000 0x1000>;
332 fsl,has-rstcr;
333 };
334 };
335
336 pci0: pcie@ffe09000 {
337 compatible = "fsl,mpc8548-pcie";
338 device_type = "pci";
339 #interrupt-cells = <1>;
340 #size-cells = <2>;
341 #address-cells = <3>;
342 reg = <0 0xffe09000 0 0x1000>;
343 bus-range = <0 255>;
344 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
345 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
346 clock-frequency = <33333333>;
347 interrupt-parent = <&mpic>;
348 interrupts = <25 2>;
349 pcie@0 {
350 reg = <0x0 0x0 0x0 0x0 0x0>;
351 #size-cells = <2>;
352 #address-cells = <3>;
353 device_type = "pci";
354 ranges = <0x2000000 0x0 0xa0000000
355 0x2000000 0x0 0xa0000000
356 0x0 0x20000000
357
358 0x1000000 0x0 0x0
359 0x1000000 0x0 0x0
360 0x0 0x100000>;
361 };
362 };
363};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
new file mode 100644
index 000000000000..e95a51285328
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -0,0 +1,184 @@
1/*
2 * P2020 RDB Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2009 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/dts-v1/;
19/ {
20 model = "fsl,P2020";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 aliases {
26 ethernet0 = &enet0;
27 serial0 = &serial0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P2020@1 {
36 device_type = "cpu";
37 reg = <0x1>;
38 next-level-cache = <&L2>;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 };
45
46 soc@ffe00000 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 device_type = "soc";
50 compatible = "fsl,p2020-immr", "simple-bus";
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 bus-frequency = <0>; // Filled out by uboot.
53
54 serial0: serial@4600 {
55 cell-index = <1>;
56 device_type = "serial";
57 compatible = "ns16550";
58 reg = <0x4600 0x100>;
59 clock-frequency = <0>;
60 };
61
62 dma@c300 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "fsl,eloplus-dma";
66 reg = <0xc300 0x4>;
67 ranges = <0x0 0xc100 0x200>;
68 cell-index = <1>;
69 dma-channel@0 {
70 compatible = "fsl,eloplus-dma-channel";
71 reg = <0x0 0x80>;
72 cell-index = <0>;
73 interrupt-parent = <&mpic>;
74 interrupts = <76 2>;
75 };
76 dma-channel@80 {
77 compatible = "fsl,eloplus-dma-channel";
78 reg = <0x80 0x80>;
79 cell-index = <1>;
80 interrupt-parent = <&mpic>;
81 interrupts = <77 2>;
82 };
83 dma-channel@100 {
84 compatible = "fsl,eloplus-dma-channel";
85 reg = <0x100 0x80>;
86 cell-index = <2>;
87 interrupt-parent = <&mpic>;
88 interrupts = <78 2>;
89 };
90 dma-channel@180 {
91 compatible = "fsl,eloplus-dma-channel";
92 reg = <0x180 0x80>;
93 cell-index = <3>;
94 interrupt-parent = <&mpic>;
95 interrupts = <79 2>;
96 };
97 };
98
99 L2: l2-cache-controller@20000 {
100 compatible = "fsl,p2020-l2-cache-controller";
101 reg = <0x20000 0x1000>;
102 cache-line-size = <32>; // 32 bytes
103 cache-size = <0x80000>; // L2,512K
104 interrupt-parent = <&mpic>;
105 };
106
107
108 enet0: ethernet@24000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 cell-index = <0>;
112 device_type = "network";
113 model = "eTSEC";
114 compatible = "gianfar";
115 reg = <0x24000 0x1000>;
116 ranges = <0x0 0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>;
120 fixed-link = <1 1 1000 0 0>;
121 phy-connection-type = "rgmii-id";
122
123 };
124
125 mpic: pic@40000 {
126 interrupt-controller;
127 #address-cells = <0>;
128 #interrupt-cells = <2>;
129 reg = <0x40000 0x40000>;
130 compatible = "chrp,open-pic";
131 device_type = "open-pic";
132 protected-sources = <
133 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
134 16 20 21 22 23 28 /* L2, dma1, USB */
135 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
136 72 45 58 25 /* sdhci, crypto , pci */
137 >;
138 };
139
140 msi@41600 {
141 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
142 reg = <0x41600 0x80>;
143 msi-available-ranges = <0 0x100>;
144 interrupts = <
145 0xe0 0
146 0xe1 0
147 0xe2 0
148 0xe3 0
149 0xe4 0
150 0xe5 0
151 0xe6 0
152 0xe7 0>;
153 interrupt-parent = <&mpic>;
154 };
155 };
156
157 pci1: pcie@ffe0a000 {
158 compatible = "fsl,mpc8548-pcie";
159 device_type = "pci";
160 #interrupt-cells = <1>;
161 #size-cells = <2>;
162 #address-cells = <3>;
163 reg = <0 0xffe0a000 0 0x1000>;
164 bus-range = <0 255>;
165 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
166 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
167 clock-frequency = <33333333>;
168 interrupt-parent = <&mpic>;
169 interrupts = <26 2>;
170 pcie@0 {
171 reg = <0x0 0x0 0x0 0x0 0x0>;
172 #size-cells = <2>;
173 #address-cells = <3>;
174 device_type = "pci";
175 ranges = <0x2000000 0x0 0xc0000000
176 0x2000000 0x0 0xc0000000
177 0x0 0x20000000
178
179 0x1000000 0x0 0x0
180 0x1000000 0x0 0x0
181 0x0 0x100000>;
182 };
183 };
184};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
new file mode 100644
index 000000000000..6b29eab05362
--- /dev/null
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -0,0 +1,554 @@
1/*
2 * P4080DS Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ccsr = &soc;
22
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 pci2 = &pci2;
30 usb0 = &usb0;
31 usb1 = &usb1;
32 dma0 = &dma0;
33 dma1 = &dma1;
34 sdhc = &sdhc;
35
36 rio0 = &rapidio0;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu0: PowerPC,4080@0 {
44 device_type = "cpu";
45 reg = <0>;
46 next-level-cache = <&L2_0>;
47 L2_0: l2-cache {
48 };
49 };
50 cpu1: PowerPC,4080@1 {
51 device_type = "cpu";
52 reg = <1>;
53 next-level-cache = <&L2_1>;
54 L2_1: l2-cache {
55 };
56 };
57 cpu2: PowerPC,4080@2 {
58 device_type = "cpu";
59 reg = <2>;
60 next-level-cache = <&L2_2>;
61 L2_2: l2-cache {
62 };
63 };
64 cpu3: PowerPC,4080@3 {
65 device_type = "cpu";
66 reg = <3>;
67 next-level-cache = <&L2_3>;
68 L2_3: l2-cache {
69 };
70 };
71 cpu4: PowerPC,4080@4 {
72 device_type = "cpu";
73 reg = <4>;
74 next-level-cache = <&L2_4>;
75 L2_4: l2-cache {
76 };
77 };
78 cpu5: PowerPC,4080@5 {
79 device_type = "cpu";
80 reg = <5>;
81 next-level-cache = <&L2_5>;
82 L2_5: l2-cache {
83 };
84 };
85 cpu6: PowerPC,4080@6 {
86 device_type = "cpu";
87 reg = <6>;
88 next-level-cache = <&L2_6>;
89 L2_6: l2-cache {
90 };
91 };
92 cpu7: PowerPC,4080@7 {
93 device_type = "cpu";
94 reg = <7>;
95 next-level-cache = <&L2_7>;
96 L2_7: l2-cache {
97 };
98 };
99 };
100
101 memory {
102 device_type = "memory";
103 };
104
105 soc: soc@ffe000000 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 device_type = "soc";
109 compatible = "simple-bus";
110 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
111 reg = <0xf 0xfe000000 0 0x00001000>;
112
113 corenet-law@0 {
114 compatible = "fsl,corenet-law";
115 reg = <0x0 0x1000>;
116 fsl,num-laws = <32>;
117 };
118
119 memory-controller@8000 {
120 compatible = "fsl,p4080-memory-controller";
121 reg = <0x8000 0x1000>;
122 interrupt-parent = <&mpic>;
123 interrupts = <0x12 2>;
124 };
125
126 memory-controller@9000 {
127 compatible = "fsl,p4080-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupt-parent = <&mpic>;
130 interrupts = <0x12 2>;
131 };
132
133 corenet-cf@18000 {
134 compatible = "fsl,corenet-cf";
135 reg = <0x18000 0x1000>;
136 fsl,ccf-num-csdids = <32>;
137 fsl,ccf-num-snoopids = <32>;
138 };
139
140 iommu@20000 {
141 compatible = "fsl,p4080-pamu";
142 reg = <0x20000 0x10000>;
143 interrupts = <24 2>;
144 interrupt-parent = <&mpic>;
145 };
146
147 mpic: pic@40000 {
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0x40000 0x40000>;
152 compatible = "chrp,open-pic";
153 device_type = "open-pic";
154 };
155
156 dma0: dma@100300 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
160 reg = <0x100300 0x4>;
161 ranges = <0x0 0x100100 0x200>;
162 cell-index = <0>;
163 dma-channel@0 {
164 compatible = "fsl,p4080-dma-channel",
165 "fsl,eloplus-dma-channel";
166 reg = <0x0 0x80>;
167 cell-index = <0>;
168 interrupt-parent = <&mpic>;
169 interrupts = <28 2>;
170 };
171 dma-channel@80 {
172 compatible = "fsl,p4080-dma-channel",
173 "fsl,eloplus-dma-channel";
174 reg = <0x80 0x80>;
175 cell-index = <1>;
176 interrupt-parent = <&mpic>;
177 interrupts = <29 2>;
178 };
179 dma-channel@100 {
180 compatible = "fsl,p4080-dma-channel",
181 "fsl,eloplus-dma-channel";
182 reg = <0x100 0x80>;
183 cell-index = <2>;
184 interrupt-parent = <&mpic>;
185 interrupts = <30 2>;
186 };
187 dma-channel@180 {
188 compatible = "fsl,p4080-dma-channel",
189 "fsl,eloplus-dma-channel";
190 reg = <0x180 0x80>;
191 cell-index = <3>;
192 interrupt-parent = <&mpic>;
193 interrupts = <31 2>;
194 };
195 };
196
197 dma1: dma@101300 {
198 #address-cells = <1>;
199 #size-cells = <1>;
200 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
201 reg = <0x101300 0x4>;
202 ranges = <0x0 0x101100 0x200>;
203 cell-index = <1>;
204 dma-channel@0 {
205 compatible = "fsl,p4080-dma-channel",
206 "fsl,eloplus-dma-channel";
207 reg = <0x0 0x80>;
208 cell-index = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <32 2>;
211 };
212 dma-channel@80 {
213 compatible = "fsl,p4080-dma-channel",
214 "fsl,eloplus-dma-channel";
215 reg = <0x80 0x80>;
216 cell-index = <1>;
217 interrupt-parent = <&mpic>;
218 interrupts = <33 2>;
219 };
220 dma-channel@100 {
221 compatible = "fsl,p4080-dma-channel",
222 "fsl,eloplus-dma-channel";
223 reg = <0x100 0x80>;
224 cell-index = <2>;
225 interrupt-parent = <&mpic>;
226 interrupts = <34 2>;
227 };
228 dma-channel@180 {
229 compatible = "fsl,p4080-dma-channel",
230 "fsl,eloplus-dma-channel";
231 reg = <0x180 0x80>;
232 cell-index = <3>;
233 interrupt-parent = <&mpic>;
234 interrupts = <35 2>;
235 };
236 };
237
238 spi@110000 {
239 cell-index = <0>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,espi";
243 reg = <0x110000 0x1000>;
244 interrupts = <53 0x2>;
245 interrupt-parent = <&mpic>;
246 espi,num-ss-bits = <4>;
247 mode = "cpu";
248
249 fsl_m25p80@0 {
250 #address-cells = <1>;
251 #size-cells = <1>;
252 compatible = "fsl,espi-flash";
253 reg = <0>;
254 linux,modalias = "fsl_m25p80";
255 spi-max-frequency = <40000000>; /* input clock */
256 partition@u-boot {
257 label = "u-boot";
258 reg = <0x00000000 0x00100000>;
259 read-only;
260 };
261 partition@kernel {
262 label = "kernel";
263 reg = <0x00100000 0x00500000>;
264 read-only;
265 };
266 partition@dtb {
267 label = "dtb";
268 reg = <0x00600000 0x00100000>;
269 read-only;
270 };
271 partition@fs {
272 label = "file system";
273 reg = <0x00700000 0x00900000>;
274 };
275 };
276 };
277
278 sdhc: sdhc@114000 {
279 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
280 reg = <0x114000 0x1000>;
281 interrupts = <48 2>;
282 interrupt-parent = <&mpic>;
283 };
284
285 i2c@118000 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 cell-index = <0>;
289 compatible = "fsl-i2c";
290 reg = <0x118000 0x100>;
291 interrupts = <38 2>;
292 interrupt-parent = <&mpic>;
293 dfsrr;
294 };
295
296 i2c@118100 {
297 #address-cells = <1>;
298 #size-cells = <0>;
299 cell-index = <1>;
300 compatible = "fsl-i2c";
301 reg = <0x118100 0x100>;
302 interrupts = <38 2>;
303 interrupt-parent = <&mpic>;
304 dfsrr;
305 eeprom@51 {
306 compatible = "at24,24c256";
307 reg = <0x51>;
308 };
309 eeprom@52 {
310 compatible = "at24,24c256";
311 reg = <0x52>;
312 };
313 rtc@68 {
314 compatible = "dallas,ds3232";
315 reg = <0x68>;
316 interrupts = <0 0x1>;
317 interrupt-parent = <&mpic>;
318 };
319 };
320
321 i2c@119000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 cell-index = <2>;
325 compatible = "fsl-i2c";
326 reg = <0x119000 0x100>;
327 interrupts = <39 2>;
328 interrupt-parent = <&mpic>;
329 dfsrr;
330 };
331
332 i2c@119100 {
333 #address-cells = <1>;
334 #size-cells = <0>;
335 cell-index = <3>;
336 compatible = "fsl-i2c";
337 reg = <0x119100 0x100>;
338 interrupts = <39 2>;
339 interrupt-parent = <&mpic>;
340 dfsrr;
341 };
342
343 serial0: serial@11c500 {
344 cell-index = <0>;
345 device_type = "serial";
346 compatible = "ns16550";
347 reg = <0x11c500 0x100>;
348 clock-frequency = <0>;
349 interrupts = <36 2>;
350 interrupt-parent = <&mpic>;
351 };
352
353 serial1: serial@11c600 {
354 cell-index = <1>;
355 device_type = "serial";
356 compatible = "ns16550";
357 reg = <0x11c600 0x100>;
358 clock-frequency = <0>;
359 interrupts = <36 2>;
360 interrupt-parent = <&mpic>;
361 };
362
363 serial2: serial@11d500 {
364 cell-index = <2>;
365 device_type = "serial";
366 compatible = "ns16550";
367 reg = <0x11d500 0x100>;
368 clock-frequency = <0>;
369 interrupts = <37 2>;
370 interrupt-parent = <&mpic>;
371 };
372
373 serial3: serial@11d600 {
374 cell-index = <3>;
375 device_type = "serial";
376 compatible = "ns16550";
377 reg = <0x11d600 0x100>;
378 clock-frequency = <0>;
379 interrupts = <37 2>;
380 interrupt-parent = <&mpic>;
381 };
382
383 gpio0: gpio@130000 {
384 compatible = "fsl,p4080-gpio";
385 reg = <0x130000 0x1000>;
386 interrupts = <55 2>;
387 interrupt-parent = <&mpic>;
388 #gpio-cells = <2>;
389 gpio-controller;
390 };
391
392 usb0: usb@210000 {
393 compatible = "fsl,p4080-usb2-mph",
394 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
395 reg = <0x210000 0x1000>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 interrupt-parent = <&mpic>;
399 interrupts = <44 0x2>;
400 phy_type = "ulpi";
401 };
402
403 usb1: usb@211000 {
404 compatible = "fsl,p4080-usb2-dr",
405 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
406 reg = <0x211000 0x1000>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 interrupt-parent = <&mpic>;
410 interrupts = <45 0x2>;
411 dr_mode = "host";
412 phy_type = "ulpi";
413 };
414 };
415
416 rapidio0: rapidio@ffe0c0000 {
417 #address-cells = <2>;
418 #size-cells = <2>;
419 compatible = "fsl,rapidio-delta";
420 reg = <0xf 0xfe0c0000 0 0x20000>;
421 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
422 interrupt-parent = <&mpic>;
423 /* err_irq bell_outb_irq bell_inb_irq
424 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
425 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
426 };
427
428 localbus@ffe124000 {
429 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
430 reg = <0xf 0xfe124000 0 0x1000>;
431 interrupts = <25 2>;
432 #address-cells = <2>;
433 #size-cells = <1>;
434
435 ranges = <0 0 0xf 0xe8000000 0x08000000>;
436
437 flash@0,0 {
438 compatible = "cfi-flash";
439 reg = <0 0 0x08000000>;
440 bank-width = <2>;
441 device-width = <2>;
442 };
443 };
444
445 pci0: pcie@ffe200000 {
446 compatible = "fsl,p4080-pcie";
447 device_type = "pci";
448 #interrupt-cells = <1>;
449 #size-cells = <2>;
450 #address-cells = <3>;
451 reg = <0xf 0xfe200000 0 0x1000>;
452 bus-range = <0x0 0xff>;
453 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
454 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
455 clock-frequency = <0x1fca055>;
456 interrupt-parent = <&mpic>;
457 interrupts = <16 2>;
458
459 interrupt-map-mask = <0xf800 0 0 7>;
460 interrupt-map = <
461 /* IDSEL 0x0 */
462 0000 0 0 1 &mpic 40 1
463 0000 0 0 2 &mpic 1 1
464 0000 0 0 3 &mpic 2 1
465 0000 0 0 4 &mpic 3 1
466 >;
467 pcie@0 {
468 reg = <0 0 0 0 0>;
469 #size-cells = <2>;
470 #address-cells = <3>;
471 device_type = "pci";
472 ranges = <0x02000000 0 0xe0000000
473 0x02000000 0 0xe0000000
474 0 0x20000000
475
476 0x01000000 0 0x00000000
477 0x01000000 0 0x00000000
478 0 0x00010000>;
479 };
480 };
481
482 pci1: pcie@ffe201000 {
483 compatible = "fsl,p4080-pcie";
484 device_type = "pci";
485 #interrupt-cells = <1>;
486 #size-cells = <2>;
487 #address-cells = <3>;
488 reg = <0xf 0xfe201000 0 0x1000>;
489 bus-range = <0 0xff>;
490 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
491 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
492 clock-frequency = <0x1fca055>;
493 interrupt-parent = <&mpic>;
494 interrupts = <16 2>;
495 interrupt-map-mask = <0xf800 0 0 7>;
496 interrupt-map = <
497 /* IDSEL 0x0 */
498 0000 0 0 1 &mpic 41 1
499 0000 0 0 2 &mpic 5 1
500 0000 0 0 3 &mpic 6 1
501 0000 0 0 4 &mpic 7 1
502 >;
503 pcie@0 {
504 reg = <0 0 0 0 0>;
505 #size-cells = <2>;
506 #address-cells = <3>;
507 device_type = "pci";
508 ranges = <0x02000000 0 0xe0000000
509 0x02000000 0 0xe0000000
510 0 0x20000000
511
512 0x01000000 0 0x00000000
513 0x01000000 0 0x00000000
514 0 0x00010000>;
515 };
516 };
517
518 pci2: pcie@ffe202000 {
519 compatible = "fsl,p4080-pcie";
520 device_type = "pci";
521 #interrupt-cells = <1>;
522 #size-cells = <2>;
523 #address-cells = <3>;
524 reg = <0xf 0xfe202000 0 0x1000>;
525 bus-range = <0x0 0xff>;
526 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
527 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
528 clock-frequency = <0x1fca055>;
529 interrupt-parent = <&mpic>;
530 interrupts = <16 2>;
531 interrupt-map-mask = <0xf800 0 0 7>;
532 interrupt-map = <
533 /* IDSEL 0x0 */
534 0000 0 0 1 &mpic 42 1
535 0000 0 0 2 &mpic 9 1
536 0000 0 0 3 &mpic 10 1
537 0000 0 0 4 &mpic 11 1
538 >;
539 pcie@0 {
540 reg = <0 0 0 0 0>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 device_type = "pci";
544 ranges = <0x02000000 0 0xe0000000
545 0x02000000 0 0xe0000000
546 0 0x20000000
547
548 0x01000000 0 0x00000000
549 0x01000000 0 0x00000000
550 0 0x00010000>;
551 };
552 };
553
554};
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
index ad402c488741..d2af32e2bf7a 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -226,6 +226,7 @@
226 max-frame-size = <9000>; 226 max-frame-size = <9000>;
227 rx-fifo-size = <4096>; 227 rx-fifo-size = <4096>;
228 tx-fifo-size = <2048>; 228 tx-fifo-size = <2048>;
229 rx-fifo-size-gige = <16384>;
229 phy-mode = "rgmii"; 230 phy-mode = "rgmii";
230 phy-map = <0x00000000>; 231 phy-map = <0x00000000>;
231 rgmii-device = <&RGMII0>; 232 rgmii-device = <&RGMII0>;
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index 31605ee4afb6..e576ee85c42f 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -146,7 +146,7 @@
146 146
147 fpga@2,4000 { 147 fpga@2,4000 {
148 compatible = "pika,fpga-sd"; 148 compatible = "pika,fpga-sd";
149 reg = <0x00000002 0x00004000 0x00000A00>; 149 reg = <0x00000002 0x00004000 0x00004000>;
150 }; 150 };
151 151
152 nor@0,0 { 152 nor@0,0 {
diff --git a/arch/powerpc/boot/dts/wii.dts b/arch/powerpc/boot/dts/wii.dts
new file mode 100644
index 000000000000..77528c9a8dbd
--- /dev/null
+++ b/arch/powerpc/boot/dts/wii.dts
@@ -0,0 +1,218 @@
1/*
2 * arch/powerpc/boot/dts/wii.dts
3 *
4 * Nintendo Wii platform device tree source
5 * Copyright (C) 2008-2009 The GameCube Linux Team
6 * Copyright (C) 2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15/dts-v1/;
16
17/*
18 * This is commented-out for now.
19 * Until a later patch is merged, the kernel can use only the first
20 * contiguous RAM range and will BUG() if the memreserve is outside
21 * that range.
22 */
23/*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
24
25/ {
26 model = "nintendo,wii";
27 compatible = "nintendo,wii";
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 chosen {
32 bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal";
33 };
34
35 memory {
36 device_type = "memory";
37 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
38 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 PowerPC,broadway@0 {
46 device_type = "cpu";
47 reg = <0>;
48 clock-frequency = <729000000>; /* 729MHz */
49 bus-frequency = <243000000>; /* 243MHz core-to-bus 3x */
50 timebase-frequency = <60750000>; /* 243MHz / 4 */
51 i-cache-line-size = <32>;
52 d-cache-line-size = <32>;
53 i-cache-size = <32768>;
54 d-cache-size = <32768>;
55 };
56 };
57
58 /* devices contained in the hollywood chipset */
59 hollywood {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "nintendo,hollywood";
63 ranges = <0x0c000000 0x0c000000 0x01000000
64 0x0d000000 0x0d000000 0x00800000
65 0x0d800000 0x0d800000 0x00800000>;
66 interrupt-parent = <&PIC0>;
67
68 video@0c002000 {
69 compatible = "nintendo,hollywood-vi",
70 "nintendo,flipper-vi";
71 reg = <0x0c002000 0x100>;
72 interrupts = <8>;
73 };
74
75 processor-interface@0c003000 {
76 compatible = "nintendo,hollywood-pi",
77 "nintendo,flipper-pi";
78 reg = <0x0c003000 0x100>;
79
80 PIC0: pic0 {
81 #interrupt-cells = <1>;
82 compatible = "nintendo,flipper-pic";
83 interrupt-controller;
84 };
85 };
86
87 dsp@0c005000 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "nintendo,hollywood-dsp",
91 "nintendo,flipper-dsp";
92 reg = <0x0c005000 0x200>;
93 interrupts = <6>;
94 };
95
96 gamepad-controller@0d006400 {
97 compatible = "nintendo,hollywood-si",
98 "nintendo,flipper-si";
99 reg = <0x0d006400 0x100>;
100 interrupts = <3>;
101 };
102
103 audio@0c006c00 {
104 compatible = "nintendo,hollywood-ai",
105 "nintendo,flipper-ai";
106 reg = <0x0d006c00 0x20>;
107 interrupts = <6>;
108 };
109
110 /* External Interface bus */
111 exi@0d006800 {
112 compatible = "nintendo,hollywood-exi",
113 "nintendo,flipper-exi";
114 reg = <0x0d006800 0x40>;
115 virtual-reg = <0x0d006800>;
116 interrupts = <4>;
117 };
118
119 usb@0d040000 {
120 compatible = "nintendo,hollywood-usb-ehci",
121 "usb-ehci";
122 reg = <0x0d040000 0x100>;
123 interrupts = <4>;
124 interrupt-parent = <&PIC1>;
125 };
126
127 usb@0d050000 {
128 compatible = "nintendo,hollywood-usb-ohci",
129 "usb-ohci";
130 reg = <0x0d050000 0x100>;
131 interrupts = <5>;
132 interrupt-parent = <&PIC1>;
133 };
134
135 usb@0d060000 {
136 compatible = "nintendo,hollywood-usb-ohci",
137 "usb-ohci";
138 reg = <0x0d060000 0x100>;
139 interrupts = <6>;
140 interrupt-parent = <&PIC1>;
141 };
142
143 sd@0d070000 {
144 compatible = "nintendo,hollywood-sdhci",
145 "sdhci";
146 reg = <0x0d070000 0x200>;
147 interrupts = <7>;
148 interrupt-parent = <&PIC1>;
149 };
150
151 sdio@0d080000 {
152 compatible = "nintendo,hollywood-sdhci",
153 "sdhci";
154 reg = <0x0d080000 0x200>;
155 interrupts = <8>;
156 interrupt-parent = <&PIC1>;
157 };
158
159 ipc@0d000000 {
160 compatible = "nintendo,hollywood-ipc";
161 reg = <0x0d000000 0x10>;
162 interrupts = <30>;
163 interrupt-parent = <&PIC1>;
164 };
165
166 PIC1: pic1@0d800030 {
167 #interrupt-cells = <1>;
168 compatible = "nintendo,hollywood-pic";
169 reg = <0x0d800030 0x10>;
170 interrupt-controller;
171 interrupts = <14>;
172 };
173
174 GPIO: gpio@0d8000c0 {
175 #gpio-cells = <2>;
176 compatible = "nintendo,hollywood-gpio";
177 reg = <0x0d8000c0 0x40>;
178 gpio-controller;
179
180 /*
181 * This is commented out while a standard binding
182 * for i2c over gpio is defined.
183 */
184 /*
185 i2c-video {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "i2c-gpio";
189
190 gpios = <&GPIO 15 0
191 &GPIO 14 0>;
192 clock-frequency = <250000>;
193 no-clock-stretching;
194 scl-is-open-drain;
195 sda-is-open-drain;
196 sda-enforce-dir;
197
198 AVE: audio-video-encoder@70 {
199 compatible = "nintendo,wii-audio-video-encoder";
200 reg = <0x70>;
201 };
202 };
203 */
204 };
205
206 control@0d800100 {
207 compatible = "nintendo,hollywood-control";
208 reg = <0x0d800100 0x300>;
209 };
210
211 disk@0d806000 {
212 compatible = "nintendo,hollywood-di";
213 reg = <0x0d806000 0x40>;
214 interrupts = <2>;
215 };
216 };
217};
218
diff --git a/arch/powerpc/boot/dts/yosemite.dts b/arch/powerpc/boot/dts/yosemite.dts
index 1fa3cb4c4ebb..64923245f0e5 100644
--- a/arch/powerpc/boot/dts/yosemite.dts
+++ b/arch/powerpc/boot/dts/yosemite.dts
@@ -282,20 +282,10 @@
282 /* Inbound 2GB range starting at 0 */ 282 /* Inbound 2GB range starting at 0 */
283 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 283 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
284 284
285 /* Bamboo has all 4 IRQ pins tied together per slot */
286 interrupt-map-mask = <0xf800 0x0 0x0 0x0>; 285 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
287 interrupt-map = < 286 interrupt-map = <
288 /* IDSEL 1 */ 287 /* IDSEL 12 */
289 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 288 0x6000 0x0 0x0 0x0 &UIC0 0x19 0x8
290
291 /* IDSEL 2 */
292 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
293
294 /* IDSEL 3 */
295 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
296
297 /* IDSEL 4 */
298 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
299 >; 289 >;
300 }; 290 };
301 }; 291 };
diff --git a/arch/powerpc/boot/gamecube-head.S b/arch/powerpc/boot/gamecube-head.S
new file mode 100644
index 000000000000..65a9b2a3bf33
--- /dev/null
+++ b/arch/powerpc/boot/gamecube-head.S
@@ -0,0 +1,111 @@
1/*
2 * arch/powerpc/boot/gamecube-head.S
3 *
4 * Nintendo GameCube bootwrapper entry.
5 * Copyright (C) 2004-2009 The GameCube Linux Team
6 * Copyright (C) 2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15#include "ppc_asm.h"
16
17/*
18 * The entry code does no assumptions regarding:
19 * - if the data and instruction caches are enabled or not
20 * - if the MMU is enabled or not
21 *
22 * We enable the caches if not already enabled, enable the MMU with an
23 * identity mapping scheme and jump to the start code.
24 */
25
26 .text
27
28 .globl _zimage_start
29_zimage_start:
30
31 /* turn the MMU off */
32 mfmsr 9
33 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
34 bcl 20, 31, 1f
351:
36 mflr 8
37 clrlwi 8, 8, 3 /* convert to a real address */
38 addi 8, 8, _mmu_off - 1b
39 mtsrr0 8
40 mtsrr1 9
41 rfi
42_mmu_off:
43 /* MMU disabled */
44
45 /* setup BATs */
46 isync
47 li 8, 0
48 mtspr 0x210, 8 /* IBAT0U */
49 mtspr 0x212, 8 /* IBAT1U */
50 mtspr 0x214, 8 /* IBAT2U */
51 mtspr 0x216, 8 /* IBAT3U */
52 mtspr 0x218, 8 /* DBAT0U */
53 mtspr 0x21a, 8 /* DBAT1U */
54 mtspr 0x21c, 8 /* DBAT2U */
55 mtspr 0x21e, 8 /* DBAT3U */
56
57 li 8, 0x01ff /* first 16MiB */
58 li 9, 0x0002 /* rw */
59 mtspr 0x211, 9 /* IBAT0L */
60 mtspr 0x210, 8 /* IBAT0U */
61 mtspr 0x219, 9 /* DBAT0L */
62 mtspr 0x218, 8 /* DBAT0U */
63
64 lis 8, 0x0c00 /* I/O mem */
65 ori 8, 8, 0x3ff /* 32MiB */
66 lis 9, 0x0c00
67 ori 9, 9, 0x002a /* uncached, guarded, rw */
68 mtspr 0x21b, 9 /* DBAT1L */
69 mtspr 0x21a, 8 /* DBAT1U */
70
71 lis 8, 0x0100 /* next 8MiB */
72 ori 8, 8, 0x00ff /* 8MiB */
73 lis 9, 0x0100
74 ori 9, 9, 0x0002 /* rw */
75 mtspr 0x215, 9 /* IBAT2L */
76 mtspr 0x214, 8 /* IBAT2U */
77 mtspr 0x21d, 9 /* DBAT2L */
78 mtspr 0x21c, 8 /* DBAT2U */
79
80 /* enable and invalidate the caches if not already enabled */
81 mfspr 8, 0x3f0 /* HID0 */
82 andi. 0, 8, (1<<15) /* HID0_ICE */
83 bne 1f
84 ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/
851:
86 andi. 0, 8, (1<<14) /* HID0_DCE */
87 bne 1f
88 ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/
891:
90 mtspr 0x3f0, 8 /* HID0 */
91 isync
92
93 /* initialize arguments */
94 li 3, 0
95 li 4, 0
96 li 5, 0
97
98 /* turn the MMU on */
99 bcl 20, 31, 1f
1001:
101 mflr 8
102 addi 8, 8, _mmu_on - 1b
103 mfmsr 9
104 ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
105 mtsrr0 8
106 mtsrr1 9
107 sync
108 rfi
109_mmu_on:
110 b _zimage_start_lib
111
diff --git a/arch/powerpc/boot/gamecube.c b/arch/powerpc/boot/gamecube.c
new file mode 100644
index 000000000000..28ae7057be5e
--- /dev/null
+++ b/arch/powerpc/boot/gamecube.c
@@ -0,0 +1,35 @@
1/*
2 * arch/powerpc/boot/gamecube.c
3 *
4 * Nintendo GameCube bootwrapper support
5 * Copyright (C) 2004-2009 The GameCube Linux Team
6 * Copyright (C) 2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15#include <stddef.h>
16#include "stdio.h"
17#include "types.h"
18#include "io.h"
19#include "ops.h"
20
21#include "ugecon.h"
22
23BSS_STACK(8192);
24
25void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
26{
27 u32 heapsize = 16*1024*1024 - (u32)_end;
28
29 simple_alloc_init(_end, heapsize, 32, 64);
30 fdt_init(_dtb_start);
31
32 if (ug_probe())
33 console_ops.write = ug_console_write;
34}
35
diff --git a/arch/powerpc/boot/ugecon.c b/arch/powerpc/boot/ugecon.c
new file mode 100644
index 000000000000..8f2a6b311534
--- /dev/null
+++ b/arch/powerpc/boot/ugecon.c
@@ -0,0 +1,147 @@
1/*
2 * arch/powerpc/boot/ugecon.c
3 *
4 * USB Gecko bootwrapper console.
5 * Copyright (C) 2008-2009 The GameCube Linux Team
6 * Copyright (C) 2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15#include <stddef.h>
16#include "stdio.h"
17#include "types.h"
18#include "io.h"
19#include "ops.h"
20
21
22#define EXI_CLK_32MHZ 5
23
24#define EXI_CSR 0x00
25#define EXI_CSR_CLKMASK (0x7<<4)
26#define EXI_CSR_CLK_32MHZ (EXI_CLK_32MHZ<<4)
27#define EXI_CSR_CSMASK (0x7<<7)
28#define EXI_CSR_CS_0 (0x1<<7) /* Chip Select 001 */
29
30#define EXI_CR 0x0c
31#define EXI_CR_TSTART (1<<0)
32#define EXI_CR_WRITE (1<<2)
33#define EXI_CR_READ_WRITE (2<<2)
34#define EXI_CR_TLEN(len) (((len)-1)<<4)
35
36#define EXI_DATA 0x10
37
38
39/* virtual address base for input/output, retrieved from device tree */
40static void *ug_io_base;
41
42
43static u32 ug_io_transaction(u32 in)
44{
45 u32 *csr_reg = ug_io_base + EXI_CSR;
46 u32 *data_reg = ug_io_base + EXI_DATA;
47 u32 *cr_reg = ug_io_base + EXI_CR;
48 u32 csr, data, cr;
49
50 /* select */
51 csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0;
52 out_be32(csr_reg, csr);
53
54 /* read/write */
55 data = in;
56 out_be32(data_reg, data);
57 cr = EXI_CR_TLEN(2) | EXI_CR_READ_WRITE | EXI_CR_TSTART;
58 out_be32(cr_reg, cr);
59
60 while (in_be32(cr_reg) & EXI_CR_TSTART)
61 barrier();
62
63 /* deselect */
64 out_be32(csr_reg, 0);
65
66 data = in_be32(data_reg);
67 return data;
68}
69
70static int ug_is_txfifo_ready(void)
71{
72 return ug_io_transaction(0xc0000000) & 0x04000000;
73}
74
75static void ug_raw_putc(char ch)
76{
77 ug_io_transaction(0xb0000000 | (ch << 20));
78}
79
80static void ug_putc(char ch)
81{
82 int count = 16;
83
84 if (!ug_io_base)
85 return;
86
87 while (!ug_is_txfifo_ready() && count--)
88 barrier();
89 if (count >= 0)
90 ug_raw_putc(ch);
91}
92
93void ug_console_write(const char *buf, int len)
94{
95 char *b = (char *)buf;
96
97 while (len--) {
98 if (*b == '\n')
99 ug_putc('\r');
100 ug_putc(*b++);
101 }
102}
103
104static int ug_is_adapter_present(void)
105{
106 if (!ug_io_base)
107 return 0;
108 return ug_io_transaction(0x90000000) == 0x04700000;
109}
110
111static void *ug_grab_exi_io_base(void)
112{
113 u32 v;
114 void *devp;
115
116 devp = find_node_by_compatible(NULL, "nintendo,flipper-exi");
117 if (devp == NULL)
118 goto err_out;
119 if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
120 goto err_out;
121
122 return (void *)v;
123
124err_out:
125 return NULL;
126}
127
128void *ug_probe(void)
129{
130 void *exi_io_base;
131 int i;
132
133 exi_io_base = ug_grab_exi_io_base();
134 if (!exi_io_base)
135 return NULL;
136
137 /* look for a usbgecko on memcard slots A and B */
138 for (i = 0; i < 2; i++) {
139 ug_io_base = exi_io_base + 0x14 * i;
140 if (ug_is_adapter_present())
141 break;
142 }
143 if (i == 2)
144 ug_io_base = NULL;
145 return ug_io_base;
146}
147
diff --git a/arch/powerpc/boot/ugecon.h b/arch/powerpc/boot/ugecon.h
new file mode 100644
index 000000000000..43737539169b
--- /dev/null
+++ b/arch/powerpc/boot/ugecon.h
@@ -0,0 +1,24 @@
1/*
2 * arch/powerpc/boot/ugecon.h
3 *
4 * USB Gecko early bootwrapper console.
5 * Copyright (C) 2008-2009 The GameCube Linux Team
6 * Copyright (C) 2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15#ifndef __UGECON_H
16#define __UGECON_H
17
18extern void *ug_probe(void);
19
20extern void ug_putc(char ch);
21extern void ug_console_write(const char *buf, int len);
22
23#endif /* __UGECON_H */
24
diff --git a/arch/powerpc/boot/wii-head.S b/arch/powerpc/boot/wii-head.S
new file mode 100644
index 000000000000..edd79b836fcf
--- /dev/null
+++ b/arch/powerpc/boot/wii-head.S
@@ -0,0 +1,142 @@
1/*
2 * arch/powerpc/boot/wii-head.S
3 *
4 * Nintendo Wii bootwrapper entry.
5 * Copyright (C) 2008-2009 The GameCube Linux Team
6 * Copyright (C) 2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15#include "ppc_asm.h"
16
17/*
18 * The entry code does no assumptions regarding:
19 * - if the data and instruction caches are enabled or not
20 * - if the MMU is enabled or not
21 * - if the high BATs are enabled or not
22 *
23 * We enable the high BATs, enable the caches if not already enabled,
24 * enable the MMU with an identity mapping scheme and jump to the start code.
25 */
26
27 .text
28
29 .globl _zimage_start
30_zimage_start:
31
32 /* turn the MMU off */
33 mfmsr 9
34 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
35 bcl 20, 31, 1f
361:
37 mflr 8
38 clrlwi 8, 8, 3 /* convert to a real address */
39 addi 8, 8, _mmu_off - 1b
40 mtsrr0 8
41 mtsrr1 9
42 rfi
43_mmu_off:
44 /* MMU disabled */
45
46 /* setup BATs */
47 isync
48 li 8, 0
49 mtspr 0x210, 8 /* IBAT0U */
50 mtspr 0x212, 8 /* IBAT1U */
51 mtspr 0x214, 8 /* IBAT2U */
52 mtspr 0x216, 8 /* IBAT3U */
53 mtspr 0x218, 8 /* DBAT0U */
54 mtspr 0x21a, 8 /* DBAT1U */
55 mtspr 0x21c, 8 /* DBAT2U */
56 mtspr 0x21e, 8 /* DBAT3U */
57
58 mtspr 0x230, 8 /* IBAT4U */
59 mtspr 0x232, 8 /* IBAT5U */
60 mtspr 0x234, 8 /* IBAT6U */
61 mtspr 0x236, 8 /* IBAT7U */
62 mtspr 0x238, 8 /* DBAT4U */
63 mtspr 0x23a, 8 /* DBAT5U */
64 mtspr 0x23c, 8 /* DBAT6U */
65 mtspr 0x23e, 8 /* DBAT7U */
66
67 li 8, 0x01ff /* first 16MiB */
68 li 9, 0x0002 /* rw */
69 mtspr 0x211, 9 /* IBAT0L */
70 mtspr 0x210, 8 /* IBAT0U */
71 mtspr 0x219, 9 /* DBAT0L */
72 mtspr 0x218, 8 /* DBAT0U */
73
74 lis 8, 0x0c00 /* I/O mem */
75 ori 8, 8, 0x3ff /* 32MiB */
76 lis 9, 0x0c00
77 ori 9, 9, 0x002a /* uncached, guarded, rw */
78 mtspr 0x21b, 9 /* DBAT1L */
79 mtspr 0x21a, 8 /* DBAT1U */
80
81 lis 8, 0x0100 /* next 8MiB */
82 ori 8, 8, 0x00ff /* 8MiB */
83 lis 9, 0x0100
84 ori 9, 9, 0x0002 /* rw */
85 mtspr 0x215, 9 /* IBAT2L */
86 mtspr 0x214, 8 /* IBAT2U */
87 mtspr 0x21d, 9 /* DBAT2L */
88 mtspr 0x21c, 8 /* DBAT2U */
89
90 lis 8, 0x1000 /* MEM2 */
91 ori 8, 8, 0x07ff /* 64MiB */
92 lis 9, 0x1000
93 ori 9, 9, 0x0002 /* rw */
94 mtspr 0x216, 8 /* IBAT3U */
95 mtspr 0x217, 9 /* IBAT3L */
96 mtspr 0x21e, 8 /* DBAT3U */
97 mtspr 0x21f, 9 /* DBAT3L */
98
99 /* enable the high BATs */
100 mfspr 8, 0x3f3 /* HID4 */
101 oris 8, 8, 0x0200
102 mtspr 0x3f3, 8 /* HID4 */
103
104 /* enable and invalidate the caches if not already enabled */
105 mfspr 8, 0x3f0 /* HID0 */
106 andi. 0, 8, (1<<15) /* HID0_ICE */
107 bne 1f
108 ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/
1091:
110 andi. 0, 8, (1<<14) /* HID0_DCE */
111 bne 1f
112 ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/
1131:
114 mtspr 0x3f0, 8 /* HID0 */
115 isync
116
117 /* initialize arguments */
118 li 3, 0
119 li 4, 0
120 li 5, 0
121
122 /* turn the MMU on */
123 bcl 20, 31, 1f
1241:
125 mflr 8
126 addi 8, 8, _mmu_on - 1b
127 mfmsr 9
128 ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
129 mtsrr0 8
130 mtsrr1 9
131 sync
132 rfi
133_mmu_on:
134 /* turn on the front blue led (aka: yay! we got here!) */
135 lis 8, 0x0d00
136 ori 8, 8, 0x00c0
137 lwz 9, 0(8)
138 ori 9, 9, 0x20
139 stw 9, 0(8)
140
141 b _zimage_start_lib
142
diff --git a/arch/powerpc/boot/wii.c b/arch/powerpc/boot/wii.c
new file mode 100644
index 000000000000..2ebaec0344dd
--- /dev/null
+++ b/arch/powerpc/boot/wii.c
@@ -0,0 +1,158 @@
1/*
2 * arch/powerpc/boot/wii.c
3 *
4 * Nintendo Wii bootwrapper support
5 * Copyright (C) 2008-2009 The GameCube Linux Team
6 * Copyright (C) 2008,2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14
15#include <stddef.h>
16#include "stdio.h"
17#include "types.h"
18#include "io.h"
19#include "ops.h"
20
21#include "ugecon.h"
22
23BSS_STACK(8192);
24
25#define HW_REG(x) ((void *)(x))
26
27#define EXI_CTRL HW_REG(0x0d800070)
28#define EXI_CTRL_ENABLE (1<<0)
29
30#define MEM2_TOP (0x10000000 + 64*1024*1024)
31#define FIRMWARE_DEFAULT_SIZE (12*1024*1024)
32
33
34struct mipc_infohdr {
35 char magic[3];
36 u8 version;
37 u32 mem2_boundary;
38 u32 ipc_in;
39 size_t ipc_in_size;
40 u32 ipc_out;
41 size_t ipc_out_size;
42};
43
44static int mipc_check_address(u32 pa)
45{
46 /* only MEM2 addresses */
47 if (pa < 0x10000000 || pa > 0x14000000)
48 return -EINVAL;
49 return 0;
50}
51
52static struct mipc_infohdr *mipc_get_infohdr(void)
53{
54 struct mipc_infohdr **hdrp, *hdr;
55
56 /* 'mini' header pointer is the last word of MEM2 memory */
57 hdrp = (struct mipc_infohdr **)0x13fffffc;
58 if (mipc_check_address((u32)hdrp)) {
59 printf("mini: invalid hdrp %08X\n", (u32)hdrp);
60 hdr = NULL;
61 goto out;
62 }
63
64 hdr = *hdrp;
65 if (mipc_check_address((u32)hdr)) {
66 printf("mini: invalid hdr %08X\n", (u32)hdr);
67 hdr = NULL;
68 goto out;
69 }
70 if (memcmp(hdr->magic, "IPC", 3)) {
71 printf("mini: invalid magic\n");
72 hdr = NULL;
73 goto out;
74 }
75
76out:
77 return hdr;
78}
79
80static int mipc_get_mem2_boundary(u32 *mem2_boundary)
81{
82 struct mipc_infohdr *hdr;
83 int error;
84
85 hdr = mipc_get_infohdr();
86 if (!hdr) {
87 error = -1;
88 goto out;
89 }
90
91 if (mipc_check_address(hdr->mem2_boundary)) {
92 printf("mini: invalid mem2_boundary %08X\n",
93 hdr->mem2_boundary);
94 error = -EINVAL;
95 goto out;
96 }
97 *mem2_boundary = hdr->mem2_boundary;
98 error = 0;
99out:
100 return error;
101
102}
103
104static void platform_fixups(void)
105{
106 void *mem;
107 u32 reg[4];
108 u32 mem2_boundary;
109 int len;
110 int error;
111
112 mem = finddevice("/memory");
113 if (!mem)
114 fatal("Can't find memory node\n");
115
116 /* two ranges of (address, size) words */
117 len = getprop(mem, "reg", reg, sizeof(reg));
118 if (len != sizeof(reg)) {
119 /* nothing to do */
120 goto out;
121 }
122
123 /* retrieve MEM2 boundary from 'mini' */
124 error = mipc_get_mem2_boundary(&mem2_boundary);
125 if (error) {
126 /* if that fails use a sane value */
127 mem2_boundary = MEM2_TOP - FIRMWARE_DEFAULT_SIZE;
128 }
129
130 if (mem2_boundary > reg[2] && mem2_boundary < reg[2] + reg[3]) {
131 reg[3] = mem2_boundary - reg[2];
132 printf("top of MEM2 @ %08X\n", reg[2] + reg[3]);
133 setprop(mem, "reg", reg, sizeof(reg));
134 }
135
136out:
137 return;
138}
139
140void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
141{
142 u32 heapsize = 24*1024*1024 - (u32)_end;
143
144 simple_alloc_init(_end, heapsize, 32, 64);
145 fdt_init(_dtb_start);
146
147 /*
148 * 'mini' boots the Broadway processor with EXI disabled.
149 * We need it enabled before probing for the USB Gecko.
150 */
151 out_be32(EXI_CTRL, in_be32(EXI_CTRL) | EXI_CTRL_ENABLE);
152
153 if (ug_probe())
154 console_ops.write = ug_console_write;
155
156 platform_ops.fixups = platform_fixups;
157}
158
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index ac9e9a58b2b0..f4594ed09a20 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -43,6 +43,9 @@ gzip=.gz
43# cross-compilation prefix 43# cross-compilation prefix
44CROSS= 44CROSS=
45 45
46# mkimage wrapper script
47MKIMAGE=$srctree/scripts/mkuboot.sh
48
46# directory for object and other files used by this script 49# directory for object and other files used by this script
47object=arch/powerpc/boot 50object=arch/powerpc/boot
48objbin=$object 51objbin=$object
@@ -230,6 +233,10 @@ xpedite52*)
230 link_address='0x1400000' 233 link_address='0x1400000'
231 platformo=$object/cuboot-85xx.o 234 platformo=$object/cuboot-85xx.o
232 ;; 235 ;;
236gamecube|wii)
237 link_address='0x600000'
238 platformo="$object/$platform-head.o $object/$platform.o"
239 ;;
233esac 240esac
234 241
235vmz="$tmpdir/`basename \"$kernel\"`.$ext" 242vmz="$tmpdir/`basename \"$kernel\"`.$ext"
@@ -263,7 +270,7 @@ membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
263case "$platform" in 270case "$platform" in
264uboot) 271uboot)
265 rm -f "$ofile" 272 rm -f "$ofile"
266 mkimage -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \ 273 ${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
267 $uboot_version -d "$vmz" "$ofile" 274 $uboot_version -d "$vmz" "$ofile"
268 if [ -z "$cacheit" ]; then 275 if [ -z "$cacheit" ]; then
269 rm -f "$vmz" 276 rm -f "$vmz"
@@ -323,7 +330,7 @@ coff)
323 ;; 330 ;;
324cuboot*) 331cuboot*)
325 gzip -f -9 "$ofile" 332 gzip -f -9 "$ofile"
326 mkimage -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \ 333 ${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \
327 $uboot_version -d "$ofile".gz "$ofile" 334 $uboot_version -d "$ofile".gz "$ofile"
328 ;; 335 ;;
329treeboot*) 336treeboot*)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 12:15:45 -0400