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-rw-r--r--arch/powerpc/boot/dts/bluestone.dts254
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts73
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts194
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts177
-rw-r--r--arch/powerpc/boot/dts/hotfoot.dts2
-rw-r--r--arch/powerpc/boot/dts/katmai.dts18
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts37
-rw-r--r--arch/powerpc/boot/dts/kmeter1.dts69
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts220
-rw-r--r--arch/powerpc/boot/dts/media5200.dts214
-rw-r--r--arch/powerpc/boot/dts/mgcoge.dts47
-rw-r--r--arch/powerpc/boot/dts/mgsuvd.dts163
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts194
-rw-r--r--arch/powerpc/boot/dts/mpc5200b.dtsi275
-rw-r--r--arch/powerpc/boot/dts/mpc8308_p1m.dts340
-rw-r--r--arch/powerpc/boot/dts/mpc8308rdb.dts10
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts13
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts52
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts13
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts1
-rw-r--r--arch/powerpc/boot/dts/mucmc52.dts174
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dts344
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core0.dts213
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core1.dts148
-rw-r--r--arch/powerpc/boot/dts/p1020si.dtsi377
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts132
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dts385
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts401
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts249
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts160
-rw-r--r--arch/powerpc/boot/dts/p2020si.dtsi382
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts97
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts196
-rw-r--r--arch/powerpc/boot/dts/pcm032.dts242
-rw-r--r--arch/powerpc/boot/dts/redwood.dts20
-rw-r--r--arch/powerpc/boot/dts/uc101.dts160
36 files changed, 2956 insertions, 3090 deletions
diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts
new file mode 100644
index 000000000000..2a56a0dbd1f7
--- /dev/null
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -0,0 +1,254 @@
1/*
2 * Device Tree for Bluestone (APM821xx) board.
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24/dts-v1/;
25
26/ {
27 #address-cells = <2>;
28 #size-cells = <1>;
29 model = "apm,bluestone";
30 compatible = "apm,bluestone";
31 dcr-parent = <&{/cpus/cpu@0}>;
32
33 aliases {
34 ethernet0 = &EMAC0;
35 serial0 = &UART0;
36 //serial1 = &UART1; --gcl missing UART1 label
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@0 {
44 device_type = "cpu";
45 model = "PowerPC,apm821xx";
46 reg = <0x00000000>;
47 clock-frequency = <0>; /* Filled in by U-Boot */
48 timebase-frequency = <0>; /* Filled in by U-Boot */
49 i-cache-line-size = <32>;
50 d-cache-line-size = <32>;
51 i-cache-size = <32768>;
52 d-cache-size = <32768>;
53 dcr-controller;
54 dcr-access-method = "native";
55 //next-level-cache = <&L2C0>; --gcl missing L2C0 label
56 };
57 };
58
59 memory {
60 device_type = "memory";
61 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
62 };
63
64 UIC0: interrupt-controller0 {
65 compatible = "ibm,uic";
66 interrupt-controller;
67 cell-index = <0>;
68 dcr-reg = <0x0c0 0x009>;
69 #address-cells = <0>;
70 #size-cells = <0>;
71 #interrupt-cells = <2>;
72 };
73
74 UIC1: interrupt-controller1 {
75 compatible = "ibm,uic";
76 interrupt-controller;
77 cell-index = <1>;
78 dcr-reg = <0x0d0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
82 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
83 interrupt-parent = <&UIC0>;
84 };
85
86 UIC2: interrupt-controller2 {
87 compatible = "ibm,uic";
88 interrupt-controller;
89 cell-index = <2>;
90 dcr-reg = <0x0e0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
94 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
95 interrupt-parent = <&UIC0>;
96 };
97
98 UIC3: interrupt-controller3 {
99 compatible = "ibm,uic";
100 interrupt-controller;
101 cell-index = <3>;
102 dcr-reg = <0x0f0 0x009>;
103 #address-cells = <0>;
104 #size-cells = <0>;
105 #interrupt-cells = <2>;
106 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
107 interrupt-parent = <&UIC0>;
108 };
109
110 SDR0: sdr {
111 compatible = "ibm,sdr-apm821xx";
112 dcr-reg = <0x00e 0x002>;
113 };
114
115 CPR0: cpr {
116 compatible = "ibm,cpr-apm821xx";
117 dcr-reg = <0x00c 0x002>;
118 };
119
120 plb {
121 compatible = "ibm,plb4";
122 #address-cells = <2>;
123 #size-cells = <1>;
124 ranges;
125 clock-frequency = <0>; /* Filled in by U-Boot */
126
127 SDRAM0: sdram {
128 compatible = "ibm,sdram-apm821xx";
129 dcr-reg = <0x010 0x002>;
130 };
131
132 MAL0: mcmal {
133 compatible = "ibm,mcmal2";
134 descriptor-memory = "ocm";
135 dcr-reg = <0x180 0x062>;
136 num-tx-chans = <1>;
137 num-rx-chans = <1>;
138 #address-cells = <0>;
139 #size-cells = <0>;
140 interrupt-parent = <&UIC2>;
141 interrupts = < /*TXEOB*/ 0x6 0x4
142 /*RXEOB*/ 0x7 0x4
143 /*SERR*/ 0x3 0x4
144 /*TXDE*/ 0x4 0x4
145 /*RXDE*/ 0x5 0x4>;
146 };
147
148 POB0: opb {
149 compatible = "ibm,opb";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
153 clock-frequency = <0>; /* Filled in by U-Boot */
154
155 EBC0: ebc {
156 compatible = "ibm,ebc";
157 dcr-reg = <0x012 0x002>;
158 #address-cells = <2>;
159 #size-cells = <1>;
160 clock-frequency = <0>; /* Filled in by U-Boot */
161 /* ranges property is supplied by U-Boot */
162 ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
163 interrupts = <0x6 0x4>;
164 interrupt-parent = <&UIC1>;
165
166 nor_flash@0,0 {
167 compatible = "amd,s29gl512n", "cfi-flash";
168 bank-width = <2>;
169 reg = <0x00000000 0x00000000 0x00400000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 partition@0 {
173 label = "kernel";
174 reg = <0x00000000 0x00180000>;
175 };
176 partition@180000 {
177 label = "env";
178 reg = <0x00180000 0x00020000>;
179 };
180 partition@1a0000 {
181 label = "u-boot";
182 reg = <0x001a0000 0x00060000>;
183 };
184 };
185 };
186
187 UART0: serial@ef600300 {
188 device_type = "serial";
189 compatible = "ns16550";
190 reg = <0xef600300 0x00000008>;
191 virtual-reg = <0xef600300>;
192 clock-frequency = <0>; /* Filled in by U-Boot */
193 current-speed = <0>; /* Filled in by U-Boot */
194 interrupt-parent = <&UIC1>;
195 interrupts = <0x1 0x4>;
196 };
197
198 IIC0: i2c@ef600700 {
199 compatible = "ibm,iic";
200 reg = <0xef600700 0x00000014>;
201 interrupt-parent = <&UIC0>;
202 interrupts = <0x2 0x4>;
203 };
204
205 IIC1: i2c@ef600800 {
206 compatible = "ibm,iic";
207 reg = <0xef600800 0x00000014>;
208 interrupt-parent = <&UIC0>;
209 interrupts = <0x3 0x4>;
210 };
211
212 RGMII0: emac-rgmii@ef601500 {
213 compatible = "ibm,rgmii";
214 reg = <0xef601500 0x00000008>;
215 has-mdio;
216 };
217
218 TAH0: emac-tah@ef601350 {
219 compatible = "ibm,tah";
220 reg = <0xef601350 0x00000030>;
221 };
222
223 EMAC0: ethernet@ef600c00 {
224 device_type = "network";
225 compatible = "ibm,emac4sync";
226 interrupt-parent = <&EMAC0>;
227 interrupts = <0x0 0x1>;
228 #interrupt-cells = <1>;
229 #address-cells = <0>;
230 #size-cells = <0>;
231 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
232 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
233 reg = <0xef600c00 0x000000c4>;
234 local-mac-address = [000000000000]; /* Filled in by U-Boot */
235 mal-device = <&MAL0>;
236 mal-tx-channel = <0>;
237 mal-rx-channel = <0>;
238 cell-index = <0>;
239 max-frame-size = <9000>;
240 rx-fifo-size = <16384>;
241 tx-fifo-size = <2048>;
242 phy-mode = "rgmii";
243 phy-map = <0x00000000>;
244 rgmii-device = <&RGMII0>;
245 rgmii-channel = <0>;
246 tah-device = <&TAH0>;
247 tah-channel = <0>;
248 has-inverted-stacr-oc;
249 has-new-stacr-staopc;
250 };
251 };
252
253 };
254};
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index a30370396250..22dd6ae84da0 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -105,6 +105,15 @@
105 dcr-reg = <0x00c 0x002>; 105 dcr-reg = <0x00c 0x002>;
106 }; 106 };
107 107
108 CPM0: cpm {
109 compatible = "ibm,cpm";
110 dcr-access-method = "native";
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
114 standby = <0xfeff791d>;
115 };
116
108 L2C0: l2c { 117 L2C0: l2c {
109 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; 118 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
110 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
@@ -163,6 +172,19 @@
163 interrupts = <0x1e 4>; 172 interrupts = <0x1e 4>;
164 }; 173 };
165 174
175 USBOTG0: usbotg@bff80000 {
176 compatible = "amcc,dwc-otg";
177 reg = <0x4 0xbff80000 0x10000>;
178 interrupt-parent = <&USBOTG0>;
179 #interrupt-cells = <1>;
180 #address-cells = <0>;
181 #size-cells = <0>;
182 interrupts = <0x0 0x1 0x2>;
183 interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
184 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
185 /* DMA */ 0x2 &UIC0 0xc 0x4>;
186 };
187
166 SATA0: sata@bffd1000 { 188 SATA0: sata@bffd1000 {
167 compatible = "amcc,sata-460ex"; 189 compatible = "amcc,sata-460ex";
168 reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; 190 reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
@@ -224,6 +246,11 @@
224 }; 246 };
225 }; 247 };
226 248
249 cpld@2,0 {
250 compatible = "amcc,ppc460ex-bcsr";
251 reg = <2 0x0 0x9>;
252 };
253
227 ndfc@3,0 { 254 ndfc@3,0 {
228 compatible = "ibm,ndfc"; 255 compatible = "ibm,ndfc";
229 reg = <0x00000003 0x00000000 0x00002000>; 256 reg = <0x00000003 0x00000000 0x00002000>;
@@ -270,28 +297,6 @@
270 interrupts = <0x1 0x4>; 297 interrupts = <0x1 0x4>;
271 }; 298 };
272 299
273 UART2: serial@ef600500 {
274 device_type = "serial";
275 compatible = "ns16550";
276 reg = <0xef600500 0x00000008>;
277 virtual-reg = <0xef600500>;
278 clock-frequency = <0>; /* Filled in by U-Boot */
279 current-speed = <0>; /* Filled in by U-Boot */
280 interrupt-parent = <&UIC1>;
281 interrupts = <28 0x4>;
282 };
283
284 UART3: serial@ef600600 {
285 device_type = "serial";
286 compatible = "ns16550";
287 reg = <0xef600600 0x00000008>;
288 virtual-reg = <0xef600600>;
289 clock-frequency = <0>; /* Filled in by U-Boot */
290 current-speed = <0>; /* Filled in by U-Boot */
291 interrupt-parent = <&UIC1>;
292 interrupts = <29 0x4>;
293 };
294
295 IIC0: i2c@ef600700 { 300 IIC0: i2c@ef600700 {
296 compatible = "ibm,iic-460ex", "ibm,iic"; 301 compatible = "ibm,iic-460ex", "ibm,iic";
297 reg = <0xef600700 0x00000014>; 302 reg = <0xef600700 0x00000014>;
@@ -320,6 +325,12 @@
320 interrupts = <0x3 0x4>; 325 interrupts = <0x3 0x4>;
321 }; 326 };
322 327
328 GPIO0: gpio@ef600b00 {
329 compatible = "ibm,ppc4xx-gpio";
330 reg = <0xef600b00 0x00000048>;
331 gpio-controller;
332 };
333
323 ZMII0: emac-zmii@ef600d00 { 334 ZMII0: emac-zmii@ef600d00 {
324 compatible = "ibm,zmii-460ex", "ibm,zmii"; 335 compatible = "ibm,zmii-460ex", "ibm,zmii";
325 reg = <0xef600d00 0x0000000c>; 336 reg = <0xef600d00 0x0000000c>;
@@ -519,5 +530,23 @@
519 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 530 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
520 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 531 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
521 }; 532 };
533
534 MSI: ppc4xx-msi@C10000000 {
535 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
536 reg = < 0xC 0x10000000 0x100>;
537 sdr-base = <0x36C>;
538 msi-data = <0x00000000>;
539 msi-mask = <0x44440000>;
540 interrupt-count = <3>;
541 interrupts = <0 1 2 3>;
542 interrupt-parent = <&UIC3>;
543 #interrupt-cells = <1>;
544 #address-cells = <0>;
545 #size-cells = <0>;
546 interrupt-map = <0 &UIC3 0x18 1
547 1 &UIC3 0x19 1
548 2 &UIC3 0x1A 1
549 3 &UIC3 0x1B 1>;
550 };
522 }; 551 };
523}; 552};
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index dd3860846f15..ad3a4f4a2b04 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -10,220 +10,74 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "schindler,cm5200"; 16 model = "schindler,cm5200";
17 compatible = "schindler,cm5200"; 17 compatible = "schindler,cm5200";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x04000000>; // 64MB
42 };
43 18
44 soc5200@f0000000 { 19 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 20 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 21 fsl,has-wdt;
71 }; 22 };
72 23
73 timer@610 { // General Purpose Timer 24 can@900 {
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 25 status = "disabled";
75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
107 };
108
109 timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
113 }; 26 };
114 27
115 rtc@800 { // Real time clock 28 can@980 {
116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 29 status = "disabled";
117 reg = <0x800 0x100>;
118 interrupts = <1 5 0 1 6 0>;
119 }; 30 };
120 31
121 gpio_simple: gpio@b00 { 32 psc@2000 { // PSC1
122 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 33 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
123 reg = <0xb00 0x40>;
124 interrupts = <1 7 0>;
125 gpio-controller;
126 #gpio-cells = <2>;
127 };
128
129 gpio_wkup: gpio@c00 {
130 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
131 reg = <0xc00 0x40>;
132 interrupts = <1 8 0 0 3 0>;
133 gpio-controller;
134 #gpio-cells = <2>;
135 };
136
137 spi@f00 {
138 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
139 reg = <0xf00 0x20>;
140 interrupts = <2 13 0 2 14 0>;
141 };
142
143 usb@1000 {
144 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
145 reg = <0x1000 0xff>;
146 interrupts = <2 6 0>;
147 };
148
149 dma-controller@1200 {
150 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
151 reg = <0x1200 0x80>;
152 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
153 3 4 0 3 5 0 3 6 0 3 7 0
154 3 8 0 3 9 0 3 10 0 3 11 0
155 3 12 0 3 13 0 3 14 0 3 15 0>;
156 }; 34 };
157 35
158 xlb@1f00 { 36 psc@2200 { // PSC2
159 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 37 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
160 reg = <0x1f00 0x100>;
161 }; 38 };
162 39
163 serial@2000 { // PSC1 40 psc@2400 { // PSC3
164 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 41 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
165 reg = <0x2000 0x100>;
166 interrupts = <2 1 0>;
167 }; 42 };
168 43
169 serial@2200 { // PSC2 44 psc@2600 { // PSC4
170 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 45 status = "disabled";
171 reg = <0x2200 0x100>;
172 interrupts = <2 2 0>;
173 }; 46 };
174 47
175 serial@2400 { // PSC3 48 psc@2800 { // PSC5
176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 49 status = "disabled";
177 reg = <0x2400 0x100>;
178 interrupts = <2 3 0>;
179 }; 50 };
180 51
181 serial@2c00 { // PSC6 52 psc@2c00 { // PSC6
182 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 53 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183 reg = <0x2c00 0x100>;
184 interrupts = <2 4 0>;
185 }; 54 };
186 55
187 ethernet@3000 { 56 ethernet@3000 {
188 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
189 reg = <0x3000 0x400>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <2 5 0>;
192 phy-handle = <&phy0>; 57 phy-handle = <&phy0>;
193 }; 58 };
194 59
195 mdio@3000 { 60 mdio@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
199 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
200 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
201
202 phy0: ethernet-phy@0 { 61 phy0: ethernet-phy@0 {
203 reg = <0>; 62 reg = <0>;
204 }; 63 };
205 }; 64 };
206 65
207 i2c@3d40 { 66 ata@3a00 {
208 #address-cells = <1>; 67 status = "disabled";
209 #size-cells = <0>;
210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
211 reg = <0x3d40 0x40>;
212 interrupts = <2 16 0>;
213 }; 68 };
214 69
215 sram@8000 { 70 i2c@3d00 {
216 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 71 status = "disabled";
217 reg = <0x8000 0x4000>;
218 }; 72 };
73
219 }; 74 };
220 75
221 localbus { 76 pci@f0000d00 {
222 compatible = "fsl,mpc5200b-lpb","simple-bus"; 77 status = "disabled";
223 #address-cells = <2>; 78 };
224 #size-cells = <1>;
225 ranges = <0 0 0xfc000000 0x2000000>;
226 79
80 localbus {
227 // 16-bit flash device at LocalPlus Bus CS0 81 // 16-bit flash device at LocalPlus Bus CS0
228 flash@0,0 { 82 flash@0,0 {
229 compatible = "cfi-flash"; 83 compatible = "cfi-flash";
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index 8e9be6bfe23e..27bd267d631c 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -11,195 +11,68 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "intercontrol,digsy-mtc"; 17 model = "intercontrol,digsy-mtc";
18 compatible = "intercontrol,digsy-mtc"; 18 compatible = "intercontrol,digsy-mtc";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39 19
40 memory { 20 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x02000000>; // 32MB 21 reg = <0x00000000 0x02000000>; // 32MB
43 }; 22 };
44 23
45 soc5200@f0000000 { 24 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer 25 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt; 26 fsl,has-wdt;
72 }; 27 };
73 28
74 timer@610 { // General Purpose Timer 29 rtc@800 {
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 30 status = "disabled";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 };
85
86 timer@630 { // General Purpose Timer
87 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
88 reg = <0x630 0x10>;
89 interrupts = <1 12 0>;
90 };
91
92 timer@640 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 reg = <0x640 0x10>;
95 interrupts = <1 13 0>;
96 };
97
98 timer@650 { // General Purpose Timer
99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 reg = <0x650 0x10>;
101 interrupts = <1 14 0>;
102 }; 31 };
103 32
104 timer@660 { // General Purpose Timer 33 can@900 {
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 34 status = "disabled";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 }; 35 };
109 36
110 timer@670 { // General Purpose Timer 37 can@980 {
111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 38 status = "disabled";
112 reg = <0x670 0x10>;
113 interrupts = <1 16 0>;
114 }; 39 };
115 40
116 gpio_simple: gpio@b00 { 41 psc@2000 { // PSC1
117 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 42 status = "disabled";
118 reg = <0xb00 0x40>;
119 interrupts = <1 7 0>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 }; 43 };
123 44
124 gpio_wkup: gpio@c00 { 45 psc@2200 { // PSC2
125 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 46 status = "disabled";
126 reg = <0xc00 0x40>;
127 interrupts = <1 8 0 0 3 0>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 }; 47 };
131 48
132 spi@f00 { 49 psc@2400 { // PSC3
133 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 50 status = "disabled";
134 reg = <0xf00 0x20>;
135 interrupts = <2 13 0 2 14 0>;
136 }; 51 };
137 52
138 usb@1000 { 53 psc@2600 { // PSC4
139 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
140 reg = <0x1000 0xff>;
141 interrupts = <2 6 0>;
142 };
143
144 dma-controller@1200 {
145 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
146 reg = <0x1200 0x80>;
147 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
148 3 4 0 3 5 0 3 6 0 3 7 0
149 3 8 0 3 9 0 3 10 0 3 11 0
150 3 12 0 3 13 0 3 14 0 3 15 0>;
151 };
152
153 xlb@1f00 {
154 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
155 reg = <0x1f00 0x100>;
156 }; 55 };
157 56
158 serial@2600 { // PSC4 57 psc@2800 { // PSC5
159 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
160 reg = <0x2600 0x100>;
161 interrupts = <2 11 0>;
162 }; 59 };
163 60
164 serial@2800 { // PSC5 61 psc@2c00 { // PSC6
165 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 62 status = "disabled";
166 reg = <0x2800 0x100>;
167 interrupts = <2 12 0>;
168 }; 63 };
169 64
170 ethernet@3000 { 65 ethernet@3000 {
171 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
172 reg = <0x3000 0x400>;
173 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupts = <2 5 0>;
175 phy-handle = <&phy0>; 66 phy-handle = <&phy0>;
176 }; 67 };
177 68
178 mdio@3000 { 69 mdio@3000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
182 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
183 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
184
185 phy0: ethernet-phy@0 { 70 phy0: ethernet-phy@0 {
186 reg = <0>; 71 reg = <0>;
187 }; 72 };
188 }; 73 };
189 74
190 ata@3a00 {
191 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
192 reg = <0x3a00 0x100>;
193 interrupts = <2 7 0>;
194 };
195
196 i2c@3d00 { 75 i2c@3d00 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
200 reg = <0x3d00 0x40>;
201 interrupts = <2 15 0>;
202
203 rtc@50 { 76 rtc@50 {
204 compatible = "at,24c08"; 77 compatible = "at,24c08";
205 reg = <0x50>; 78 reg = <0x50>;
@@ -211,16 +84,16 @@
211 }; 84 };
212 }; 85 };
213 86
214 sram@8000 { 87 i2c@3d40 {
215 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 88 status = "disabled";
216 reg = <0x8000 0x4000>;
217 }; 89 };
218 }; 90 };
219 91
220 lpb { 92 pci@f0000d00 {
221 compatible = "fsl,mpc5200b-lpb","simple-bus"; 93 status = "disabled";
222 #address-cells = <2>; 94 };
223 #size-cells = <1>; 95
96 localbus {
224 ranges = <0 0 0xff000000 0x1000000>; 97 ranges = <0 0 0xff000000 0x1000000>;
225 98
226 // 16-bit flash device at LocalPlus Bus CS0 99 // 16-bit flash device at LocalPlus Bus CS0
diff --git a/arch/powerpc/boot/dts/hotfoot.dts b/arch/powerpc/boot/dts/hotfoot.dts
index cad9c3840afc..71d3bb4931dc 100644
--- a/arch/powerpc/boot/dts/hotfoot.dts
+++ b/arch/powerpc/boot/dts/hotfoot.dts
@@ -117,6 +117,8 @@
117 }; 117 };
118 118
119 IIC: i2c@ef600500 { 119 IIC: i2c@ef600500 {
120 #address-cells = <1>;
121 #size-cells = <0>;
120 compatible = "ibm,iic-405ep", "ibm,iic"; 122 compatible = "ibm,iic-405ep", "ibm,iic";
121 reg = <0xef600500 0x00000011>; 123 reg = <0xef600500 0x00000011>;
122 interrupt-parent = <&UIC0>; 124 interrupt-parent = <&UIC0>;
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 7c3be5e45748..f913dbe25d35 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -442,6 +442,24 @@
442 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; 442 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
443 }; 443 };
444 444
445 MSI: ppc4xx-msi@400300000 {
446 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
447 reg = < 0x4 0x00300000 0x100>;
448 sdr-base = <0x3B0>;
449 msi-data = <0x00000000>;
450 msi-mask = <0x44440000>;
451 interrupt-count = <3>;
452 interrupts =<0 1 2 3>;
453 interrupt-parent = <&UIC0>;
454 #interrupt-cells = <1>;
455 #address-cells = <0>;
456 #size-cells = <0>;
457 interrupt-map = <0 &UIC0 0xC 1
458 1 &UIC0 0x0D 1
459 2 &UIC0 0x0E 1
460 3 &UIC0 0x0F 1>;
461 };
462
445 I2O: i2o@400100000 { 463 I2O: i2o@400100000 {
446 compatible = "ibm,i2o-440spe"; 464 compatible = "ibm,i2o-440spe";
447 reg = <0x00000004 0x00100000 0x100>; 465 reg = <0x00000004 0x00100000 0x100>;
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 083e68eeaca4..1613d6e4049e 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -82,6 +82,15 @@
82 interrupt-parent = <&UIC0>; 82 interrupt-parent = <&UIC0>;
83 }; 83 };
84 84
85 CPM0: cpm {
86 compatible = "ibm,cpm";
87 dcr-access-method = "native";
88 dcr-reg = <0x0b0 0x003>;
89 unused-units = <0x00000000>;
90 idle-doze = <0x02000000>;
91 standby = <0xe3e74800>;
92 };
93
85 plb { 94 plb {
86 compatible = "ibm,plb-405ex", "ibm,plb4"; 95 compatible = "ibm,plb-405ex", "ibm,plb4";
87 #address-cells = <1>; 96 #address-cells = <1>;
@@ -394,5 +403,33 @@
394 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ 403 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
395 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; 404 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
396 }; 405 };
406
407 MSI: ppc4xx-msi@C10000000 {
408 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
409 reg = < 0x0 0xEF620000 0x100>;
410 sdr-base = <0x4B0>;
411 msi-data = <0x00000000>;
412 msi-mask = <0x44440000>;
413 interrupt-count = <12>;
414 interrupts = <0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD>;
415 interrupt-parent = <&UIC2>;
416 #interrupt-cells = <1>;
417 #address-cells = <0>;
418 #size-cells = <0>;
419 interrupt-map = <0 &UIC2 0x10 1
420 1 &UIC2 0x11 1
421 2 &UIC2 0x12 1
422 2 &UIC2 0x13 1
423 2 &UIC2 0x14 1
424 2 &UIC2 0x15 1
425 2 &UIC2 0x16 1
426 2 &UIC2 0x17 1
427 2 &UIC2 0x18 1
428 2 &UIC2 0x19 1
429 2 &UIC2 0x1A 1
430 2 &UIC2 0x1B 1
431 2 &UIC2 0x1C 1
432 3 &UIC2 0x1D 1>;
433 };
397 }; 434 };
398}; 435};
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index d8b5d12fb663..d16bae1230f7 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Keymile KMETER1 Device Tree Source 2 * Keymile KMETER1 Device Tree Source
3 * 3 *
4 * 2008 DENX Software Engineering GmbH 4 * 2008-2011 DENX Software Engineering GmbH
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -70,11 +70,11 @@
70 #address-cells = <1>; 70 #address-cells = <1>;
71 #size-cells = <0>; 71 #size-cells = <0>;
72 cell-index = <0>; 72 cell-index = <0>;
73 compatible = "fsl-i2c"; 73 compatible = "fsl,mpc8313-i2c","fsl-i2c";
74 reg = <0x3000 0x100>; 74 reg = <0x3000 0x100>;
75 interrupts = <14 0x8>; 75 interrupts = <14 0x8>;
76 interrupt-parent = <&ipic>; 76 interrupt-parent = <&ipic>;
77 dfsrr; 77 clock-frequency = <400000>;
78 }; 78 };
79 79
80 serial0: serial@4500 { 80 serial0: serial@4500 {
@@ -137,6 +137,13 @@
137 compatible = "fsl,mpc8360-par_io"; 137 compatible = "fsl,mpc8360-par_io";
138 num-ports = <7>; 138 num-ports = <7>;
139 139
140 qe_pio_c: gpio-controller@30 {
141 #gpio-cells = <2>;
142 compatible = "fsl,mpc8360-qe-pario-bank",
143 "fsl,mpc8323-qe-pario-bank";
144 reg = <0x1430 0x18>;
145 gpio-controller;
146 };
140 pio_ucc1: ucc_pin@0 { 147 pio_ucc1: ucc_pin@0 {
141 reg = <0>; 148 reg = <0>;
142 149
@@ -472,7 +479,17 @@
472 #address-cells = <0>; 479 #address-cells = <0>;
473 #interrupt-cells = <1>; 480 #interrupt-cells = <1>;
474 reg = <0x80 0x80>; 481 reg = <0x80 0x80>;
475 interrupts = <32 8 33 8>; 482 big-endian;
483 interrupts = <
484 32 0x8
485 33 0x8
486 34 0x8
487 35 0x8
488 40 0x8
489 41 0x8
490 42 0x8
491 43 0x8
492 >;
476 interrupt-parent = <&ipic>; 493 interrupt-parent = <&ipic>;
477 }; 494 };
478 }; 495 };
@@ -484,43 +501,31 @@
484 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 501 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
485 "simple-bus"; 502 "simple-bus";
486 reg = <0xe0005000 0xd8>; 503 reg = <0xe0005000 0xd8>;
487 ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */ 504 ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
505 1 0 0xe8000000 0x01000000 /* LB 1 */
506 3 0 0xa0000000 0x10000000>; /* LB 3 */
488 507
489 flash@f0000000,0 { 508 flash@0,0 {
490 compatible = "cfi-flash"; 509 compatible = "cfi-flash";
491 /* 510 reg = <0 0 0x04000000>;
492 * The Intel P30 chip has 2 non-identical chips on
493 * one die, so we need to define 2 separate regions
494 * that are scanned by physmap_of independantly.
495 */
496 reg = <0 0x00000000 0x02000000
497 0 0x02000000 0x02000000>; /* Filled in by U-Boot */
498 bank-width = <2>;
499 #address-cells = <1>; 511 #address-cells = <1>;
500 #size-cells = <1>; 512 #size-cells = <1>;
501 partition@0 { 513 bank-width = <2>;
514 partition@0 { /* 768KB */
502 label = "u-boot"; 515 label = "u-boot";
503 reg = <0 0x40000>; 516 reg = <0 0xC0000>;
504 }; 517 };
505 partition@40000 { 518 partition@c0000 { /* 128KB */
506 label = "env"; 519 label = "env";
507 reg = <0x40000 0x40000>; 520 reg = <0xC0000 0x20000>;
508 };
509 partition@80000 {
510 label = "dtb";
511 reg = <0x80000 0x20000>;
512 };
513 partition@a0000 {
514 label = "kernel";
515 reg = <0xa0000 0x300000>;
516 }; 521 };
517 partition@3a0000 { 522 partition@e0000 { /* 128KB */
518 label = "ramdisk"; 523 label = "envred";
519 reg = <0x3a0000 0x800000>; 524 reg = <0xE0000 0x20000>;
520 }; 525 };
521 partition@ba0000 { 526 partition@100000 { /* 64512KB */
522 label = "user"; 527 label = "ubi0";
523 reg = <0xba0000 0x3460000>; 528 reg = <0x100000 0x3F00000>;
524 }; 529 };
525 }; 530 };
526 }; 531 };
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 59702ace900f..fb288bb882b6 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -10,256 +10,75 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "fsl,lite5200b"; 16 model = "fsl,lite5200b";
17 compatible = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38 18
39 memory { 19 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x10000000>; // 256MB 20 reg = <0x00000000 0x10000000>; // 256MB
42 }; 21 };
43 22
44 soc5200@f0000000 { 23 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 24 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 25 fsl,has-wdt;
71 }; 26 };
72 27
73 timer@610 { // General Purpose Timer 28 psc@2000 { // PSC1
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 29 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
75 reg = <0x610 0x10>; 30 cell-index = <0>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
107 };
108
109 timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
113 };
114
115 rtc@800 { // Real time clock
116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117 reg = <0x800 0x100>;
118 interrupts = <1 5 0 1 6 0>;
119 };
120
121 can@900 {
122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
123 interrupts = <2 17 0>;
124 reg = <0x900 0x80>;
125 };
126
127 can@980 {
128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
129 interrupts = <2 18 0>;
130 reg = <0x980 0x80>;
131 };
132
133 gpio_simple: gpio@b00 {
134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
135 reg = <0xb00 0x40>;
136 interrupts = <1 7 0>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 gpio_wkup: gpio@c00 {
142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
143 reg = <0xc00 0x40>;
144 interrupts = <1 8 0 0 3 0>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 }; 31 };
148 32
149 spi@f00 { 33 psc@2200 { // PSC2
150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 34 status = "disabled";
151 reg = <0xf00 0x20>;
152 interrupts = <2 13 0 2 14 0>;
153 }; 35 };
154 36
155 usb@1000 { 37 psc@2400 { // PSC3
156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 38 status = "disabled";
157 reg = <0x1000 0xff>;
158 interrupts = <2 6 0>;
159 }; 39 };
160 40
161 dma-controller@1200 { 41 psc@2600 { // PSC4
162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 42 status = "disabled";
163 reg = <0x1200 0x80>;
164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
165 3 4 0 3 5 0 3 6 0 3 7 0
166 3 8 0 3 9 0 3 10 0 3 11 0
167 3 12 0 3 13 0 3 14 0 3 15 0>;
168 }; 43 };
169 44
170 xlb@1f00 { 45 psc@2800 { // PSC5
171 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 46 status = "disabled";
172 reg = <0x1f00 0x100>;
173 }; 47 };
174 48
175 serial@2000 { // PSC1 49 psc@2c00 { // PSC6
176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 50 status = "disabled";
177 cell-index = <0>;
178 reg = <0x2000 0x100>;
179 interrupts = <2 1 0>;
180 }; 51 };
181 52
182 // PSC2 in ac97 mode example 53 // PSC2 in ac97 mode example
183 //ac97@2200 { // PSC2 54 //ac97@2200 { // PSC2
184 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 55 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
185 // cell-index = <1>; 56 // cell-index = <1>;
186 // reg = <0x2200 0x100>;
187 // interrupts = <2 2 0>;
188 //}; 57 //};
189 58
190 // PSC3 in CODEC mode example 59 // PSC3 in CODEC mode example
191 //i2s@2400 { // PSC3 60 //i2s@2400 { // PSC3
192 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible 61 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
193 // cell-index = <2>; 62 // cell-index = <2>;
194 // reg = <0x2400 0x100>;
195 // interrupts = <2 3 0>;
196 //};
197
198 // PSC4 in uart mode example
199 //serial@2600 { // PSC4
200 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
201 // cell-index = <3>;
202 // reg = <0x2600 0x100>;
203 // interrupts = <2 11 0>;
204 //};
205
206 // PSC5 in uart mode example
207 //serial@2800 { // PSC5
208 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
209 // cell-index = <4>;
210 // reg = <0x2800 0x100>;
211 // interrupts = <2 12 0>;
212 //}; 63 //};
213 64
214 // PSC6 in spi mode example 65 // PSC6 in spi mode example
215 //spi@2c00 { // PSC6 66 //spi@2c00 { // PSC6
216 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 67 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
217 // cell-index = <5>; 68 // cell-index = <5>;
218 // reg = <0x2c00 0x100>;
219 // interrupts = <2 4 0>;
220 //}; 69 //};
221 70
222 ethernet@3000 { 71 ethernet@3000 {
223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
224 reg = <0x3000 0x400>;
225 local-mac-address = [ 00 00 00 00 00 00 ];
226 interrupts = <2 5 0>;
227 phy-handle = <&phy0>; 72 phy-handle = <&phy0>;
228 }; 73 };
229 74
230 mdio@3000 { 75 mdio@3000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
234 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
235 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
236
237 phy0: ethernet-phy@0 { 76 phy0: ethernet-phy@0 {
238 reg = <0>; 77 reg = <0>;
239 }; 78 };
240 }; 79 };
241 80
242 ata@3a00 {
243 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
244 reg = <0x3a00 0x100>;
245 interrupts = <2 7 0>;
246 };
247
248 i2c@3d00 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
252 reg = <0x3d00 0x40>;
253 interrupts = <2 15 0>;
254 };
255
256 i2c@3d40 { 81 i2c@3d40 {
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
260 reg = <0x3d40 0x40>;
261 interrupts = <2 16 0>;
262
263 eeprom@50 { 82 eeprom@50 {
264 compatible = "atmel,24c02"; 83 compatible = "atmel,24c02";
265 reg = <0x50>; 84 reg = <0x50>;
@@ -273,12 +92,6 @@
273 }; 92 };
274 93
275 pci@f0000d00 { 94 pci@f0000d00 {
276 #interrupt-cells = <1>;
277 #size-cells = <2>;
278 #address-cells = <3>;
279 device_type = "pci";
280 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
281 reg = <0xf0000d00 0x100>;
282 interrupt-map-mask = <0xf800 0 0 7>; 95 interrupt-map-mask = <0xf800 0 0 7>;
283 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 96 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
284 0xc000 0 0 2 &mpc5200_pic 1 1 3 97 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -298,11 +111,6 @@
298 }; 111 };
299 112
300 localbus { 113 localbus {
301 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
302
303 #address-cells = <2>;
304 #size-cells = <1>;
305
306 ranges = <0 0 0xfe000000 0x02000000>; 114 ranges = <0 0 0xfe000000 0x02000000>;
307 115
308 flash@0,0 { 116 flash@0,0 {
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index 0c3902bc5b6a..48d72f38e5ed 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -11,14 +11,11 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "fsl,media5200"; 17 model = "fsl,media5200";
18 compatible = "fsl,media5200"; 18 compatible = "fsl,media5200";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22 19
23 aliases { 20 aliases {
24 console = &console; 21 console = &console;
@@ -30,16 +27,7 @@
30 }; 27 };
31 28
32 cpus { 29 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5200@0 { 30 PowerPC,5200@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <0x4000>; // L1, 16K
42 i-cache-size = <0x4000>; // L1, 16K
43 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot 31 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
44 bus-frequency = <132000000>; // 132 MHz 32 bus-frequency = <132000000>; // 132 MHz
45 clock-frequency = <396000000>; // 396 MHz 33 clock-frequency = <396000000>; // 396 MHz
@@ -47,205 +35,57 @@
47 }; 35 };
48 36
49 memory { 37 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x08000000>; // 128MB RAM 38 reg = <0x00000000 0x08000000>; // 128MB RAM
52 }; 39 };
53 40
54 soc@f0000000 { 41 soc5200@f0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "fsl,mpc5200b-immr";
58 ranges = <0 0xf0000000 0x0000c000>;
59 reg = <0xf0000000 0x00000100>;
60 bus-frequency = <132000000>;// 132 MHz 42 bus-frequency = <132000000>;// 132 MHz
61 system-frequency = <0>; // from bootloader
62
63 cdm@200 {
64 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
65 reg = <0x200 0x38>;
66 };
67
68 mpc5200_pic: interrupt-controller@500 {
69 // 5200 interrupts are encoded into two levels;
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
73 reg = <0x500 0x80>;
74 };
75 43
76 timer@600 { // General Purpose Timer 44 timer@600 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 reg = <0x600 0x10>;
79 interrupts = <1 9 0>;
80 fsl,has-wdt; 45 fsl,has-wdt;
81 }; 46 };
82 47
83 timer@610 { // General Purpose Timer 48 psc@2000 { // PSC1
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 49 status = "disabled";
85 reg = <0x610 0x10>;
86 interrupts = <1 10 0>;
87 };
88
89 timer@620 { // General Purpose Timer
90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 reg = <0x620 0x10>;
92 interrupts = <1 11 0>;
93 };
94
95 timer@630 { // General Purpose Timer
96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97 reg = <0x630 0x10>;
98 interrupts = <1 12 0>;
99 };
100
101 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x640 0x10>;
104 interrupts = <1 13 0>;
105 };
106
107 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 };
112
113 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 reg = <0x660 0x10>;
116 interrupts = <1 15 0>;
117 };
118
119 timer@670 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 reg = <0x670 0x10>;
122 interrupts = <1 16 0>;
123 };
124
125 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>;
129 };
130
131 can@900 {
132 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
133 interrupts = <2 17 0>;
134 reg = <0x900 0x80>;
135 }; 50 };
136 51
137 can@980 { 52 psc@2200 { // PSC2
138 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 53 status = "disabled";
139 interrupts = <2 18 0>;
140 reg = <0x980 0x80>;
141 }; 54 };
142 55
143 gpio_simple: gpio@b00 { 56 psc@2400 { // PSC3
144 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 57 status = "disabled";
145 reg = <0xb00 0x40>;
146 interrupts = <1 7 0>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 }; 58 };
150 59
151 gpio_wkup: gpio@c00 { 60 psc@2600 { // PSC4
152 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 61 status = "disabled";
153 reg = <0xc00 0x40>;
154 interrupts = <1 8 0 0 3 0>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 }; 62 };
158 63
159 spi@f00 { 64 psc@2800 { // PSC5
160 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 65 status = "disabled";
161 reg = <0xf00 0x20>;
162 interrupts = <2 13 0 2 14 0>;
163 };
164
165 usb@1000 {
166 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
167 reg = <0x1000 0x100>;
168 interrupts = <2 6 0>;
169 };
170
171 dma-controller@1200 {
172 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
173 reg = <0x1200 0x80>;
174 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
175 3 4 0 3 5 0 3 6 0 3 7 0
176 3 8 0 3 9 0 3 10 0 3 11 0
177 3 12 0 3 13 0 3 14 0 3 15 0>;
178 };
179
180 xlb@1f00 {
181 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
182 reg = <0x1f00 0x100>;
183 }; 66 };
184 67
185 // PSC6 in uart mode 68 // PSC6 in uart mode
186 console: serial@2c00 { // PSC6 69 console: psc@2c00 { // PSC6
187 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
188 cell-index = <5>;
189 port-number = <0>; // Logical port assignment
190 reg = <0x2c00 0x100>;
191 interrupts = <2 4 0>;
192 }; 71 };
193 72
194 eth0: ethernet@3000 { 73 ethernet@3000 {
195 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
196 reg = <0x3000 0x400>;
197 local-mac-address = [ 00 00 00 00 00 00 ];
198 interrupts = <2 5 0>;
199 phy-handle = <&phy0>; 74 phy-handle = <&phy0>;
200 }; 75 };
201 76
202 mdio@3000 { 77 mdio@3000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
206 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
207 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
208
209 phy0: ethernet-phy@0 { 78 phy0: ethernet-phy@0 {
210 reg = <0>; 79 reg = <0>;
211 }; 80 };
212 }; 81 };
213 82
214 ata@3a00 { 83 usb@1000 {
215 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 84 reg = <0x1000 0x100>;
216 reg = <0x3a00 0x100>;
217 interrupts = <2 7 0>;
218 };
219
220 i2c@3d00 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
224 reg = <0x3d00 0x40>;
225 interrupts = <2 15 0>;
226 };
227
228 i2c@3d40 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
232 reg = <0x3d40 0x40>;
233 interrupts = <2 16 0>;
234 };
235
236 sram@8000 {
237 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
238 reg = <0x8000 0x4000>;
239 }; 85 };
240 }; 86 };
241 87
242 pci@f0000d00 { 88 pci@f0000d00 {
243 #interrupt-cells = <1>;
244 #size-cells = <2>;
245 #address-cells = <3>;
246 device_type = "pci";
247 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
248 reg = <0xf0000d00 0x100>;
249 interrupt-map-mask = <0xf800 0 0 7>; 89 interrupt-map-mask = <0xf800 0 0 7>;
250 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 90 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
251 0xc000 0 0 2 &media5200_fpga 0 3 91 0xc000 0 0 2 &media5200_fpga 0 3
@@ -262,37 +102,29 @@
262 102
263 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP 103 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
264 >; 104 >;
265 clock-frequency = <0>; // From boot loader
266 interrupts = <2 8 0 2 9 0 2 10 0>;
267 interrupt-parent = <&mpc5200_pic>;
268 bus-range = <0 0>;
269 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 105 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
270 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 106 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
271 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 107 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
108 interrupt-parent = <&mpc5200_pic>;
272 }; 109 };
273 110
274 localbus { 111 localbus {
275 compatible = "fsl,mpc5200b-lpb","simple-bus";
276 #address-cells = <2>;
277 #size-cells = <1>;
278
279 ranges = < 0 0 0xfc000000 0x02000000 112 ranges = < 0 0 0xfc000000 0x02000000
280 1 0 0xfe000000 0x02000000 113 1 0 0xfe000000 0x02000000
281 2 0 0xf0010000 0x00010000 114 2 0 0xf0010000 0x00010000
282 3 0 0xf0020000 0x00010000 >; 115 3 0 0xf0020000 0x00010000 >;
283
284 flash@0,0 { 116 flash@0,0 {
285 compatible = "amd,am29lv28ml", "cfi-flash"; 117 compatible = "amd,am29lv28ml", "cfi-flash";
286 reg = <0 0x0 0x2000000>; // 32 MB 118 reg = <0 0x0 0x2000000>; // 32 MB
287 bank-width = <4>; // Width in bytes of the flash bank 119 bank-width = <4>; // Width in bytes of the flash bank
288 device-width = <2>; // Two devices on each bank 120 device-width = <2>; // Two devices on each bank
289 }; 121 };
290 122
291 flash@1,0 { 123 flash@1,0 {
292 compatible = "amd,am29lv28ml", "cfi-flash"; 124 compatible = "amd,am29lv28ml", "cfi-flash";
293 reg = <1 0 0x2000000>; // 32 MB 125 reg = <1 0 0x2000000>; // 32 MB
294 bank-width = <4>; // Width in bytes of the flash bank 126 bank-width = <4>; // Width in bytes of the flash bank
295 device-width = <2>; // Two devices on each bank 127 device-width = <2>; // Two devices on each bank
296 }; 128 };
297 129
298 media5200_fpga: fpga@2,0 { 130 media5200_fpga: fpga@2,0 {
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts
index 0ce96644176d..1360d2f69024 100644
--- a/arch/powerpc/boot/dts/mgcoge.dts
+++ b/arch/powerpc/boot/dts/mgcoge.dts
@@ -13,7 +13,7 @@
13/dts-v1/; 13/dts-v1/;
14/ { 14/ {
15 model = "MGCOGE"; 15 model = "MGCOGE";
16 compatible = "keymile,mgcoge"; 16 compatible = "keymile,km82xx";
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
@@ -48,8 +48,10 @@
48 reg = <0xf0010100 0x40>; 48 reg = <0xf0010100 0x40>;
49 49
50 ranges = <0 0 0xfe000000 0x00400000 50 ranges = <0 0 0xfe000000 0x00400000
51 5 0 0x50000000 0x20000000 51 1 0 0x30000000 0x00010000
52 >; /* Filled in by U-Boot */ 52 2 0 0x40000000 0x00010000
53 5 0 0x50000000 0x04000000
54 >;
53 55
54 flash@0,0 { 56 flash@0,0 {
55 compatible = "cfi-flash"; 57 compatible = "cfi-flash";
@@ -60,36 +62,32 @@
60 device-width = <1>; 62 device-width = <1>;
61 partition@0 { 63 partition@0 {
62 label = "u-boot"; 64 label = "u-boot";
63 reg = <0 0x40000>; 65 reg = <0x00000 0xC0000>;
64 }; 66 };
65 partition@40000 { 67 partition@1 {
66 label = "env"; 68 label = "env";
67 reg = <0x40000 0x20000>; 69 reg = <0xC0000 0x20000>;
68 }; 70 };
69 partition@60000 { 71 partition@2 {
70 label = "kernel"; 72 label = "envred";
71 reg = <0x60000 0x220000>; 73 reg = <0xE0000 0x20000>;
72 }; 74 };
73 partition@280000 { 75 partition@3 {
74 label = "dtb"; 76 label = "free";
75 reg = <0x280000 0x20000>; 77 reg = <0x100000 0x300000>;
76 }; 78 };
77 }; 79 };
78 80
79 flash@5,0 { 81 flash@5,0 {
80 compatible = "cfi-flash"; 82 compatible = "cfi-flash";
81 reg = <5 0x0 0x2000000>; 83 reg = <5 0x00000000 0x02000000
84 5 0x02000000 0x02000000>;
82 #address-cells = <1>; 85 #address-cells = <1>;
83 #size-cells = <1>; 86 #size-cells = <1>;
84 bank-width = <2>; 87 bank-width = <2>;
85 device-width = <2>; 88 partition@app { /* 64 MBytes */
86 partition@0 { 89 label = "ubi0";
87 label = "ramdisk"; 90 reg = <0x00000000 0x04000000>;
88 reg = <0 0x7a0000>;
89 };
90 partition@7a0000 {
91 label = "user";
92 reg = <0x7a0000 0x1860000>;
93 }; 91 };
94 }; 92 };
95 }; 93 };
@@ -217,6 +215,13 @@
217 }; 215 };
218 }; 216 };
219 217
218 cpm2_pio_c: gpio-controller@10d40 {
219 #gpio-cells = <2>;
220 compatible = "fsl,cpm2-pario-bank";
221 reg = <0x10d40 0x14>;
222 gpio-controller;
223 };
224
220 PIC: interrupt-controller@10c00 { 225 PIC: interrupt-controller@10c00 {
221 #interrupt-cells = <2>; 226 #interrupt-cells = <2>;
222 interrupt-controller; 227 interrupt-controller;
diff --git a/arch/powerpc/boot/dts/mgsuvd.dts b/arch/powerpc/boot/dts/mgsuvd.dts
deleted file mode 100644
index e4fc53ab42bd..000000000000
--- a/arch/powerpc/boot/dts/mgsuvd.dts
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * MGSUVD Device Tree Source
3 *
4 * Copyright 2008 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14/ {
15 model = "MGSUVD";
16 compatible = "keymile,mgsuvd";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 PowerPC,852@0 {
25 device_type = "cpu";
26 reg = <0>;
27 d-cache-line-size = <16>;
28 i-cache-line-size = <16>;
29 d-cache-size = <8192>;
30 i-cache-size = <8192>;
31 timebase-frequency = <0>; /* Filled in by u-boot */
32 bus-frequency = <0>; /* Filled in by u-boot */
33 clock-frequency = <0>; /* Filled in by u-boot */
34 interrupts = <15 2>; /* decrementer interrupt */
35 interrupt-parent = <&PIC>;
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <00000000 0x4000000>; /* Filled in by u-boot */
42 };
43
44 localbus@fff00100 {
45 compatible = "fsl,mpc852-localbus", "fsl,pq1-localbus", "simple-bus";
46 #address-cells = <2>;
47 #size-cells = <1>;
48 reg = <0xfff00100 0x40>;
49
50 ranges = <0 0 0xf0000000 0x01000000>; /* Filled in by u-boot */
51
52 flash@0,0 {
53 compatible = "cfi-flash";
54 reg = <0 0 0x1000000>;
55 #address-cells = <1>;
56 #size-cells = <1>;
57 bank-width = <1>;
58 device-width = <1>;
59 partition@0 {
60 label = "u-boot";
61 reg = <0 0x80000>;
62 };
63 partition@80000 {
64 label = "env";
65 reg = <0x80000 0x20000>;
66 };
67 partition@a0000 {
68 label = "kernel";
69 reg = <0xa0000 0x1e0000>;
70 };
71 partition@280000 {
72 label = "dtb";
73 reg = <0x280000 0x20000>;
74 };
75 partition@2a0000 {
76 label = "root";
77 reg = <0x2a0000 0x500000>;
78 };
79 partition@7a0000 {
80 label = "user";
81 reg = <0x7a0000 0x860000>;
82 };
83 };
84 };
85
86 soc@fff00000 {
87 compatible = "fsl,mpc852", "fsl,pq1-soc", "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 device_type = "soc";
91 ranges = <0 0xfff00000 0x00004000>;
92
93 PIC: interrupt-controller@0 {
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 reg = <0 24>;
97 compatible = "fsl,mpc852-pic", "fsl,pq1-pic";
98 };
99
100 cpm@9c0 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "fsl,mpc852-cpm", "fsl,cpm1", "simple-bus";
104 interrupts = <0>; /* cpm error interrupt */
105 interrupt-parent = <&CPM_PIC>;
106 reg = <0x9c0 10>;
107 ranges;
108
109 muram@2000 {
110 compatible = "fsl,cpm-muram";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 ranges = <0 0x2000 0x2000>;
114
115 data@0 {
116 compatible = "fsl,cpm-muram-data";
117 reg = <0x800 0x1800>;
118 };
119 };
120
121 brg@9f0 {
122 compatible = "fsl,mpc852-brg",
123 "fsl,cpm1-brg",
124 "fsl,cpm-brg";
125 reg = <0x9f0 0x10>;
126 clock-frequency = <0>; /* Filled in by u-boot */
127 };
128
129 CPM_PIC: interrupt-controller@930 {
130 interrupt-controller;
131 #interrupt-cells = <1>;
132 interrupts = <5 2 0 2>;
133 interrupt-parent = <&PIC>;
134 reg = <0x930 0x20>;
135 compatible = "fsl,cpm1-pic";
136 };
137
138 /* MON-1 */
139 serial@a80 {
140 device_type = "serial";
141 compatible = "fsl,cpm1-smc-uart";
142 reg = <0xa80 0x10 0x3fc0 0x40>;
143 interrupts = <4>;
144 interrupt-parent = <&CPM_PIC>;
145 fsl,cpm-brg = <1>;
146 fsl,cpm-command = <0x0090>;
147 current-speed = <0>; /* Filled in by u-boot */
148 };
149
150 ethernet@a40 {
151 device_type = "network";
152 compatible = "fsl,mpc866-scc-enet",
153 "fsl,cpm1-scc-enet";
154 reg = <0xa40 0x18 0x3e00 0x100>;
155 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by u-boot */
156 interrupts = <28>;
157 interrupt-parent = <&CPM_PIC>;
158 fsl,cpm-command = <0x80>;
159 fixed-link = <0 0 10 0 0>;
160 };
161 };
162 };
163};
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 6ca4fc144a33..0b78e89ac69b 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,219 +10,73 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "promess,motionpro"; 16 model = "promess,motionpro";
17 compatible = "promess,motionpro"; 17 compatible = "promess,motionpro";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x04000000>; // 64MB
42 };
43 18
44 soc5200@f0000000 { 19 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 20 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 21 fsl,has-wdt;
71 }; 22 };
72 23
73 timer@610 { // General Purpose Timer 24 timer@660 { // Motion-PRO status LED
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 motionpro-led@660 { // Motion-PRO status LED
104 compatible = "promess,motionpro-led"; 25 compatible = "promess,motionpro-led";
105 label = "motionpro-statusled"; 26 label = "motionpro-statusled";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 blink-delay = <100>; // 100 msec 27 blink-delay = <100>; // 100 msec
109 }; 28 };
110 29
111 motionpro-led@670 { // Motion-PRO ready LED 30 timer@670 { // Motion-PRO ready LED
112 compatible = "promess,motionpro-led"; 31 compatible = "promess,motionpro-led";
113 label = "motionpro-readyled"; 32 label = "motionpro-readyled";
114 reg = <0x670 0x10>;
115 interrupts = <1 16 0>;
116 };
117
118 rtc@800 { // Real time clock
119 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
120 reg = <0x800 0x100>;
121 interrupts = <1 5 0 1 6 0>;
122 };
123
124 can@980 {
125 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
126 interrupts = <2 18 0>;
127 reg = <0x980 0x80>;
128 }; 33 };
129 34
130 gpio_simple: gpio@b00 { 35 can@900 {
131 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 36 status = "disabled";
132 reg = <0xb00 0x40>;
133 interrupts = <1 7 0>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 }; 37 };
137 38
138 gpio_wkup: gpio@c00 { 39 psc@2000 { // PSC1
139 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 40 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
140 reg = <0xc00 0x40>;
141 interrupts = <1 8 0 0 3 0>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
146 spi@f00 {
147 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
148 reg = <0xf00 0x20>;
149 interrupts = <2 13 0 2 14 0>;
150 }; 41 };
151 42
152 usb@1000 { 43 // PSC2 in spi master mode
153 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 44 psc@2200 { // PSC2
154 reg = <0x1000 0xff>; 45 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
155 interrupts = <2 6 0>; 46 cell-index = <1>;
156 }; 47 };
157 48
158 dma-controller@1200 { 49 psc@2400 { // PSC3
159 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 50 status = "disabled";
160 reg = <0x1200 0x80>;
161 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
162 3 4 0 3 5 0 3 6 0 3 7 0
163 3 8 0 3 9 0 3 10 0 3 11 0
164 3 12 0 3 13 0 3 14 0 3 15 0>;
165 }; 51 };
166 52
167 xlb@1f00 { 53 psc@2600 { // PSC4
168 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 54 status = "disabled";
169 reg = <0x1f00 0x100>;
170 }; 55 };
171 56
172 serial@2000 { // PSC1 57 psc@2800 { // PSC5
173 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
174 reg = <0x2000 0x100>;
175 interrupts = <2 1 0>;
176 };
177
178 // PSC2 in spi master mode
179 spi@2200 { // PSC2
180 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
181 cell-index = <1>;
182 reg = <0x2200 0x100>;
183 interrupts = <2 2 0>;
184 }; 59 };
185 60
186 // PSC5 in uart mode 61 psc@2c00 { // PSC6
187 serial@2800 { // PSC5 62 status = "disabled";
188 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
189 reg = <0x2800 0x100>;
190 interrupts = <2 12 0>;
191 }; 63 };
192 64
193 ethernet@3000 { 65 ethernet@3000 {
194 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
195 reg = <0x3000 0x400>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <2 5 0>;
198 phy-handle = <&phy0>; 66 phy-handle = <&phy0>;
199 }; 67 };
200 68
201 mdio@3000 { 69 mdio@3000 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
205 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
206 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
207
208 phy0: ethernet-phy@2 { 70 phy0: ethernet-phy@2 {
209 reg = <2>; 71 reg = <2>;
210 }; 72 };
211 }; 73 };
212 74
213 ata@3a00 { 75 i2c@3d00 {
214 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 76 status = "disabled";
215 reg = <0x3a00 0x100>;
216 interrupts = <2 7 0>;
217 }; 77 };
218 78
219 i2c@3d40 { 79 i2c@3d40 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
223 reg = <0x3d40 0x40>;
224 interrupts = <2 16 0>;
225
226 rtc@68 { 80 rtc@68 {
227 compatible = "dallas,ds1339"; 81 compatible = "dallas,ds1339";
228 reg = <0x68>; 82 reg = <0x68>;
@@ -235,10 +89,11 @@
235 }; 89 };
236 }; 90 };
237 91
92 pci@f0000d00 {
93 status = "disabled";
94 };
95
238 localbus { 96 localbus {
239 compatible = "fsl,mpc5200b-lpb","simple-bus";
240 #address-cells = <2>;
241 #size-cells = <1>;
242 ranges = <0 0 0xff000000 0x01000000 97 ranges = <0 0 0xff000000 0x01000000
243 1 0 0x50000000 0x00010000 98 1 0 0x50000000 0x00010000
244 2 0 0x50010000 0x00010000 99 2 0 0x50010000 0x00010000
@@ -280,5 +135,6 @@
280 #size-cells = <1>; 135 #size-cells = <1>;
281 #address-cells = <1>; 136 #address-cells = <1>;
282 }; 137 };
138
283 }; 139 };
284}; 140};
diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
new file mode 100644
index 000000000000..bc27548e895d
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
@@ -0,0 +1,275 @@
1/*
2 * base MPC5200b Device Tree Source
3 *
4 * Copyright (C) 2010 SecretLab
5 * Grant Likely <grant@secretlab.ca>
6 * John Bonesio <bones@secretlab.ca>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "fsl,mpc5200b";
18 compatible = "fsl,mpc5200b";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 powerpc: PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory: memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44
45 soc: soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 };
72
73 timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
107 };
108
109 timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
113 };
114
115 rtc@800 { // Real time clock
116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117 reg = <0x800 0x100>;
118 interrupts = <1 5 0 1 6 0>;
119 };
120
121 can@900 {
122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
123 interrupts = <2 17 0>;
124 reg = <0x900 0x80>;
125 };
126
127 can@980 {
128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
129 interrupts = <2 18 0>;
130 reg = <0x980 0x80>;
131 };
132
133 gpio_simple: gpio@b00 {
134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
135 reg = <0xb00 0x40>;
136 interrupts = <1 7 0>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 gpio_wkup: gpio@c00 {
142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
143 reg = <0xc00 0x40>;
144 interrupts = <1 8 0 0 3 0>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 };
148
149 spi@f00 {
150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
151 reg = <0xf00 0x20>;
152 interrupts = <2 13 0 2 14 0>;
153 };
154
155 usb: usb@1000 {
156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
157 reg = <0x1000 0xff>;
158 interrupts = <2 6 0>;
159 };
160
161 dma-controller@1200 {
162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
163 reg = <0x1200 0x80>;
164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
165 3 4 0 3 5 0 3 6 0 3 7 0
166 3 8 0 3 9 0 3 10 0 3 11 0
167 3 12 0 3 13 0 3 14 0 3 15 0>;
168 };
169
170 xlb@1f00 {
171 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
172 reg = <0x1f00 0x100>;
173 };
174
175 psc1: psc@2000 { // PSC1
176 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
177 reg = <0x2000 0x100>;
178 interrupts = <2 1 0>;
179 };
180
181 psc2: psc@2200 { // PSC2
182 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
183 reg = <0x2200 0x100>;
184 interrupts = <2 2 0>;
185 };
186
187 psc3: psc@2400 { // PSC3
188 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
189 reg = <0x2400 0x100>;
190 interrupts = <2 3 0>;
191 };
192
193 psc4: psc@2600 { // PSC4
194 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
195 reg = <0x2600 0x100>;
196 interrupts = <2 11 0>;
197 };
198
199 psc5: psc@2800 { // PSC5
200 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
201 reg = <0x2800 0x100>;
202 interrupts = <2 12 0>;
203 };
204
205 psc6: psc@2c00 { // PSC6
206 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
207 reg = <0x2c00 0x100>;
208 interrupts = <2 4 0>;
209 };
210
211 eth0: ethernet@3000 {
212 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
213 reg = <0x3000 0x400>;
214 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <2 5 0>;
216 };
217
218 mdio@3000 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
222 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
224 };
225
226 ata@3a00 {
227 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
228 reg = <0x3a00 0x100>;
229 interrupts = <2 7 0>;
230 };
231
232 i2c@3d00 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
236 reg = <0x3d00 0x40>;
237 interrupts = <2 15 0>;
238 };
239
240 i2c@3d40 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
244 reg = <0x3d40 0x40>;
245 interrupts = <2 16 0>;
246 };
247
248 sram@8000 {
249 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
250 reg = <0x8000 0x4000>;
251 };
252 };
253
254 pci: pci@f0000d00 {
255 #interrupt-cells = <1>;
256 #size-cells = <2>;
257 #address-cells = <3>;
258 device_type = "pci";
259 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
260 reg = <0xf0000d00 0x100>;
261 // interrupt-map-mask = need to add
262 // interrupt-map = need to add
263 clock-frequency = <0>; // From boot loader
264 interrupts = <2 8 0 2 9 0 2 10 0>;
265 bus-range = <0 0>;
266 // ranges = need to add
267 };
268
269 localbus: localbus {
270 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
271 #address-cells = <2>;
272 #size-cells = <1>;
273 ranges = <0 0 0xfc000000 0x2000000>;
274 };
275};
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
new file mode 100644
index 000000000000..697b3f6b78bf
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -0,0 +1,340 @@
1/*
2 * mpc8308_p1m Device Tree Source
3 *
4 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 compatible = "denx,mpc8308_p1m";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8308@0 {
32 device_type = "cpu";
33 reg = <0x0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <16384>;
37 i-cache-size = <16384>;
38 timebase-frequency = <0>; // from bootloader
39 bus-frequency = <0>; // from bootloader
40 clock-frequency = <0>; // from bootloader
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x08000000>; // 128MB at 0
47 };
48
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>;
56
57 ranges = <0x0 0x0 0xfc000000 0x04000000
58 0x1 0x0 0xfbff0000 0x00008000
59 0x2 0x0 0xfbff8000 0x00008000>;
60
61 flash@0,0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
65 reg = <0x0 0x0 0x4000000>;
66 bank-width = <2>;
67 device-width = <1>;
68
69 u-boot@0 {
70 reg = <0x0 0x60000>;
71 read-only;
72 };
73 env@60000 {
74 reg = <0x60000 0x20000>;
75 };
76 env1@80000 {
77 reg = <0x80000 0x20000>;
78 };
79 kernel@a0000 {
80 reg = <0xa0000 0x200000>;
81 };
82 dtb@2a0000 {
83 reg = <0x2a0000 0x20000>;
84 };
85 ramdisk@2c0000 {
86 reg = <0x2c0000 0x640000>;
87 };
88 user@700000 {
89 reg = <0x700000 0x3900000>;
90 };
91 };
92
93 can@1,0 {
94 compatible = "nxp,sja1000";
95 reg = <0x1 0x0 0x80>;
96 interrupts = <18 0x8>;
97 interrups-parent = <&ipic>;
98 };
99
100 cpld@2,0 {
101 compatible = "denx,mpc8308_p1m-cpld";
102 reg = <0x2 0x0 0x8>;
103 interrupts = <48 0x8>;
104 interrups-parent = <&ipic>;
105 };
106 };
107
108 immr@e0000000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 device_type = "soc";
112 compatible = "fsl,mpc8308-immr", "simple-bus";
113 ranges = <0 0xe0000000 0x00100000>;
114 reg = <0xe0000000 0x00000200>;
115 bus-frequency = <0>;
116
117 i2c@3000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 compatible = "fsl-i2c";
121 reg = <0x3000 0x100>;
122 interrupts = <14 0x8>;
123 interrupt-parent = <&ipic>;
124 dfsrr;
125 fram@50 {
126 compatible = "ramtron,24c64";
127 reg = <0x50>;
128 };
129 };
130
131 i2c@3100 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 compatible = "fsl-i2c";
135 reg = <0x3100 0x100>;
136 interrupts = <15 0x8>;
137 interrupt-parent = <&ipic>;
138 dfsrr;
139 pwm@28 {
140 compatible = "maxim,ds1050";
141 reg = <0x28>;
142 };
143 sensor@48 {
144 compatible = "maxim,max6625";
145 reg = <0x48>;
146 };
147 sensor@49 {
148 compatible = "maxim,max6625";
149 reg = <0x49>;
150 };
151 sensor@4b {
152 compatible = "maxim,max6625";
153 reg = <0x4b>;
154 };
155 };
156
157 usb@23000 {
158 compatible = "fsl-usb2-dr";
159 reg = <0x23000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupt-parent = <&ipic>;
163 interrupts = <38 0x8>;
164 dr_mode = "peripheral";
165 phy_type = "ulpi";
166 };
167
168 enet0: ethernet@24000 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0x24000 0x1000>;
172
173 cell-index = <0>;
174 device_type = "network";
175 model = "eTSEC";
176 compatible = "gianfar";
177 reg = <0x24000 0x1000>;
178 local-mac-address = [ 00 00 00 00 00 00 ];
179 interrupts = <32 0x8 33 0x8 34 0x8>;
180 interrupt-parent = <&ipic>;
181 phy-handle = < &phy1 >;
182
183 mdio@520 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "fsl,gianfar-mdio";
187 reg = <0x520 0x20>;
188 phy1: ethernet-phy@1 {
189 interrupt-parent = <&ipic>;
190 interrupts = <17 0x8>;
191 reg = <0x1>;
192 device_type = "ethernet-phy";
193 };
194 phy2: ethernet-phy@2 {
195 interrupt-parent = <&ipic>;
196 interrupts = <19 0x8>;
197 reg = <0x2>;
198 device_type = "ethernet-phy";
199 };
200 tbi0: tbi-phy@11 {
201 reg = <0x11>;
202 device_type = "tbi-phy";
203 };
204 };
205 };
206
207 enet1: ethernet@25000 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 cell-index = <1>;
211 device_type = "network";
212 model = "eTSEC";
213 compatible = "gianfar";
214 reg = <0x25000 0x1000>;
215 ranges = <0x0 0x25000 0x1000>;
216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <35 0x8 36 0x8 37 0x8>;
218 interrupt-parent = <&ipic>;
219 phy-handle = < &phy2 >;
220
221 mdio@520 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,gianfar-tbi";
225 reg = <0x520 0x20>;
226 tbi1: tbi-phy@11 {
227 reg = <0x11>;
228 device_type = "tbi-phy";
229 };
230 };
231 };
232
233 serial0: serial@4500 {
234 cell-index = <0>;
235 device_type = "serial";
236 compatible = "ns16550";
237 reg = <0x4500 0x100>;
238 clock-frequency = <133333333>;
239 interrupts = <9 0x8>;
240 interrupt-parent = <&ipic>;
241 };
242
243 serial1: serial@4600 {
244 cell-index = <1>;
245 device_type = "serial";
246 compatible = "ns16550";
247 reg = <0x4600 0x100>;
248 clock-frequency = <133333333>;
249 interrupts = <10 0x8>;
250 interrupt-parent = <&ipic>;
251 };
252
253 gpio@c00 {
254 #gpio-cells = <2>;
255 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
256 reg = <0xc00 0x18>;
257 interrupts = <74 0x8>;
258 interrupt-parent = <&ipic>;
259 gpio-controller;
260 };
261
262 timer@500 {
263 compatible = "fsl,mpc8308-gtm", "fsl,gtm";
264 reg = <0x500 0x100>;
265 interrupts = <90 8 78 8 84 8 72 8>;
266 interrupt-parent = <&ipic>;
267 clock-frequency = <133333333>;
268 };
269
270 /* IPIC
271 * interrupts cell = <intr #, sense>
272 * sense values match linux IORESOURCE_IRQ_* defines:
273 * sense == 8: Level, low assertion
274 * sense == 2: Edge, high-to-low change
275 */
276 ipic: interrupt-controller@700 {
277 compatible = "fsl,ipic";
278 interrupt-controller;
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
281 reg = <0x700 0x100>;
282 device_type = "ipic";
283 };
284
285 ipic-msi@7c0 {
286 compatible = "fsl,ipic-msi";
287 reg = <0x7c0 0x40>;
288 msi-available-ranges = <0x0 0x100>;
289 interrupts = < 0x43 0x8
290 0x4 0x8
291 0x51 0x8
292 0x52 0x8
293 0x56 0x8
294 0x57 0x8
295 0x58 0x8
296 0x59 0x8 >;
297 interrupt-parent = < &ipic >;
298 };
299
300 dma@2c000 {
301 compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
302 reg = <0x2c000 0x1800>;
303 interrupts = <3 0x8
304 94 0x8>;
305 interrupt-parent = < &ipic >;
306 };
307
308 };
309
310 pci0: pcie@e0009000 {
311 #address-cells = <3>;
312 #size-cells = <2>;
313 #interrupt-cells = <1>;
314 device_type = "pci";
315 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
316 reg = <0xe0009000 0x00001000
317 0xb0000000 0x01000000>;
318 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
319 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
320 bus-range = <0 0>;
321 interrupt-map-mask = <0 0 0 0>;
322 interrupt-map = <0 0 0 0 &ipic 1 8>;
323 interrupts = <0x1 0x8>;
324 interrupt-parent = <&ipic>;
325 clock-frequency = <0>;
326
327 pcie@0 {
328 #address-cells = <3>;
329 #size-cells = <2>;
330 device_type = "pci";
331 reg = <0 0 0 0 0>;
332 ranges = <0x02000000 0 0xa0000000
333 0x02000000 0 0xa0000000
334 0 0x10000000
335 0x01000000 0 0x00000000
336 0x01000000 0 0x00000000
337 0 0x00800000>;
338 };
339 };
340};
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
index a97eb2db5a18..a0bd1881081e 100644
--- a/arch/powerpc/boot/dts/mpc8308rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -109,7 +109,7 @@
109 #address-cells = <1>; 109 #address-cells = <1>;
110 #size-cells = <1>; 110 #size-cells = <1>;
111 device_type = "soc"; 111 device_type = "soc";
112 compatible = "fsl,mpc8315-immr", "simple-bus"; 112 compatible = "fsl,mpc8308-immr", "simple-bus";
113 ranges = <0 0xe0000000 0x00100000>; 113 ranges = <0 0xe0000000 0x00100000>;
114 reg = <0xe0000000 0x00000200>; 114 reg = <0xe0000000 0x00000200>;
115 bus-frequency = <0>; 115 bus-frequency = <0>;
@@ -265,6 +265,14 @@
265 interrupt-parent = < &ipic >; 265 interrupt-parent = < &ipic >;
266 }; 266 };
267 267
268 dma@2c000 {
269 compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
270 reg = <0x2c000 0x1800>;
271 interrupts = <3 0x8
272 94 0x8>;
273 interrupt-parent = < &ipic >;
274 };
275
268 }; 276 };
269 277
270 pci0: pcie@e0009000 { 278 pci0: pcie@e0009000 {
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 761faa7b6964..ac1eb320c7b4 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -176,6 +176,19 @@
176 sleep = <&pmc 0x00300000>; 176 sleep = <&pmc 0x00300000>;
177 }; 177 };
178 178
179 ptp_clock@24E00 {
180 compatible = "fsl,etsec-ptp";
181 reg = <0x24E00 0xB0>;
182 interrupts = <12 0x8 13 0x8>;
183 interrupt-parent = < &ipic >;
184 fsl,tclk-period = <10>;
185 fsl,tmr-prsc = <100>;
186 fsl,tmr-add = <0x999999A4>;
187 fsl,tmr-fiper1 = <0x3B9AC9F6>;
188 fsl,tmr-fiper2 = <0x00018696>;
189 fsl,max-adj = <659999998>;
190 };
191
179 enet0: ethernet@24000 { 192 enet0: ethernet@24000 {
180 #address-cells = <1>; 193 #address-cells = <1>;
181 #size-cells = <1>; 194 #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index 815cebb2e3e5..a75c10eed269 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -108,6 +108,58 @@
108 }; 108 };
109 }; 109 };
110 110
111 spi@7000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "fsl,mpc8536-espi";
115 reg = <0x7000 0x1000>;
116 interrupts = <59 0x2>;
117 interrupt-parent = <&mpic>;
118 fsl,espi-num-chipselects = <4>;
119
120 flash@0 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "spansion,s25sl12801";
124 reg = <0>;
125 spi-max-frequency = <40000000>;
126 partition@u-boot {
127 label = "u-boot";
128 reg = <0x00000000 0x00100000>;
129 read-only;
130 };
131 partition@kernel {
132 label = "kernel";
133 reg = <0x00100000 0x00500000>;
134 read-only;
135 };
136 partition@dtb {
137 label = "dtb";
138 reg = <0x00600000 0x00100000>;
139 read-only;
140 };
141 partition@fs {
142 label = "file system";
143 reg = <0x00700000 0x00900000>;
144 };
145 };
146 flash@1 {
147 compatible = "spansion,s25sl12801";
148 reg = <1>;
149 spi-max-frequency = <40000000>;
150 };
151 flash@2 {
152 compatible = "spansion,s25sl12801";
153 reg = <2>;
154 spi-max-frequency = <40000000>;
155 };
156 flash@3 {
157 compatible = "spansion,s25sl12801";
158 reg = <3>;
159 spi-max-frequency = <40000000>;
160 };
161 };
162
111 dma@21300 { 163 dma@21300 {
112 #address-cells = <1>; 164 #address-cells = <1>;
113 #size-cells = <1>; 165 #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc1285c140..f6c04d25e916 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
324 }; 324 };
325 }; 325 };
326 326
327 ptp_clock@24E00 {
328 compatible = "fsl,etsec-ptp";
329 reg = <0x24E00 0xB0>;
330 interrupts = <68 2 69 2 70 2 71 2>;
331 interrupt-parent = < &mpic >;
332 fsl,tclk-period = <5>;
333 fsl,tmr-prsc = <200>;
334 fsl,tmr-add = <0xAAAAAAAB>;
335 fsl,tmr-fiper1 = <0x3B9AC9FB>;
336 fsl,tmr-fiper2 = <0x3B9AC9FB>;
337 fsl,max-adj = <499999999>;
338 };
339
327 enet0: ethernet@24000 { 340 enet0: ethernet@24000 {
328 #address-cells = <1>; 341 #address-cells = <1>;
329 #size-cells = <1>; 342 #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 9535ce68caae..83c3218cb4da 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -286,6 +286,7 @@
286 286
287 ssi@16100 { 287 ssi@16100 {
288 compatible = "fsl,mpc8610-ssi"; 288 compatible = "fsl,mpc8610-ssi";
289 status = "disabled";
289 cell-index = <1>; 290 cell-index = <1>;
290 reg = <0x16100 0x100>; 291 reg = <0x16100 0x100>;
291 interrupt-parent = <&mpic>; 292 interrupt-parent = <&mpic>;
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
index b72a7581d798..21d34720fcc9 100644
--- a/arch/powerpc/boot/dts/mucmc52.dts
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -11,172 +11,109 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "manroland,mucmc52"; 17 model = "manroland,mucmc52";
18 compatible = "manroland,mucmc52"; 18 compatible = "manroland,mucmc52";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44 19
45 soc5200@f0000000 { 20 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // GPT 0 in GPIO mode 21 gpt0: timer@600 { // GPT 0 in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller; 22 gpio-controller;
72 #gpio-cells = <2>; 23 #gpio-cells = <2>;
73 }; 24 };
74 25
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode 26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller; 27 gpio-controller;
80 #gpio-cells = <2>; 28 #gpio-cells = <2>;
81 }; 29 };
82 30
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode 31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller; 32 gpio-controller;
88 #gpio-cells = <2>; 33 #gpio-cells = <2>;
89 }; 34 };
90 35
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode 36 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x630 0x10>;
94 interrupts = <1 12 0>;
95 gpio-controller; 37 gpio-controller;
96 #gpio-cells = <2>; 38 #gpio-cells = <2>;
97 }; 39 };
98 40
99 gpio_simple: gpio@b00 { 41 timer@640 {
100 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 42 status = "disabled";
101 reg = <0xb00 0x40>;
102 interrupts = <1 7 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 }; 43 };
106 44
107 gpio_wkup: gpio@c00 { 45 timer@650 {
108 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 46 status = "disabled";
109 reg = <0xc00 0x40>; 47 };
110 interrupts = <1 8 0 0 3 0>; 48
111 gpio-controller; 49 timer@660 {
112 #gpio-cells = <2>; 50 status = "disabled";
51 };
52
53 timer@670 {
54 status = "disabled";
113 }; 55 };
114 56
115 dma-controller@1200 { 57 rtc@800 {
116 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 58 status = "disabled";
117 reg = <0x1200 0x80>;
118 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
119 3 4 0 3 5 0 3 6 0 3 7 0
120 3 8 0 3 9 0 3 10 0 3 11 0
121 3 12 0 3 13 0 3 14 0 3 15 0>;
122 }; 59 };
123 60
124 xlb@1f00 { 61 can@900 {
125 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 62 status = "disabled";
126 reg = <0x1f00 0x100>;
127 }; 63 };
128 64
129 serial@2000 { /* PSC1 in UART mode */ 65 can@980 {
66 status = "disabled";
67 };
68
69 spi@f00 {
70 status = "disabled";
71 };
72
73 usb@1000 {
74 status = "disabled";
75 };
76
77 psc@2000 { // PSC1
130 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 78 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
131 reg = <0x2000 0x100>;
132 interrupts = <2 1 0>;
133 }; 79 };
134 80
135 serial@2200 { /* PSC2 in UART mode */ 81 psc@2200 { // PSC2
136 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 82 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
137 reg = <0x2200 0x100>;
138 interrupts = <2 2 0>;
139 }; 83 };
140 84
141 serial@2c00 { /* PSC6 in UART mode */ 85 psc@2400 { // PSC3
86 status = "disabled";
87 };
88
89 psc@2600 { // PSC4
90 status = "disabled";
91 };
92
93 psc@2800 { // PSC5
94 status = "disabled";
95 };
96
97 psc@2c00 { // PSC6
142 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 98 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
143 reg = <0x2c00 0x100>;
144 interrupts = <2 4 0>;
145 }; 99 };
146 100
147 ethernet@3000 { 101 ethernet@3000 {
148 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
149 reg = <0x3000 0x400>;
150 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <2 5 0>;
152 phy-handle = <&phy0>; 102 phy-handle = <&phy0>;
153 }; 103 };
154 104
155 mdio@3000 { 105 mdio@3000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
159 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
160 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
161
162 phy0: ethernet-phy@0 { 106 phy0: ethernet-phy@0 {
163 compatible = "intel,lxt971"; 107 compatible = "intel,lxt971";
164 reg = <0>; 108 reg = <0>;
165 }; 109 };
166 }; 110 };
167 111
168 ata@3a00 { 112 i2c@3d00 {
169 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 113 status = "disabled";
170 reg = <0x3a00 0x100>;
171 interrupts = <2 7 0>;
172 }; 114 };
173 115
174 i2c@3d40 { 116 i2c@3d40 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>;
180 hwmon@2c { 117 hwmon@2c {
181 compatible = "ad,adm9240"; 118 compatible = "ad,adm9240";
182 reg = <0x2c>; 119 reg = <0x2c>;
@@ -186,20 +123,9 @@
186 reg = <0x51>; 123 reg = <0x51>;
187 }; 124 };
188 }; 125 };
189
190 sram@8000 {
191 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
192 reg = <0x8000 0x4000>;
193 };
194 }; 126 };
195 127
196 pci@f0000d00 { 128 pci@f0000d00 {
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 device_type = "pci";
201 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
202 reg = <0xf0000d00 0x100>;
203 interrupt-map-mask = <0xf800 0 0 7>; 129 interrupt-map-mask = <0xf800 0 0 7>;
204 interrupt-map = < 130 interrupt-map = <
205 /* IDSEL 0x10 */ 131 /* IDSEL 0x10 */
@@ -208,20 +134,12 @@
208 0x8000 0 0 3 &mpc5200_pic 0 2 3 134 0x8000 0 0 3 &mpc5200_pic 0 2 3
209 0x8000 0 0 4 &mpc5200_pic 0 1 3 135 0x8000 0 0 4 &mpc5200_pic 0 1 3
210 >; 136 >;
211 clock-frequency = <0>; // From boot loader
212 interrupts = <2 8 0 2 9 0 2 10 0>;
213 bus-range = <0 0>;
214 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000 137 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
215 0x02000000 0 0x90000000 0x90000000 0 0x10000000 138 0x02000000 0 0x90000000 0x90000000 0 0x10000000
216 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 139 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
217 }; 140 };
218 141
219 localbus { 142 localbus {
220 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
221
222 #address-cells = <2>;
223 #size-cells = <1>;
224
225 ranges = <0 0 0xff800000 0x00800000 143 ranges = <0 0 0xff800000 0x00800000
226 1 0 0x80000000 0x00800000 144 1 0 0x80000000 0x00800000
227 3 0 0x80000000 0x00800000>; 145 3 0 0x80000000 0x00800000>;
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index 22f64b62d7f6..d6a8ae458137 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P1020 RDB Device Tree Source 2 * P1020 RDB Device Tree Source
3 * 3 *
4 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p1020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P1020"; 15 model = "fsl,P1020RDB";
15 compatible = "fsl,P1020RDB"; 16 compatible = "fsl,P1020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 serial0 = &serial0; 19 serial0 = &serial0;
@@ -26,34 +25,11 @@
26 pci1 = &pci1; 25 pci1 = &pci1;
27 }; 26 };
28 27
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory { 28 memory {
47 device_type = "memory"; 29 device_type = "memory";
48 }; 30 };
49 31
50 localbus@ffe05000 { 32 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57 33
58 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 34 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,88 +141,14 @@
165 }; 141 };
166 142
167 soc@ffe00000 { 143 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p1020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p1020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <16 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p1020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <16 2>;
193 };
194
195 i2c@3000 { 144 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 { 145 rtc@68 {
205 compatible = "dallas,ds1339"; 146 compatible = "dallas,ds1339";
206 reg = <0x68>; 147 reg = <0x68>;
207 }; 148 };
208 }; 149 };
209 150
210 i2c@3100 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240
241 spi@7000 { 151 spi@7000 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250 152
251 fsl_m25p80@0 { 153 fsl_m25p80@0 {
252 #address-cells = <1>; 154 #address-cells = <1>;
@@ -294,66 +196,7 @@
294 }; 196 };
295 }; 197 };
296 198
297 gpio: gpio-controller@f000 {
298 #gpio-cells = <2>;
299 compatible = "fsl,mpc8572-gpio";
300 reg = <0xf000 0x100>;
301 interrupts = <47 0x2>;
302 interrupt-parent = <&mpic>;
303 gpio-controller;
304 };
305
306 L2: l2-cache-controller@20000 {
307 compatible = "fsl,p1020-l2-cache-controller";
308 reg = <0x20000 0x1000>;
309 cache-line-size = <32>; // 32 bytes
310 cache-size = <0x40000>; // L2,256K
311 interrupt-parent = <&mpic>;
312 interrupts = <16 2>;
313 };
314
315 dma@21300 {
316 #address-cells = <1>;
317 #size-cells = <1>;
318 compatible = "fsl,eloplus-dma";
319 reg = <0x21300 0x4>;
320 ranges = <0x0 0x21100 0x200>;
321 cell-index = <0>;
322 dma-channel@0 {
323 compatible = "fsl,eloplus-dma-channel";
324 reg = <0x0 0x80>;
325 cell-index = <0>;
326 interrupt-parent = <&mpic>;
327 interrupts = <20 2>;
328 };
329 dma-channel@80 {
330 compatible = "fsl,eloplus-dma-channel";
331 reg = <0x80 0x80>;
332 cell-index = <1>;
333 interrupt-parent = <&mpic>;
334 interrupts = <21 2>;
335 };
336 dma-channel@100 {
337 compatible = "fsl,eloplus-dma-channel";
338 reg = <0x100 0x80>;
339 cell-index = <2>;
340 interrupt-parent = <&mpic>;
341 interrupts = <22 2>;
342 };
343 dma-channel@180 {
344 compatible = "fsl,eloplus-dma-channel";
345 reg = <0x180 0x80>;
346 cell-index = <3>;
347 interrupt-parent = <&mpic>;
348 interrupts = <23 2>;
349 };
350 };
351
352 mdio@24000 { 199 mdio@24000 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 compatible = "fsl,etsec2-mdio";
356 reg = <0x24000 0x1000 0xb0030 0x4>;
357 200
358 phy0: ethernet-phy@0 { 201 phy0: ethernet-phy@0 {
359 interrupt-parent = <&mpic>; 202 interrupt-parent = <&mpic>;
@@ -369,10 +212,6 @@
369 }; 212 };
370 213
371 mdio@25000 { 214 mdio@25000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "fsl,etsec2-tbi";
375 reg = <0x25000 0x1000 0xb1030 0x4>;
376 215
377 tbi0: tbi-phy@11 { 216 tbi0: tbi-phy@11 {
378 reg = <0x11>; 217 reg = <0x11>;
@@ -381,97 +220,25 @@
381 }; 220 };
382 221
383 enet0: ethernet@b0000 { 222 enet0: ethernet@b0000 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 device_type = "network";
387 model = "eTSEC";
388 compatible = "fsl,etsec2";
389 fsl,num_rx_queues = <0x8>;
390 fsl,num_tx_queues = <0x8>;
391 local-mac-address = [ 00 00 00 00 00 00 ];
392 interrupt-parent = <&mpic>;
393 fixed-link = <1 1 1000 0 0>; 223 fixed-link = <1 1 1000 0 0>;
394 phy-connection-type = "rgmii-id"; 224 phy-connection-type = "rgmii-id";
395 225
396 queue-group@0 {
397 #address-cells = <1>;
398 #size-cells = <1>;
399 reg = <0xb0000 0x1000>;
400 interrupts = <29 2 30 2 34 2>;
401 };
402
403 queue-group@1 {
404 #address-cells = <1>;
405 #size-cells = <1>;
406 reg = <0xb4000 0x1000>;
407 interrupts = <17 2 18 2 24 2>;
408 };
409 }; 226 };
410 227
411 enet1: ethernet@b1000 { 228 enet1: ethernet@b1000 {
412 #address-cells = <1>;
413 #size-cells = <1>;
414 device_type = "network";
415 model = "eTSEC";
416 compatible = "fsl,etsec2";
417 fsl,num_rx_queues = <0x8>;
418 fsl,num_tx_queues = <0x8>;
419 local-mac-address = [ 00 00 00 00 00 00 ];
420 interrupt-parent = <&mpic>;
421 phy-handle = <&phy0>; 229 phy-handle = <&phy0>;
422 tbi-handle = <&tbi0>; 230 tbi-handle = <&tbi0>;
423 phy-connection-type = "sgmii"; 231 phy-connection-type = "sgmii";
424 232
425 queue-group@0 {
426 #address-cells = <1>;
427 #size-cells = <1>;
428 reg = <0xb1000 0x1000>;
429 interrupts = <35 2 36 2 40 2>;
430 };
431
432 queue-group@1 {
433 #address-cells = <1>;
434 #size-cells = <1>;
435 reg = <0xb5000 0x1000>;
436 interrupts = <51 2 52 2 67 2>;
437 };
438 }; 233 };
439 234
440 enet2: ethernet@b2000 { 235 enet2: ethernet@b2000 {
441 #address-cells = <1>;
442 #size-cells = <1>;
443 device_type = "network";
444 model = "eTSEC";
445 compatible = "fsl,etsec2";
446 fsl,num_rx_queues = <0x8>;
447 fsl,num_tx_queues = <0x8>;
448 local-mac-address = [ 00 00 00 00 00 00 ];
449 interrupt-parent = <&mpic>;
450 phy-handle = <&phy1>; 236 phy-handle = <&phy1>;
451 phy-connection-type = "rgmii-id"; 237 phy-connection-type = "rgmii-id";
452 238
453 queue-group@0 {
454 #address-cells = <1>;
455 #size-cells = <1>;
456 reg = <0xb2000 0x1000>;
457 interrupts = <31 2 32 2 33 2>;
458 };
459
460 queue-group@1 {
461 #address-cells = <1>;
462 #size-cells = <1>;
463 reg = <0xb6000 0x1000>;
464 interrupts = <25 2 26 2 27 2>;
465 };
466 }; 239 };
467 240
468 usb@22000 { 241 usb@22000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "fsl-usb2-dr";
472 reg = <0x22000 0x1000>;
473 interrupt-parent = <&mpic>;
474 interrupts = <28 0x2>;
475 phy_type = "ulpi"; 242 phy_type = "ulpi";
476 }; 243 };
477 244
@@ -481,82 +248,23 @@
481 it enables USB2. OTOH, U-Boot does create a new node 248 it enables USB2. OTOH, U-Boot does create a new node
482 when there isn't any. So, just comment it out. 249 when there isn't any. So, just comment it out.
483 usb@23000 { 250 usb@23000 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl-usb2-dr";
487 reg = <0x23000 0x1000>;
488 interrupt-parent = <&mpic>;
489 interrupts = <46 0x2>;
490 phy_type = "ulpi"; 251 phy_type = "ulpi";
491 }; 252 };
492 */ 253 */
493 254
494 sdhci@2e000 {
495 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
496 reg = <0x2e000 0x1000>;
497 interrupts = <72 0x2>;
498 interrupt-parent = <&mpic>;
499 /* Filled in by U-Boot */
500 clock-frequency = <0>;
501 };
502
503 crypto@30000 {
504 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
505 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
506 reg = <0x30000 0x10000>;
507 interrupts = <45 2 58 2>;
508 interrupt-parent = <&mpic>;
509 fsl,num-channels = <4>;
510 fsl,channel-fifo-len = <24>;
511 fsl,exec-units-mask = <0xbfe>;
512 fsl,descriptor-types-mask = <0x3ab0ebf>;
513 };
514
515 mpic: pic@40000 {
516 interrupt-controller;
517 #address-cells = <0>;
518 #interrupt-cells = <2>;
519 reg = <0x40000 0x40000>;
520 compatible = "chrp,open-pic";
521 device_type = "open-pic";
522 };
523
524 msi@41600 {
525 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
526 reg = <0x41600 0x80>;
527 msi-available-ranges = <0 0x100>;
528 interrupts = <
529 0xe0 0
530 0xe1 0
531 0xe2 0
532 0xe3 0
533 0xe4 0
534 0xe5 0
535 0xe6 0
536 0xe7 0>;
537 interrupt-parent = <&mpic>;
538 };
539
540 global-utilities@e0000 { //global utilities block
541 compatible = "fsl,p1020-guts";
542 reg = <0xe0000 0x1000>;
543 fsl,has-rstcr;
544 };
545 }; 255 };
546 256
547 pci0: pcie@ffe09000 { 257 pci0: pcie@ffe09000 {
548 compatible = "fsl,mpc8548-pcie";
549 device_type = "pci";
550 #interrupt-cells = <1>;
551 #size-cells = <2>;
552 #address-cells = <3>;
553 reg = <0 0xffe09000 0 0x1000>;
554 bus-range = <0 255>;
555 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 258 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
556 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 259 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
557 clock-frequency = <33333333>; 260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
558 interrupt-parent = <&mpic>; 261 interrupt-map = <
559 interrupts = <16 2>; 262 /* IDSEL 0x0 */
263 0000 0x0 0x0 0x1 &mpic 0x4 0x1
264 0000 0x0 0x0 0x2 &mpic 0x5 0x1
265 0000 0x0 0x0 0x3 &mpic 0x6 0x1
266 0000 0x0 0x0 0x4 &mpic 0x7 0x1
267 >;
560 pcie@0 { 268 pcie@0 {
561 reg = <0x0 0x0 0x0 0x0 0x0>; 269 reg = <0x0 0x0 0x0 0x0 0x0>;
562 #size-cells = <2>; 270 #size-cells = <2>;
@@ -573,25 +281,23 @@
573 }; 281 };
574 282
575 pci1: pcie@ffe0a000 { 283 pci1: pcie@ffe0a000 {
576 compatible = "fsl,mpc8548-pcie"; 284 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
577 device_type = "pci"; 285 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
578 #interrupt-cells = <1>; 286 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
579 #size-cells = <2>; 287 interrupt-map = <
580 #address-cells = <3>; 288 /* IDSEL 0x0 */
581 reg = <0 0xffe0a000 0 0x1000>; 289 0000 0x0 0x0 0x1 &mpic 0x0 0x1
582 bus-range = <0 255>; 290 0000 0x0 0x0 0x2 &mpic 0x1 0x1
583 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 291 0000 0x0 0x0 0x3 &mpic 0x2 0x1
584 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 292 0000 0x0 0x0 0x4 &mpic 0x3 0x1
585 clock-frequency = <33333333>; 293 >;
586 interrupt-parent = <&mpic>;
587 interrupts = <16 2>;
588 pcie@0 { 294 pcie@0 {
589 reg = <0x0 0x0 0x0 0x0 0x0>; 295 reg = <0x0 0x0 0x0 0x0 0x0>;
590 #size-cells = <2>; 296 #size-cells = <2>;
591 #address-cells = <3>; 297 #address-cells = <3>;
592 device_type = "pci"; 298 device_type = "pci";
593 ranges = <0x2000000 0x0 0xc0000000 299 ranges = <0x2000000 0x0 0x80000000
594 0x2000000 0x0 0xc0000000 300 0x2000000 0x0 0x80000000
595 0x0 0x20000000 301 0x0 0x20000000
596 302
597 0x1000000 0x0 0x0 303 0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
new file mode 100644
index 000000000000..f0bf7f42f097
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -0,0 +1,213 @@
1/*
2 * P1020 RDB Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
7 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
8 *
9 * Please note to add "-b 0" for core0's dts compiling.
10 *
11 * Copyright 2011 Freescale Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19/include/ "p1020si.dtsi"
20
21/ {
22 model = "fsl,P1020RDB";
23 compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
24
25 aliases {
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 serial0 = &serial0;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 PowerPC,P1020@1 {
35 status = "disabled";
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 };
42
43 localbus@ffe05000 {
44 status = "disabled";
45 };
46
47 soc@ffe00000 {
48 i2c@3000 {
49 rtc@68 {
50 compatible = "dallas,ds1339";
51 reg = <0x68>;
52 };
53 };
54
55 serial1: serial@4600 {
56 status = "disabled";
57 };
58
59 spi@7000 {
60 fsl_m25p80@0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,espi-flash";
64 reg = <0>;
65 linux,modalias = "fsl_m25p80";
66 spi-max-frequency = <40000000>;
67
68 partition@0 {
69 /* 512KB for u-boot Bootloader Image */
70 reg = <0x0 0x00080000>;
71 label = "SPI (RO) U-Boot Image";
72 read-only;
73 };
74
75 partition@80000 {
76 /* 512KB for DTB Image */
77 reg = <0x00080000 0x00080000>;
78 label = "SPI (RO) DTB Image";
79 read-only;
80 };
81
82 partition@100000 {
83 /* 4MB for Linux Kernel Image */
84 reg = <0x00100000 0x00400000>;
85 label = "SPI (RO) Linux Kernel Image";
86 read-only;
87 };
88
89 partition@500000 {
90 /* 4MB for Compressed RFS Image */
91 reg = <0x00500000 0x00400000>;
92 label = "SPI (RO) Compressed RFS Image";
93 read-only;
94 };
95
96 partition@900000 {
97 /* 7MB for JFFS2 based RFS */
98 reg = <0x00900000 0x00700000>;
99 label = "SPI (RW) JFFS2 RFS";
100 };
101 };
102 };
103
104 mdio@24000 {
105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>;
107 interrupts = <3 1>;
108 reg = <0x0>;
109 };
110 phy1: ethernet-phy@1 {
111 interrupt-parent = <&mpic>;
112 interrupts = <2 1>;
113 reg = <0x1>;
114 };
115 };
116
117 mdio@25000 {
118 tbi0: tbi-phy@11 {
119 reg = <0x11>;
120 device_type = "tbi-phy";
121 };
122 };
123
124 enet0: ethernet@b0000 {
125 status = "disabled";
126 };
127
128 enet1: ethernet@b1000 {
129 phy-handle = <&phy0>;
130 tbi-handle = <&tbi0>;
131 phy-connection-type = "sgmii";
132 };
133
134 enet2: ethernet@b2000 {
135 phy-handle = <&phy1>;
136 phy-connection-type = "rgmii-id";
137 };
138
139 usb@22000 {
140 phy_type = "ulpi";
141 };
142
143 /* USB2 is shared with localbus, so it must be disabled
144 by default. We can't put 'status = "disabled";' here
145 since U-Boot doesn't clear the status property when
146 it enables USB2. OTOH, U-Boot does create a new node
147 when there isn't any. So, just comment it out.
148 usb@23000 {
149 phy_type = "ulpi";
150 };
151 */
152
153 mpic: pic@40000 {
154 protected-sources = <
155 42 29 30 34 /* serial1, enet0-queue-group0 */
156 17 18 24 45 /* enet0-queue-group1, crypto */
157 >;
158 };
159
160 };
161
162 pci0: pcie@ffe09000 {
163 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
164 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
165 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
166 interrupt-map = <
167 /* IDSEL 0x0 */
168 0000 0x0 0x0 0x1 &mpic 0x4 0x1
169 0000 0x0 0x0 0x2 &mpic 0x5 0x1
170 0000 0x0 0x0 0x3 &mpic 0x6 0x1
171 0000 0x0 0x0 0x4 &mpic 0x7 0x1
172 >;
173 pcie@0 {
174 reg = <0x0 0x0 0x0 0x0 0x0>;
175 #size-cells = <2>;
176 #address-cells = <3>;
177 device_type = "pci";
178 ranges = <0x2000000 0x0 0xa0000000
179 0x2000000 0x0 0xa0000000
180 0x0 0x20000000
181
182 0x1000000 0x0 0x0
183 0x1000000 0x0 0x0
184 0x0 0x100000>;
185 };
186 };
187
188 pci1: pcie@ffe0a000 {
189 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
190 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
191 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
192 interrupt-map = <
193 /* IDSEL 0x0 */
194 0000 0x0 0x0 0x1 &mpic 0x0 0x1
195 0000 0x0 0x0 0x2 &mpic 0x1 0x1
196 0000 0x0 0x0 0x3 &mpic 0x2 0x1
197 0000 0x0 0x0 0x4 &mpic 0x3 0x1
198 >;
199 pcie@0 {
200 reg = <0x0 0x0 0x0 0x0 0x0>;
201 #size-cells = <2>;
202 #address-cells = <3>;
203 device_type = "pci";
204 ranges = <0x2000000 0x0 0x80000000
205 0x2000000 0x0 0x80000000
206 0x0 0x20000000
207
208 0x1000000 0x0 0x0
209 0x1000000 0x0 0x0
210 0x0 0x100000>;
211 };
212 };
213};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
new file mode 100644
index 000000000000..6ec02204a44e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
@@ -0,0 +1,148 @@
1/*
2 * P1020 RDB Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, eth0, crypto.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2011 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/include/ "p1020si.dtsi"
19
20/ {
21 model = "fsl,P1020RDB";
22 compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 };
28
29 cpus {
30 PowerPC,P1020@0 {
31 status = "disabled";
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 };
38
39 localbus@ffe05000 {
40 status = "disabled";
41 };
42
43 soc@ffe00000 {
44 ecm-law@0 {
45 status = "disabled";
46 };
47
48 ecm@1000 {
49 status = "disabled";
50 };
51
52 memory-controller@2000 {
53 status = "disabled";
54 };
55
56 i2c@3000 {
57 status = "disabled";
58 };
59
60 i2c@3100 {
61 status = "disabled";
62 };
63
64 serial0: serial@4500 {
65 status = "disabled";
66 };
67
68 spi@7000 {
69 status = "disabled";
70 };
71
72 gpio: gpio-controller@f000 {
73 status = "disabled";
74 };
75
76 dma@21300 {
77 status = "disabled";
78 };
79
80 mdio@24000 {
81 status = "disabled";
82 };
83
84 mdio@25000 {
85 status = "disabled";
86 };
87
88 enet0: ethernet@b0000 {
89 fixed-link = <1 1 1000 0 0>;
90 phy-connection-type = "rgmii-id";
91
92 };
93
94 enet1: ethernet@b1000 {
95 status = "disabled";
96 };
97
98 enet2: ethernet@b2000 {
99 status = "disabled";
100 };
101
102 usb@22000 {
103 status = "disabled";
104 };
105
106 sdhci@2e000 {
107 status = "disabled";
108 };
109
110 mpic: pic@40000 {
111 protected-sources = <
112 16 /* ecm, mem, L2, pci0, pci1 */
113 43 42 59 /* i2c, serial0, spi */
114 47 63 62 /* gpio, tdm */
115 20 21 22 23 /* dma */
116 03 02 /* mdio */
117 35 36 40 /* enet1-queue-group0 */
118 51 52 67 /* enet1-queue-group1 */
119 31 32 33 /* enet2-queue-group0 */
120 25 26 27 /* enet2-queue-group1 */
121 28 72 58 /* usb, sdhci, crypto */
122 0xb0 0xb1 0xb2 /* message */
123 0xb3 0xb4 0xb5
124 0xb6 0xb7
125 0xe0 0xe1 0xe2 /* msi */
126 0xe3 0xe4 0xe5
127 0xe6 0xe7 /* sdhci, crypto , pci */
128 >;
129 };
130
131 msi@41600 {
132 status = "disabled";
133 };
134
135 global-utilities@e0000 { //global utilities block
136 status = "disabled";
137 };
138
139 };
140
141 pci0: pcie@ffe09000 {
142 status = "disabled";
143 };
144
145 pci1: pcie@ffe0a000 {
146 status = "disabled";
147 };
148};
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
new file mode 100644
index 000000000000..5c5acb66c3fc
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -0,0 +1,377 @@
1/*
2 * P1020si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P1020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p1020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p1020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <16 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p1020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <16 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 gpio: gpio-controller@f000 {
126 #gpio-cells = <2>;
127 compatible = "fsl,mpc8572-gpio";
128 reg = <0xf000 0x100>;
129 interrupts = <47 0x2>;
130 interrupt-parent = <&mpic>;
131 gpio-controller;
132 };
133
134 L2: l2-cache-controller@20000 {
135 compatible = "fsl,p1020-l2-cache-controller";
136 reg = <0x20000 0x1000>;
137 cache-line-size = <32>; // 32 bytes
138 cache-size = <0x40000>; // L2,256K
139 interrupt-parent = <&mpic>;
140 interrupts = <16 2>;
141 };
142
143 dma@21300 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "fsl,eloplus-dma";
147 reg = <0x21300 0x4>;
148 ranges = <0x0 0x21100 0x200>;
149 cell-index = <0>;
150 dma-channel@0 {
151 compatible = "fsl,eloplus-dma-channel";
152 reg = <0x0 0x80>;
153 cell-index = <0>;
154 interrupt-parent = <&mpic>;
155 interrupts = <20 2>;
156 };
157 dma-channel@80 {
158 compatible = "fsl,eloplus-dma-channel";
159 reg = <0x80 0x80>;
160 cell-index = <1>;
161 interrupt-parent = <&mpic>;
162 interrupts = <21 2>;
163 };
164 dma-channel@100 {
165 compatible = "fsl,eloplus-dma-channel";
166 reg = <0x100 0x80>;
167 cell-index = <2>;
168 interrupt-parent = <&mpic>;
169 interrupts = <22 2>;
170 };
171 dma-channel@180 {
172 compatible = "fsl,eloplus-dma-channel";
173 reg = <0x180 0x80>;
174 cell-index = <3>;
175 interrupt-parent = <&mpic>;
176 interrupts = <23 2>;
177 };
178 };
179
180 mdio@24000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,etsec2-mdio";
184 reg = <0x24000 0x1000 0xb0030 0x4>;
185
186 };
187
188 mdio@25000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,etsec2-tbi";
192 reg = <0x25000 0x1000 0xb1030 0x4>;
193
194 };
195
196 enet0: ethernet@b0000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 device_type = "network";
200 model = "eTSEC";
201 compatible = "fsl,etsec2";
202 fsl,num_rx_queues = <0x8>;
203 fsl,num_tx_queues = <0x8>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupt-parent = <&mpic>;
206
207 queue-group@0 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 reg = <0xb0000 0x1000>;
211 interrupts = <29 2 30 2 34 2>;
212 };
213
214 queue-group@1 {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 reg = <0xb4000 0x1000>;
218 interrupts = <17 2 18 2 24 2>;
219 };
220 };
221
222 enet1: ethernet@b1000 {
223 #address-cells = <1>;
224 #size-cells = <1>;
225 device_type = "network";
226 model = "eTSEC";
227 compatible = "fsl,etsec2";
228 fsl,num_rx_queues = <0x8>;
229 fsl,num_tx_queues = <0x8>;
230 local-mac-address = [ 00 00 00 00 00 00 ];
231 interrupt-parent = <&mpic>;
232
233 queue-group@0 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 reg = <0xb1000 0x1000>;
237 interrupts = <35 2 36 2 40 2>;
238 };
239
240 queue-group@1 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 reg = <0xb5000 0x1000>;
244 interrupts = <51 2 52 2 67 2>;
245 };
246 };
247
248 enet2: ethernet@b2000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "fsl,etsec2";
254 fsl,num_rx_queues = <0x8>;
255 fsl,num_tx_queues = <0x8>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupt-parent = <&mpic>;
258
259 queue-group@0 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 reg = <0xb2000 0x1000>;
263 interrupts = <31 2 32 2 33 2>;
264 };
265
266 queue-group@1 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 reg = <0xb6000 0x1000>;
270 interrupts = <25 2 26 2 27 2>;
271 };
272 };
273
274 usb@22000 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 compatible = "fsl-usb2-dr";
278 reg = <0x22000 0x1000>;
279 interrupt-parent = <&mpic>;
280 interrupts = <28 0x2>;
281 };
282
283 /* USB2 is shared with localbus, so it must be disabled
284 by default. We can't put 'status = "disabled";' here
285 since U-Boot doesn't clear the status property when
286 it enables USB2. OTOH, U-Boot does create a new node
287 when there isn't any. So, just comment it out.
288 usb@23000 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "fsl-usb2-dr";
292 reg = <0x23000 0x1000>;
293 interrupt-parent = <&mpic>;
294 interrupts = <46 0x2>;
295 phy_type = "ulpi";
296 };
297 */
298
299 sdhci@2e000 {
300 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
301 reg = <0x2e000 0x1000>;
302 interrupts = <72 0x2>;
303 interrupt-parent = <&mpic>;
304 /* Filled in by U-Boot */
305 clock-frequency = <0>;
306 };
307
308 crypto@30000 {
309 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
310 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
311 reg = <0x30000 0x10000>;
312 interrupts = <45 2 58 2>;
313 interrupt-parent = <&mpic>;
314 fsl,num-channels = <4>;
315 fsl,channel-fifo-len = <24>;
316 fsl,exec-units-mask = <0xbfe>;
317 fsl,descriptor-types-mask = <0x3ab0ebf>;
318 };
319
320 mpic: pic@40000 {
321 interrupt-controller;
322 #address-cells = <0>;
323 #interrupt-cells = <2>;
324 reg = <0x40000 0x40000>;
325 compatible = "chrp,open-pic";
326 device_type = "open-pic";
327 };
328
329 msi@41600 {
330 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
331 reg = <0x41600 0x80>;
332 msi-available-ranges = <0 0x100>;
333 interrupts = <
334 0xe0 0
335 0xe1 0
336 0xe2 0
337 0xe3 0
338 0xe4 0
339 0xe5 0
340 0xe6 0
341 0xe7 0>;
342 interrupt-parent = <&mpic>;
343 };
344
345 global-utilities@e0000 { //global utilities block
346 compatible = "fsl,p1020-guts","fsl,p2020-guts";
347 reg = <0xe0000 0x1000>;
348 fsl,has-rstcr;
349 };
350 };
351
352 pci0: pcie@ffe09000 {
353 compatible = "fsl,mpc8548-pcie";
354 device_type = "pci";
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0 0xffe09000 0 0x1000>;
359 bus-range = <0 255>;
360 clock-frequency = <33333333>;
361 interrupt-parent = <&mpic>;
362 interrupts = <16 2>;
363 };
364
365 pci1: pcie@ffe0a000 {
366 compatible = "fsl,mpc8548-pcie";
367 device_type = "pci";
368 #interrupt-cells = <1>;
369 #size-cells = <2>;
370 #address-cells = <3>;
371 reg = <0 0xffe0a000 0 0x1000>;
372 bus-range = <0 255>;
373 clock-frequency = <33333333>;
374 interrupt-parent = <&mpic>;
375 interrupts = <16 2>;
376 };
377};
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index 8bcb10b92677..98d9426d4b85 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -52,7 +52,7 @@
52 #size-cells = <1>; 52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; 53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>; 54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>; 55 interrupts = <19 2 0 0>;
56 56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000 58 0x1 0x0 0xf 0xe0000000 0x08000000
@@ -148,6 +148,17 @@
148 label = "reserved-nand"; 148 label = "reserved-nand";
149 }; 149 };
150 }; 150 };
151
152 board-control@3,0 {
153 compatible = "fsl,p1022ds-pixis";
154 reg = <3 0 0x30>;
155 interrupt-parent = <&mpic>;
156 /*
157 * IRQ8 is generated if the "EVENT" switch is pressed
158 * and PX_CTL[EVESEL] is set to 00.
159 */
160 interrupts = <8 8 0 0>;
161 };
151 }; 162 };
152 163
153 soc@fffe00000 { 164 soc@fffe00000 {
@@ -167,13 +178,13 @@
167 ecm@1000 { 178 ecm@1000 {
168 compatible = "fsl,p1022-ecm", "fsl,ecm"; 179 compatible = "fsl,p1022-ecm", "fsl,ecm";
169 reg = <0x1000 0x1000>; 180 reg = <0x1000 0x1000>;
170 interrupts = <16 2>; 181 interrupts = <16 2 0 0>;
171 }; 182 };
172 183
173 memory-controller@2000 { 184 memory-controller@2000 {
174 compatible = "fsl,p1022-memory-controller"; 185 compatible = "fsl,p1022-memory-controller";
175 reg = <0x2000 0x1000>; 186 reg = <0x2000 0x1000>;
176 interrupts = <16 2>; 187 interrupts = <16 2 0 0>;
177 }; 188 };
178 189
179 i2c@3000 { 190 i2c@3000 {
@@ -182,7 +193,7 @@
182 cell-index = <0>; 193 cell-index = <0>;
183 compatible = "fsl-i2c"; 194 compatible = "fsl-i2c";
184 reg = <0x3000 0x100>; 195 reg = <0x3000 0x100>;
185 interrupts = <43 2>; 196 interrupts = <43 2 0 0>;
186 dfsrr; 197 dfsrr;
187 }; 198 };
188 199
@@ -192,14 +203,16 @@
192 cell-index = <1>; 203 cell-index = <1>;
193 compatible = "fsl-i2c"; 204 compatible = "fsl-i2c";
194 reg = <0x3100 0x100>; 205 reg = <0x3100 0x100>;
195 interrupts = <43 2>; 206 interrupts = <43 2 0 0>;
196 dfsrr; 207 dfsrr;
197 208
198 wm8776:codec@1a { 209 wm8776:codec@1a {
199 compatible = "wlf,wm8776"; 210 compatible = "wlf,wm8776";
200 reg = <0x1a>; 211 reg = <0x1a>;
201 /* MCLK source is a stand-alone oscillator */ 212 /*
202 clock-frequency = <12288000>; 213 * clock-frequency will be set by U-Boot if
214 * the clock is enabled.
215 */
203 }; 216 };
204 }; 217 };
205 218
@@ -209,7 +222,7 @@
209 compatible = "ns16550"; 222 compatible = "ns16550";
210 reg = <0x4500 0x100>; 223 reg = <0x4500 0x100>;
211 clock-frequency = <0>; 224 clock-frequency = <0>;
212 interrupts = <42 2>; 225 interrupts = <42 2 0 0>;
213 }; 226 };
214 227
215 serial1: serial@4600 { 228 serial1: serial@4600 {
@@ -218,7 +231,7 @@
218 compatible = "ns16550"; 231 compatible = "ns16550";
219 reg = <0x4600 0x100>; 232 reg = <0x4600 0x100>;
220 clock-frequency = <0>; 233 clock-frequency = <0>;
221 interrupts = <42 2>; 234 interrupts = <42 2 0 0>;
222 }; 235 };
223 236
224 spi@7000 { 237 spi@7000 {
@@ -227,7 +240,7 @@
227 #size-cells = <0>; 240 #size-cells = <0>;
228 compatible = "fsl,espi"; 241 compatible = "fsl,espi";
229 reg = <0x7000 0x1000>; 242 reg = <0x7000 0x1000>;
230 interrupts = <59 0x2>; 243 interrupts = <59 0x2 0 0>;
231 espi,num-ss-bits = <4>; 244 espi,num-ss-bits = <4>;
232 mode = "cpu"; 245 mode = "cpu";
233 246
@@ -264,12 +277,13 @@
264 compatible = "fsl,mpc8610-ssi"; 277 compatible = "fsl,mpc8610-ssi";
265 cell-index = <0>; 278 cell-index = <0>;
266 reg = <0x15000 0x100>; 279 reg = <0x15000 0x100>;
267 interrupts = <75 2>; 280 interrupts = <75 2 0 0>;
268 fsl,mode = "i2s-slave"; 281 fsl,mode = "i2s-slave";
269 codec-handle = <&wm8776>; 282 codec-handle = <&wm8776>;
270 fsl,playback-dma = <&dma00>; 283 fsl,playback-dma = <&dma00>;
271 fsl,capture-dma = <&dma01>; 284 fsl,capture-dma = <&dma01>;
272 fsl,fifo-depth = <16>; 285 fsl,fifo-depth = <15>;
286 fsl,ssi-asynchronous;
273 }; 287 };
274 288
275 dma@c300 { 289 dma@c300 {
@@ -280,28 +294,28 @@
280 ranges = <0x0 0xc100 0x200>; 294 ranges = <0x0 0xc100 0x200>;
281 cell-index = <1>; 295 cell-index = <1>;
282 dma00: dma-channel@0 { 296 dma00: dma-channel@0 {
283 compatible = "fsl,eloplus-dma-channel"; 297 compatible = "fsl,ssi-dma-channel";
284 reg = <0x0 0x80>; 298 reg = <0x0 0x80>;
285 cell-index = <0>; 299 cell-index = <0>;
286 interrupts = <76 2>; 300 interrupts = <76 2 0 0>;
287 }; 301 };
288 dma01: dma-channel@80 { 302 dma01: dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel"; 303 compatible = "fsl,ssi-dma-channel";
290 reg = <0x80 0x80>; 304 reg = <0x80 0x80>;
291 cell-index = <1>; 305 cell-index = <1>;
292 interrupts = <77 2>; 306 interrupts = <77 2 0 0>;
293 }; 307 };
294 dma-channel@100 { 308 dma-channel@100 {
295 compatible = "fsl,eloplus-dma-channel"; 309 compatible = "fsl,eloplus-dma-channel";
296 reg = <0x100 0x80>; 310 reg = <0x100 0x80>;
297 cell-index = <2>; 311 cell-index = <2>;
298 interrupts = <78 2>; 312 interrupts = <78 2 0 0>;
299 }; 313 };
300 dma-channel@180 { 314 dma-channel@180 {
301 compatible = "fsl,eloplus-dma-channel"; 315 compatible = "fsl,eloplus-dma-channel";
302 reg = <0x180 0x80>; 316 reg = <0x180 0x80>;
303 cell-index = <3>; 317 cell-index = <3>;
304 interrupts = <79 2>; 318 interrupts = <79 2 0 0>;
305 }; 319 };
306 }; 320 };
307 321
@@ -309,7 +323,7 @@
309 #gpio-cells = <2>; 323 #gpio-cells = <2>;
310 compatible = "fsl,mpc8572-gpio"; 324 compatible = "fsl,mpc8572-gpio";
311 reg = <0xf000 0x100>; 325 reg = <0xf000 0x100>;
312 interrupts = <47 0x2>; 326 interrupts = <47 0x2 0 0>;
313 gpio-controller; 327 gpio-controller;
314 }; 328 };
315 329
@@ -318,7 +332,7 @@
318 reg = <0x20000 0x1000>; 332 reg = <0x20000 0x1000>;
319 cache-line-size = <32>; // 32 bytes 333 cache-line-size = <32>; // 32 bytes
320 cache-size = <0x40000>; // L2, 256K 334 cache-size = <0x40000>; // L2, 256K
321 interrupts = <16 2>; 335 interrupts = <16 2 0 0>;
322 }; 336 };
323 337
324 dma@21300 { 338 dma@21300 {
@@ -332,25 +346,25 @@
332 compatible = "fsl,eloplus-dma-channel"; 346 compatible = "fsl,eloplus-dma-channel";
333 reg = <0x0 0x80>; 347 reg = <0x0 0x80>;
334 cell-index = <0>; 348 cell-index = <0>;
335 interrupts = <20 2>; 349 interrupts = <20 2 0 0>;
336 }; 350 };
337 dma-channel@80 { 351 dma-channel@80 {
338 compatible = "fsl,eloplus-dma-channel"; 352 compatible = "fsl,eloplus-dma-channel";
339 reg = <0x80 0x80>; 353 reg = <0x80 0x80>;
340 cell-index = <1>; 354 cell-index = <1>;
341 interrupts = <21 2>; 355 interrupts = <21 2 0 0>;
342 }; 356 };
343 dma-channel@100 { 357 dma-channel@100 {
344 compatible = "fsl,eloplus-dma-channel"; 358 compatible = "fsl,eloplus-dma-channel";
345 reg = <0x100 0x80>; 359 reg = <0x100 0x80>;
346 cell-index = <2>; 360 cell-index = <2>;
347 interrupts = <22 2>; 361 interrupts = <22 2 0 0>;
348 }; 362 };
349 dma-channel@180 { 363 dma-channel@180 {
350 compatible = "fsl,eloplus-dma-channel"; 364 compatible = "fsl,eloplus-dma-channel";
351 reg = <0x180 0x80>; 365 reg = <0x180 0x80>;
352 cell-index = <3>; 366 cell-index = <3>;
353 interrupts = <23 2>; 367 interrupts = <23 2 0 0>;
354 }; 368 };
355 }; 369 };
356 370
@@ -359,7 +373,7 @@
359 #size-cells = <0>; 373 #size-cells = <0>;
360 compatible = "fsl-usb2-dr"; 374 compatible = "fsl-usb2-dr";
361 reg = <0x22000 0x1000>; 375 reg = <0x22000 0x1000>;
362 interrupts = <28 0x2>; 376 interrupts = <28 0x2 0 0>;
363 phy_type = "ulpi"; 377 phy_type = "ulpi";
364 }; 378 };
365 379
@@ -370,11 +384,11 @@
370 reg = <0x24000 0x1000 0xb0030 0x4>; 384 reg = <0x24000 0x1000 0xb0030 0x4>;
371 385
372 phy0: ethernet-phy@0 { 386 phy0: ethernet-phy@0 {
373 interrupts = <3 1>; 387 interrupts = <3 1 0 0>;
374 reg = <0x1>; 388 reg = <0x1>;
375 }; 389 };
376 phy1: ethernet-phy@1 { 390 phy1: ethernet-phy@1 {
377 interrupts = <9 1>; 391 interrupts = <9 1 0 0>;
378 reg = <0x2>; 392 reg = <0x2>;
379 }; 393 };
380 }; 394 };
@@ -405,13 +419,13 @@
405 #address-cells = <1>; 419 #address-cells = <1>;
406 #size-cells = <1>; 420 #size-cells = <1>;
407 reg = <0xB0000 0x1000>; 421 reg = <0xB0000 0x1000>;
408 interrupts = <29 2 30 2 34 2>; 422 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
409 }; 423 };
410 queue-group@1{ 424 queue-group@1{
411 #address-cells = <1>; 425 #address-cells = <1>;
412 #size-cells = <1>; 426 #size-cells = <1>;
413 reg = <0xB4000 0x1000>; 427 reg = <0xB4000 0x1000>;
414 interrupts = <17 2 18 2 24 2>; 428 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
415 }; 429 };
416 }; 430 };
417 431
@@ -432,20 +446,20 @@
432 #address-cells = <1>; 446 #address-cells = <1>;
433 #size-cells = <1>; 447 #size-cells = <1>;
434 reg = <0xB1000 0x1000>; 448 reg = <0xB1000 0x1000>;
435 interrupts = <35 2 36 2 40 2>; 449 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
436 }; 450 };
437 queue-group@1{ 451 queue-group@1{
438 #address-cells = <1>; 452 #address-cells = <1>;
439 #size-cells = <1>; 453 #size-cells = <1>;
440 reg = <0xB5000 0x1000>; 454 reg = <0xB5000 0x1000>;
441 interrupts = <51 2 52 2 67 2>; 455 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
442 }; 456 };
443 }; 457 };
444 458
445 sdhci@2e000 { 459 sdhci@2e000 {
446 compatible = "fsl,p1022-esdhc", "fsl,esdhc"; 460 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
447 reg = <0x2e000 0x1000>; 461 reg = <0x2e000 0x1000>;
448 interrupts = <72 0x2>; 462 interrupts = <72 0x2 0 0>;
449 fsl,sdhci-auto-cmd12; 463 fsl,sdhci-auto-cmd12;
450 /* Filled in by U-Boot */ 464 /* Filled in by U-Boot */
451 clock-frequency = <0>; 465 clock-frequency = <0>;
@@ -456,7 +470,7 @@
456 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 470 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
457 "fsl,sec2.0"; 471 "fsl,sec2.0";
458 reg = <0x30000 0x10000>; 472 reg = <0x30000 0x10000>;
459 interrupts = <45 2 58 2>; 473 interrupts = <45 2 0 0 58 2 0 0>;
460 fsl,num-channels = <4>; 474 fsl,num-channels = <4>;
461 fsl,channel-fifo-len = <24>; 475 fsl,channel-fifo-len = <24>;
462 fsl,exec-units-mask = <0x97c>; 476 fsl,exec-units-mask = <0x97c>;
@@ -464,17 +478,17 @@
464 }; 478 };
465 479
466 sata@18000 { 480 sata@18000 {
467 compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; 481 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
468 reg = <0x18000 0x1000>; 482 reg = <0x18000 0x1000>;
469 cell-index = <1>; 483 cell-index = <1>;
470 interrupts = <74 0x2>; 484 interrupts = <74 0x2 0 0>;
471 }; 485 };
472 486
473 sata@19000 { 487 sata@19000 {
474 compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; 488 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
475 reg = <0x19000 0x1000>; 489 reg = <0x19000 0x1000>;
476 cell-index = <2>; 490 cell-index = <2>;
477 interrupts = <41 0x2>; 491 interrupts = <41 0x2 0 0>;
478 }; 492 };
479 493
480 power@e0070{ 494 power@e0070{
@@ -485,21 +499,33 @@
485 display@10000 { 499 display@10000 {
486 compatible = "fsl,diu", "fsl,p1022-diu"; 500 compatible = "fsl,diu", "fsl,p1022-diu";
487 reg = <0x10000 1000>; 501 reg = <0x10000 1000>;
488 interrupts = <64 2>; 502 interrupts = <64 2 0 0>;
489 }; 503 };
490 504
491 timer@41100 { 505 timer@41100 {
492 compatible = "fsl,mpic-global-timer"; 506 compatible = "fsl,mpic-global-timer";
493 reg = <0x41100 0x204>; 507 reg = <0x41100 0x100 0x41300 4>;
494 interrupts = <0xf7 0x2>; 508 interrupts = <0 0 3 0
509 1 0 3 0
510 2 0 3 0
511 3 0 3 0>;
512 };
513
514 timer@42100 {
515 compatible = "fsl,mpic-global-timer";
516 reg = <0x42100 0x100 0x42300 4>;
517 interrupts = <4 0 3 0
518 5 0 3 0
519 6 0 3 0
520 7 0 3 0>;
495 }; 521 };
496 522
497 mpic: pic@40000 { 523 mpic: pic@40000 {
498 interrupt-controller; 524 interrupt-controller;
499 #address-cells = <0>; 525 #address-cells = <0>;
500 #interrupt-cells = <2>; 526 #interrupt-cells = <4>;
501 reg = <0x40000 0x40000>; 527 reg = <0x40000 0x40000>;
502 compatible = "chrp,open-pic"; 528 compatible = "fsl,mpic";
503 device_type = "open-pic"; 529 device_type = "open-pic";
504 }; 530 };
505 531
@@ -508,14 +534,14 @@
508 reg = <0x41600 0x80>; 534 reg = <0x41600 0x80>;
509 msi-available-ranges = <0 0x100>; 535 msi-available-ranges = <0 0x100>;
510 interrupts = < 536 interrupts = <
511 0xe0 0 537 0xe0 0 0 0
512 0xe1 0 538 0xe1 0 0 0
513 0xe2 0 539 0xe2 0 0 0
514 0xe3 0 540 0xe3 0 0 0
515 0xe4 0 541 0xe4 0 0 0
516 0xe5 0 542 0xe5 0 0 0
517 0xe6 0 543 0xe6 0 0 0
518 0xe7 0>; 544 0xe7 0 0 0>;
519 }; 545 };
520 546
521 global-utilities@e0000 { //global utilities block 547 global-utilities@e0000 { //global utilities block
@@ -536,7 +562,7 @@
536 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000 562 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
537 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 563 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
538 clock-frequency = <33333333>; 564 clock-frequency = <33333333>;
539 interrupts = <16 2>; 565 interrupts = <16 2 0 0>;
540 interrupt-map-mask = <0xf800 0 0 7>; 566 interrupt-map-mask = <0xf800 0 0 7>;
541 interrupt-map = < 567 interrupt-map = <
542 /* IDSEL 0x0 */ 568 /* IDSEL 0x0 */
@@ -571,7 +597,7 @@
571 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 597 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
572 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; 598 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
573 clock-frequency = <33333333>; 599 clock-frequency = <33333333>;
574 interrupts = <16 2>; 600 interrupts = <16 2 0 0>;
575 interrupt-map-mask = <0xf800 0 0 7>; 601 interrupt-map-mask = <0xf800 0 0 7>;
576 interrupt-map = < 602 interrupt-map = <
577 /* IDSEL 0x0 */ 603 /* IDSEL 0x0 */
@@ -607,7 +633,7 @@
607 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 633 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
608 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 634 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
609 clock-frequency = <33333333>; 635 clock-frequency = <33333333>;
610 interrupts = <16 2>; 636 interrupts = <16 2 0 0>;
611 interrupt-map-mask = <0xf800 0 0 7>; 637 interrupt-map-mask = <0xf800 0 0 7>;
612 interrupt-map = < 638 interrupt-map = <
613 /* IDSEL 0x0 */ 639 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 11019142813c..dae403100f2f 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P2020 DS Device Tree Source 2 * P2020 DS Device Tree Source
3 * 3 *
4 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p2020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P2020"; 15 model = "fsl,P2020DS";
15 compatible = "fsl,P2020DS"; 16 compatible = "fsl,P2020DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -27,35 +26,13 @@
27 pci2 = &pci2; 26 pci2 = &pci2;
28 }; 27 };
29 28
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,P2020@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 next-level-cache = <&L2>;
38 };
39
40 PowerPC,P2020@1 {
41 device_type = "cpu";
42 reg = <0x1>;
43 next-level-cache = <&L2>;
44 };
45 };
46 29
47 memory { 30 memory {
48 device_type = "memory"; 31 device_type = "memory";
49 }; 32 };
50 33
51 localbus@ffe05000 { 34 localbus@ffe05000 {
52 #address-cells = <2>;
53 #size-cells = <1>;
54 compatible = "fsl,elbc", "simple-bus"; 35 compatible = "fsl,elbc", "simple-bus";
55 reg = <0 0xffe05000 0 0x1000>;
56 interrupts = <19 2>;
57 interrupt-parent = <&mpic>;
58
59 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 36 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
60 0x1 0x0 0x0 0xe0000000 0x08000000 37 0x1 0x0 0x0 0xe0000000 0x08000000
61 0x2 0x0 0x0 0xffa00000 0x00040000 38 0x2 0x0 0x0 0xffa00000 0x00040000
@@ -158,352 +135,90 @@
158 }; 135 };
159 136
160 soc@ffe00000 { 137 soc@ffe00000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 device_type = "soc";
164 compatible = "fsl,p2020-immr", "simple-bus";
165 ranges = <0x0 0 0xffe00000 0x100000>;
166 bus-frequency = <0>; // Filled out by uboot.
167
168 ecm-law@0 {
169 compatible = "fsl,ecm-law";
170 reg = <0x0 0x1000>;
171 fsl,num-laws = <12>;
172 };
173
174 ecm@1000 {
175 compatible = "fsl,p2020-ecm", "fsl,ecm";
176 reg = <0x1000 0x1000>;
177 interrupts = <17 2>;
178 interrupt-parent = <&mpic>;
179 };
180
181 memory-controller@2000 {
182 compatible = "fsl,p2020-memory-controller";
183 reg = <0x2000 0x1000>;
184 interrupt-parent = <&mpic>;
185 interrupts = <18 2>;
186 };
187
188 i2c@3000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 cell-index = <0>;
192 compatible = "fsl-i2c";
193 reg = <0x3000 0x100>;
194 interrupts = <43 2>;
195 interrupt-parent = <&mpic>;
196 dfsrr;
197 };
198
199 i2c@3100 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 cell-index = <1>;
203 compatible = "fsl-i2c";
204 reg = <0x3100 0x100>;
205 interrupts = <43 2>;
206 interrupt-parent = <&mpic>;
207 dfsrr;
208 };
209 138
210 serial0: serial@4500 { 139 usb@22000 {
211 cell-index = <0>; 140 phy_type = "ulpi";
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>;
215 clock-frequency = <0>;
216 interrupts = <42 2>;
217 interrupt-parent = <&mpic>;
218 };
219
220 serial1: serial@4600 {
221 cell-index = <1>;
222 device_type = "serial";
223 compatible = "ns16550";
224 reg = <0x4600 0x100>;
225 clock-frequency = <0>;
226 interrupts = <42 2>;
227 interrupt-parent = <&mpic>;
228 };
229
230 spi@7000 {
231 compatible = "fsl,espi";
232 reg = <0x7000 0x1000>;
233 interrupts = <59 0x2>;
234 interrupt-parent = <&mpic>;
235 }; 141 };
236 142
237 dma@c300 { 143 mdio@24520 {
238 #address-cells = <1>; 144 phy0: ethernet-phy@0 {
239 #size-cells = <1>;
240 compatible = "fsl,eloplus-dma";
241 reg = <0xc300 0x4>;
242 ranges = <0x0 0xc100 0x200>;
243 cell-index = <1>;
244 dma-channel@0 {
245 compatible = "fsl,eloplus-dma-channel";
246 reg = <0x0 0x80>;
247 cell-index = <0>;
248 interrupt-parent = <&mpic>; 145 interrupt-parent = <&mpic>;
249 interrupts = <76 2>; 146 interrupts = <3 1>;
147 reg = <0x0>;
250 }; 148 };
251 dma-channel@80 { 149 phy1: ethernet-phy@1 {
252 compatible = "fsl,eloplus-dma-channel";
253 reg = <0x80 0x80>;
254 cell-index = <1>;
255 interrupt-parent = <&mpic>; 150 interrupt-parent = <&mpic>;
256 interrupts = <77 2>; 151 interrupts = <3 1>;
152 reg = <0x1>;
257 }; 153 };
258 dma-channel@100 { 154 phy2: ethernet-phy@2 {
259 compatible = "fsl,eloplus-dma-channel";
260 reg = <0x100 0x80>;
261 cell-index = <2>;
262 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
263 interrupts = <78 2>; 156 interrupts = <3 1>;
157 reg = <0x2>;
264 }; 158 };
265 dma-channel@180 { 159 tbi0: tbi-phy@11 {
266 compatible = "fsl,eloplus-dma-channel"; 160 reg = <0x11>;
267 reg = <0x180 0x80>; 161 device_type = "tbi-phy";
268 cell-index = <3>;
269 interrupt-parent = <&mpic>;
270 interrupts = <79 2>;
271 }; 162 };
272 };
273 163
274 gpio: gpio-controller@f000 {
275 #gpio-cells = <2>;
276 compatible = "fsl,mpc8572-gpio";
277 reg = <0xf000 0x100>;
278 interrupts = <47 0x2>;
279 interrupt-parent = <&mpic>;
280 gpio-controller;
281 }; 164 };
282 165
283 L2: l2-cache-controller@20000 { 166 mdio@25520 {
284 compatible = "fsl,p2020-l2-cache-controller"; 167 tbi1: tbi-phy@11 {
285 reg = <0x20000 0x1000>; 168 reg = <0x11>;
286 cache-line-size = <32>; // 32 bytes 169 device_type = "tbi-phy";
287 cache-size = <0x80000>; // L2, 512k 170 };
288 interrupt-parent = <&mpic>;
289 interrupts = <16 2>;
290 }; 171 };
291 172
292 dma@21300 { 173 mdio@26520 {
293 #address-cells = <1>; 174 tbi2: tbi-phy@11 {
294 #size-cells = <1>; 175 reg = <0x11>;
295 compatible = "fsl,eloplus-dma"; 176 device_type = "tbi-phy";
296 reg = <0x21300 0x4>;
297 ranges = <0x0 0x21100 0x200>;
298 cell-index = <0>;
299 dma-channel@0 {
300 compatible = "fsl,eloplus-dma-channel";
301 reg = <0x0 0x80>;
302 cell-index = <0>;
303 interrupt-parent = <&mpic>;
304 interrupts = <20 2>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,eloplus-dma-channel";
308 reg = <0x80 0x80>;
309 cell-index = <1>;
310 interrupt-parent = <&mpic>;
311 interrupts = <21 2>;
312 };
313 dma-channel@100 {
314 compatible = "fsl,eloplus-dma-channel";
315 reg = <0x100 0x80>;
316 cell-index = <2>;
317 interrupt-parent = <&mpic>;
318 interrupts = <22 2>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,eloplus-dma-channel";
322 reg = <0x180 0x80>;
323 cell-index = <3>;
324 interrupt-parent = <&mpic>;
325 interrupts = <23 2>;
326 }; 177 };
178
327 }; 179 };
328 180
329 usb@22000 { 181 ptp_clock@24E00 {
330 #address-cells = <1>; 182 compatible = "fsl,etsec-ptp";
331 #size-cells = <0>; 183 reg = <0x24E00 0xB0>;
332 compatible = "fsl-usb2-dr"; 184 interrupts = <68 2 69 2 70 2>;
333 reg = <0x22000 0x1000>; 185 interrupt-parent = < &mpic >;
334 interrupt-parent = <&mpic>; 186 fsl,tclk-period = <5>;
335 interrupts = <28 0x2>; 187 fsl,tmr-prsc = <200>;
336 phy_type = "ulpi"; 188 fsl,tmr-add = <0xCCCCCCCD>;
189 fsl,tmr-fiper1 = <0x3B9AC9FB>;
190 fsl,tmr-fiper2 = <0x0001869B>;
191 fsl,max-adj = <249999999>;
337 }; 192 };
338 193
339 enet0: ethernet@24000 { 194 enet0: ethernet@24000 {
340 #address-cells = <1>;
341 #size-cells = <1>;
342 cell-index = <0>;
343 device_type = "network";
344 model = "eTSEC";
345 compatible = "gianfar";
346 reg = <0x24000 0x1000>;
347 ranges = <0x0 0x24000 0x1000>;
348 local-mac-address = [ 00 00 00 00 00 00 ];
349 interrupts = <29 2 30 2 34 2>;
350 interrupt-parent = <&mpic>;
351 tbi-handle = <&tbi0>; 195 tbi-handle = <&tbi0>;
352 phy-handle = <&phy0>; 196 phy-handle = <&phy0>;
353 phy-connection-type = "rgmii-id"; 197 phy-connection-type = "rgmii-id";
354
355 mdio@520 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "fsl,gianfar-mdio";
359 reg = <0x520 0x20>;
360
361 phy0: ethernet-phy@0 {
362 interrupt-parent = <&mpic>;
363 interrupts = <3 1>;
364 reg = <0x0>;
365 };
366 phy1: ethernet-phy@1 {
367 interrupt-parent = <&mpic>;
368 interrupts = <3 1>;
369 reg = <0x1>;
370 };
371 phy2: ethernet-phy@2 {
372 interrupt-parent = <&mpic>;
373 interrupts = <3 1>;
374 reg = <0x2>;
375 };
376 tbi0: tbi-phy@11 {
377 reg = <0x11>;
378 device_type = "tbi-phy";
379 };
380 };
381 }; 198 };
382 199
383 enet1: ethernet@25000 { 200 enet1: ethernet@25000 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 cell-index = <1>;
387 device_type = "network";
388 model = "eTSEC";
389 compatible = "gianfar";
390 reg = <0x25000 0x1000>;
391 ranges = <0x0 0x25000 0x1000>;
392 local-mac-address = [ 00 00 00 00 00 00 ];
393 interrupts = <35 2 36 2 40 2>;
394 interrupt-parent = <&mpic>;
395 tbi-handle = <&tbi1>; 201 tbi-handle = <&tbi1>;
396 phy-handle = <&phy1>; 202 phy-handle = <&phy1>;
397 phy-connection-type = "rgmii-id"; 203 phy-connection-type = "rgmii-id";
398 204
399 mdio@520 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "fsl,gianfar-tbi";
403 reg = <0x520 0x20>;
404
405 tbi1: tbi-phy@11 {
406 reg = <0x11>;
407 device_type = "tbi-phy";
408 };
409 };
410 }; 205 };
411 206
412 enet2: ethernet@26000 { 207 enet2: ethernet@26000 {
413 #address-cells = <1>;
414 #size-cells = <1>;
415 cell-index = <2>;
416 device_type = "network";
417 model = "eTSEC";
418 compatible = "gianfar";
419 reg = <0x26000 0x1000>;
420 ranges = <0x0 0x26000 0x1000>;
421 local-mac-address = [ 00 00 00 00 00 00 ];
422 interrupts = <31 2 32 2 33 2>;
423 interrupt-parent = <&mpic>;
424 tbi-handle = <&tbi2>; 208 tbi-handle = <&tbi2>;
425 phy-handle = <&phy2>; 209 phy-handle = <&phy2>;
426 phy-connection-type = "rgmii-id"; 210 phy-connection-type = "rgmii-id";
427
428 mdio@520 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "fsl,gianfar-tbi";
432 reg = <0x520 0x20>;
433
434 tbi2: tbi-phy@11 {
435 reg = <0x11>;
436 device_type = "tbi-phy";
437 };
438 };
439 };
440
441 sdhci@2e000 {
442 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
443 reg = <0x2e000 0x1000>;
444 interrupts = <72 0x2>;
445 interrupt-parent = <&mpic>;
446 /* Filled in by U-Boot */
447 clock-frequency = <0>;
448 };
449
450 crypto@30000 {
451 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
452 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
453 reg = <0x30000 0x10000>;
454 interrupts = <45 2 58 2>;
455 interrupt-parent = <&mpic>;
456 fsl,num-channels = <4>;
457 fsl,channel-fifo-len = <24>;
458 fsl,exec-units-mask = <0xbfe>;
459 fsl,descriptor-types-mask = <0x3ab0ebf>;
460 }; 211 };
461 212
462 mpic: pic@40000 {
463 interrupt-controller;
464 #address-cells = <0>;
465 #interrupt-cells = <2>;
466 reg = <0x40000 0x40000>;
467 compatible = "chrp,open-pic";
468 device_type = "open-pic";
469 };
470 213
471 msi@41600 { 214 msi@41600 {
472 compatible = "fsl,mpic-msi"; 215 compatible = "fsl,mpic-msi";
473 reg = <0x41600 0x80>;
474 msi-available-ranges = <0 0x100>;
475 interrupts = <
476 0xe0 0
477 0xe1 0
478 0xe2 0
479 0xe3 0
480 0xe4 0
481 0xe5 0
482 0xe6 0
483 0xe7 0>;
484 interrupt-parent = <&mpic>;
485 };
486
487 global-utilities@e0000 { //global utilities block
488 compatible = "fsl,p2020-guts";
489 reg = <0xe0000 0x1000>;
490 fsl,has-rstcr;
491 }; 216 };
492 }; 217 };
493 218
494 pci0: pcie@ffe08000 { 219 pci0: pcie@ffe08000 {
495 compatible = "fsl,mpc8548-pcie";
496 device_type = "pci";
497 #interrupt-cells = <1>;
498 #size-cells = <2>;
499 #address-cells = <3>;
500 reg = <0 0xffe08000 0 0x1000>;
501 bus-range = <0 255>;
502 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 220 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
503 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 221 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
504 clock-frequency = <33333333>;
505 interrupt-parent = <&mpic>;
506 interrupts = <24 2>;
507 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 222 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
508 interrupt-map = < 223 interrupt-map = <
509 /* IDSEL 0x0 */ 224 /* IDSEL 0x0 */
@@ -528,18 +243,8 @@
528 }; 243 };
529 244
530 pci1: pcie@ffe09000 { 245 pci1: pcie@ffe09000 {
531 compatible = "fsl,mpc8548-pcie";
532 device_type = "pci";
533 #interrupt-cells = <1>;
534 #size-cells = <2>;
535 #address-cells = <3>;
536 reg = <0 0xffe09000 0 0x1000>;
537 bus-range = <0 255>;
538 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 246 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
539 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 247 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
540 clock-frequency = <33333333>;
541 interrupt-parent = <&mpic>;
542 interrupts = <25 2>;
543 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 248 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
544 interrupt-map = < 249 interrupt-map = <
545 250
@@ -667,18 +372,8 @@
667 }; 372 };
668 373
669 pci2: pcie@ffe0a000 { 374 pci2: pcie@ffe0a000 {
670 compatible = "fsl,mpc8548-pcie";
671 device_type = "pci";
672 #interrupt-cells = <1>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 reg = <0 0xffe0a000 0 0x1000>;
676 bus-range = <0 255>;
677 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 375 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
678 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 376 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
679 clock-frequency = <33333333>;
680 interrupt-parent = <&mpic>;
681 interrupts = <26 2>;
682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 377 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
683 interrupt-map = < 378 interrupt-map = <
684 /* IDSEL 0x0 */ 379 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index da4cb0d8d215..1d7a05f3021e 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P2020 RDB Device Tree Source 2 * P2020 RDB Device Tree Source
3 * 3 *
4 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p2020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P2020"; 15 model = "fsl,P2020RDB";
15 compatible = "fsl,P2020RDB"; 16 compatible = "fsl,P2020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -26,34 +25,11 @@
26 pci1 = &pci1; 25 pci1 = &pci1;
27 }; 26 };
28 27
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P2020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P2020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory { 28 memory {
47 device_type = "memory"; 29 device_type = "memory";
48 }; 30 };
49 31
50 localbus@ffe05000 { 32 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57 33
58 /* NOR and NAND Flashes */ 34 /* NOR and NAND Flashes */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,90 +141,16 @@
165 }; 141 };
166 142
167 soc@ffe00000 { 143 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p2020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p2020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <17 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p2020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
194
195 i2c@3000 { 144 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 { 145 rtc@68 {
205 compatible = "dallas,ds1339"; 146 compatible = "dallas,ds1339";
206 reg = <0x68>; 147 reg = <0x68>;
207 }; 148 };
208 }; 149 };
209 150
210 i2c@3100 { 151 spi@7000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240 152
241 spi@7000 { 153 fsl_m25p80@0 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250
251 fsl_m25p80@0 {
252 #address-cells = <1>; 154 #address-cells = <1>;
253 #size-cells = <1>; 155 #size-cells = <1>;
254 compatible = "fsl,espi-flash"; 156 compatible = "fsl,espi-flash";
@@ -294,254 +196,81 @@
294 }; 196 };
295 }; 197 };
296 198
297 dma@c300 { 199 usb@22000 {
298 #address-cells = <1>; 200 phy_type = "ulpi";
299 #size-cells = <1>; 201 };
300 compatible = "fsl,eloplus-dma"; 202
301 reg = <0xc300 0x4>; 203 mdio@24520 {
302 ranges = <0x0 0xc100 0x200>; 204 phy0: ethernet-phy@0 {
303 cell-index = <1>;
304 dma-channel@0 {
305 compatible = "fsl,eloplus-dma-channel";
306 reg = <0x0 0x80>;
307 cell-index = <0>;
308 interrupt-parent = <&mpic>;
309 interrupts = <76 2>;
310 };
311 dma-channel@80 {
312 compatible = "fsl,eloplus-dma-channel";
313 reg = <0x80 0x80>;
314 cell-index = <1>;
315 interrupt-parent = <&mpic>;
316 interrupts = <77 2>;
317 };
318 dma-channel@100 {
319 compatible = "fsl,eloplus-dma-channel";
320 reg = <0x100 0x80>;
321 cell-index = <2>;
322 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
323 interrupts = <78 2>; 206 interrupts = <3 1>;
324 }; 207 reg = <0x0>;
325 dma-channel@180 { 208 };
326 compatible = "fsl,eloplus-dma-channel"; 209 phy1: ethernet-phy@1 {
327 reg = <0x180 0x80>;
328 cell-index = <3>;
329 interrupt-parent = <&mpic>; 210 interrupt-parent = <&mpic>;
330 interrupts = <79 2>; 211 interrupts = <3 1>;
331 }; 212 reg = <0x1>;
213 };
332 }; 214 };
333 215
334 gpio: gpio-controller@f000 { 216 mdio@25520 {
335 #gpio-cells = <2>; 217 tbi0: tbi-phy@11 {
336 compatible = "fsl,mpc8572-gpio"; 218 reg = <0x11>;
337 reg = <0xf000 0x100>; 219 device_type = "tbi-phy";
338 interrupts = <47 0x2>; 220 };
339 interrupt-parent = <&mpic>;
340 gpio-controller;
341 }; 221 };
342 222
343 L2: l2-cache-controller@20000 { 223 mdio@26520 {
344 compatible = "fsl,p2020-l2-cache-controller"; 224 status = "disabled";
345 reg = <0x20000 0x1000>;
346 cache-line-size = <32>; // 32 bytes
347 cache-size = <0x80000>; // L2,512K
348 interrupt-parent = <&mpic>;
349 interrupts = <16 2>;
350 }; 225 };
351 226
352 dma@21300 { 227 ptp_clock@24E00 {
353 #address-cells = <1>; 228 compatible = "fsl,etsec-ptp";
354 #size-cells = <1>; 229 reg = <0x24E00 0xB0>;
355 compatible = "fsl,eloplus-dma"; 230 interrupts = <68 2 69 2 70 2>;
356 reg = <0x21300 0x4>; 231 interrupt-parent = < &mpic >;
357 ranges = <0x0 0x21100 0x200>; 232 fsl,tclk-period = <5>;
358 cell-index = <0>; 233 fsl,tmr-prsc = <200>;
359 dma-channel@0 { 234 fsl,tmr-add = <0xCCCCCCCD>;
360 compatible = "fsl,eloplus-dma-channel"; 235 fsl,tmr-fiper1 = <0x3B9AC9FB>;
361 reg = <0x0 0x80>; 236 fsl,tmr-fiper2 = <0x0001869B>;
362 cell-index = <0>; 237 fsl,max-adj = <249999999>;
363 interrupt-parent = <&mpic>;
364 interrupts = <20 2>;
365 };
366 dma-channel@80 {
367 compatible = "fsl,eloplus-dma-channel";
368 reg = <0x80 0x80>;
369 cell-index = <1>;
370 interrupt-parent = <&mpic>;
371 interrupts = <21 2>;
372 };
373 dma-channel@100 {
374 compatible = "fsl,eloplus-dma-channel";
375 reg = <0x100 0x80>;
376 cell-index = <2>;
377 interrupt-parent = <&mpic>;
378 interrupts = <22 2>;
379 };
380 dma-channel@180 {
381 compatible = "fsl,eloplus-dma-channel";
382 reg = <0x180 0x80>;
383 cell-index = <3>;
384 interrupt-parent = <&mpic>;
385 interrupts = <23 2>;
386 };
387 };
388
389 usb@22000 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 compatible = "fsl-usb2-dr";
393 reg = <0x22000 0x1000>;
394 interrupt-parent = <&mpic>;
395 interrupts = <28 0x2>;
396 phy_type = "ulpi";
397 }; 238 };
398 239
399 enet0: ethernet@24000 { 240 enet0: ethernet@24000 {
400 #address-cells = <1>;
401 #size-cells = <1>;
402 cell-index = <0>;
403 device_type = "network";
404 model = "eTSEC";
405 compatible = "gianfar";
406 reg = <0x24000 0x1000>;
407 ranges = <0x0 0x24000 0x1000>;
408 local-mac-address = [ 00 00 00 00 00 00 ];
409 interrupts = <29 2 30 2 34 2>;
410 interrupt-parent = <&mpic>;
411 fixed-link = <1 1 1000 0 0>; 241 fixed-link = <1 1 1000 0 0>;
412 phy-connection-type = "rgmii-id"; 242 phy-connection-type = "rgmii-id";
413
414 mdio@520 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "fsl,gianfar-mdio";
418 reg = <0x520 0x20>;
419
420 phy0: ethernet-phy@0 {
421 interrupt-parent = <&mpic>;
422 interrupts = <3 1>;
423 reg = <0x0>;
424 };
425 phy1: ethernet-phy@1 {
426 interrupt-parent = <&mpic>;
427 interrupts = <3 1>;
428 reg = <0x1>;
429 };
430 };
431 }; 243 };
432 244
433 enet1: ethernet@25000 { 245 enet1: ethernet@25000 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 cell-index = <1>;
437 device_type = "network";
438 model = "eTSEC";
439 compatible = "gianfar";
440 reg = <0x25000 0x1000>;
441 ranges = <0x0 0x25000 0x1000>;
442 local-mac-address = [ 00 00 00 00 00 00 ];
443 interrupts = <35 2 36 2 40 2>;
444 interrupt-parent = <&mpic>;
445 tbi-handle = <&tbi0>; 246 tbi-handle = <&tbi0>;
446 phy-handle = <&phy0>; 247 phy-handle = <&phy0>;
447 phy-connection-type = "sgmii"; 248 phy-connection-type = "sgmii";
448
449 mdio@520 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "fsl,gianfar-tbi";
453 reg = <0x520 0x20>;
454
455 tbi0: tbi-phy@11 {
456 reg = <0x11>;
457 device_type = "tbi-phy";
458 };
459 };
460 }; 249 };
461 250
462 enet2: ethernet@26000 { 251 enet2: ethernet@26000 {
463 #address-cells = <1>;
464 #size-cells = <1>;
465 cell-index = <2>;
466 device_type = "network";
467 model = "eTSEC";
468 compatible = "gianfar";
469 reg = <0x26000 0x1000>;
470 ranges = <0x0 0x26000 0x1000>;
471 local-mac-address = [ 00 00 00 00 00 00 ];
472 interrupts = <31 2 32 2 33 2>;
473 interrupt-parent = <&mpic>;
474 phy-handle = <&phy1>; 252 phy-handle = <&phy1>;
475 phy-connection-type = "rgmii-id"; 253 phy-connection-type = "rgmii-id";
476 }; 254 };
477 255
478 sdhci@2e000 { 256 };
479 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
480 reg = <0x2e000 0x1000>;
481 interrupts = <72 0x2>;
482 interrupt-parent = <&mpic>;
483 /* Filled in by U-Boot */
484 clock-frequency = <0>;
485 };
486
487 crypto@30000 {
488 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
489 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
490 reg = <0x30000 0x10000>;
491 interrupts = <45 2 58 2>;
492 interrupt-parent = <&mpic>;
493 fsl,num-channels = <4>;
494 fsl,channel-fifo-len = <24>;
495 fsl,exec-units-mask = <0xbfe>;
496 fsl,descriptor-types-mask = <0x3ab0ebf>;
497 };
498
499 mpic: pic@40000 {
500 interrupt-controller;
501 #address-cells = <0>;
502 #interrupt-cells = <2>;
503 reg = <0x40000 0x40000>;
504 compatible = "chrp,open-pic";
505 device_type = "open-pic";
506 };
507
508 msi@41600 {
509 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
510 reg = <0x41600 0x80>;
511 msi-available-ranges = <0 0x100>;
512 interrupts = <
513 0xe0 0
514 0xe1 0
515 0xe2 0
516 0xe3 0
517 0xe4 0
518 0xe5 0
519 0xe6 0
520 0xe7 0>;
521 interrupt-parent = <&mpic>;
522 };
523 257
524 global-utilities@e0000 { //global utilities block 258 pci0: pcie@ffe08000 {
525 compatible = "fsl,p2020-guts"; 259 status = "disabled";
526 reg = <0xe0000 0x1000>;
527 fsl,has-rstcr;
528 };
529 }; 260 };
530 261
531 pci0: pcie@ffe09000 { 262 pci1: pcie@ffe09000 {
532 compatible = "fsl,mpc8548-pcie";
533 device_type = "pci";
534 #interrupt-cells = <1>;
535 #size-cells = <2>;
536 #address-cells = <3>;
537 reg = <0 0xffe09000 0 0x1000>;
538 bus-range = <0 255>;
539 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 263 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
540 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 264 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
541 clock-frequency = <33333333>; 265 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
542 interrupt-parent = <&mpic>; 266 interrupt-map = <
543 interrupts = <25 2>; 267 /* IDSEL 0x0 */
544 pcie@0 { 268 0000 0x0 0x0 0x1 &mpic 0x4 0x1
269 0000 0x0 0x0 0x2 &mpic 0x5 0x1
270 0000 0x0 0x0 0x3 &mpic 0x6 0x1
271 0000 0x0 0x0 0x4 &mpic 0x7 0x1
272 >;
273 pcie@0 {
545 reg = <0x0 0x0 0x0 0x0 0x0>; 274 reg = <0x0 0x0 0x0 0x0 0x0>;
546 #size-cells = <2>; 275 #size-cells = <2>;
547 #address-cells = <3>; 276 #address-cells = <3>;
@@ -556,26 +285,24 @@
556 }; 285 };
557 }; 286 };
558 287
559 pci1: pcie@ffe0a000 { 288 pci2: pcie@ffe0a000 {
560 compatible = "fsl,mpc8548-pcie"; 289 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
561 device_type = "pci"; 290 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
562 #interrupt-cells = <1>; 291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
563 #size-cells = <2>; 292 interrupt-map = <
564 #address-cells = <3>; 293 /* IDSEL 0x0 */
565 reg = <0 0xffe0a000 0 0x1000>; 294 0000 0x0 0x0 0x1 &mpic 0x0 0x1
566 bus-range = <0 255>; 295 0000 0x0 0x0 0x2 &mpic 0x1 0x1
567 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 296 0000 0x0 0x0 0x3 &mpic 0x2 0x1
568 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 297 0000 0x0 0x0 0x4 &mpic 0x3 0x1
569 clock-frequency = <33333333>; 298 >;
570 interrupt-parent = <&mpic>;
571 interrupts = <26 2>;
572 pcie@0 { 299 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>; 300 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>; 301 #size-cells = <2>;
575 #address-cells = <3>; 302 #address-cells = <3>;
576 device_type = "pci"; 303 device_type = "pci";
577 ranges = <0x2000000 0x0 0xc0000000 304 ranges = <0x2000000 0x0 0x80000000
578 0x2000000 0x0 0xc0000000 305 0x2000000 0x0 0x80000000
579 0x0 0x20000000 306 0x0 0x20000000
580 307
581 0x1000000 0x0 0x0 308 0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index 0fe93d0c8b2e..fc8ddddfccb6 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -6,7 +6,7 @@
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb, 6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
7 * eth1, eth2, sdhc, crypto, global-util, pci0. 7 * eth1, eth2, sdhc, crypto, global-util, pci0.
8 * 8 *
9 * Copyright 2009 Freescale Semiconductor Inc. 9 * Copyright 2009-2011 Freescale Semiconductor Inc.
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the 12 * under the terms of the GNU General Public License as published by the
@@ -14,12 +14,11 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/dts-v1/; 17/include/ "p2020si.dtsi"
18
18/ { 19/ {
19 model = "fsl,P2020"; 20 model = "fsl,P2020RDB";
20 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
21 #address-cells = <2>;
22 #size-cells = <2>;
23 22
24 aliases { 23 aliases {
25 ethernet1 = &enet1; 24 ethernet1 = &enet1;
@@ -29,91 +28,33 @@
29 }; 28 };
30 29
31 cpus { 30 cpus {
32 #address-cells = <1>; 31 PowerPC,P2020@1 {
33 #size-cells = <0>; 32 status = "disabled";
34
35 PowerPC,P2020@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 }; 33 };
34
40 }; 35 };
41 36
42 memory { 37 memory {
43 device_type = "memory"; 38 device_type = "memory";
44 }; 39 };
45 40
46 soc@ffe00000 { 41 localbus@ffe05000 {
47 #address-cells = <1>; 42 status = "disabled";
48 #size-cells = <1>; 43 };
49 device_type = "soc";
50 compatible = "fsl,p2020-immr", "simple-bus";
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 bus-frequency = <0>; // Filled out by uboot.
53
54 ecm-law@0 {
55 compatible = "fsl,ecm-law";
56 reg = <0x0 0x1000>;
57 fsl,num-laws = <12>;
58 };
59
60 ecm@1000 {
61 compatible = "fsl,p2020-ecm", "fsl,ecm";
62 reg = <0x1000 0x1000>;
63 interrupts = <17 2>;
64 interrupt-parent = <&mpic>;
65 };
66
67 memory-controller@2000 {
68 compatible = "fsl,p2020-memory-controller";
69 reg = <0x2000 0x1000>;
70 interrupt-parent = <&mpic>;
71 interrupts = <18 2>;
72 };
73 44
45 soc@ffe00000 {
74 i2c@3000 { 46 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <43 2>;
81 interrupt-parent = <&mpic>;
82 dfsrr;
83 rtc@68 { 47 rtc@68 {
84 compatible = "dallas,ds1339"; 48 compatible = "dallas,ds1339";
85 reg = <0x68>; 49 reg = <0x68>;
86 }; 50 };
87 }; 51 };
88 52
89 i2c@3100 { 53 serial1: serial@4600 {
90 #address-cells = <1>; 54 status = "disabled";
91 #size-cells = <0>;
92 cell-index = <1>;
93 compatible = "fsl-i2c";
94 reg = <0x3100 0x100>;
95 interrupts = <43 2>;
96 interrupt-parent = <&mpic>;
97 dfsrr;
98 };
99
100 serial0: serial@4500 {
101 cell-index = <0>;
102 device_type = "serial";
103 compatible = "ns16550";
104 reg = <0x4500 0x100>;
105 clock-frequency = <0>;
106 }; 55 };
107 56
108 spi@7000 { 57 spi@7000 {
109 cell-index = <0>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "fsl,espi";
113 reg = <0x7000 0x1000>;
114 interrupts = <59 0x2>;
115 interrupt-parent = <&mpic>;
116 mode = "cpu";
117 58
118 fsl_m25p80@0 { 59 fsl_m25p80@0 {
119 #address-cells = <1>; 60 #address-cells = <1>;
@@ -161,76 +102,15 @@
161 }; 102 };
162 }; 103 };
163 104
164 gpio: gpio-controller@f000 { 105 dma@c300 {
165 #gpio-cells = <2>; 106 status = "disabled";
166 compatible = "fsl,mpc8572-gpio";
167 reg = <0xf000 0x100>;
168 interrupts = <47 0x2>;
169 interrupt-parent = <&mpic>;
170 gpio-controller;
171 };
172
173 L2: l2-cache-controller@20000 {
174 compatible = "fsl,p2020-l2-cache-controller";
175 reg = <0x20000 0x1000>;
176 cache-line-size = <32>; // 32 bytes
177 cache-size = <0x80000>; // L2,512K
178 interrupt-parent = <&mpic>;
179 interrupts = <16 2>;
180 };
181
182 dma@21300 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "fsl,eloplus-dma";
186 reg = <0x21300 0x4>;
187 ranges = <0x0 0x21100 0x200>;
188 cell-index = <0>;
189 dma-channel@0 {
190 compatible = "fsl,eloplus-dma-channel";
191 reg = <0x0 0x80>;
192 cell-index = <0>;
193 interrupt-parent = <&mpic>;
194 interrupts = <20 2>;
195 };
196 dma-channel@80 {
197 compatible = "fsl,eloplus-dma-channel";
198 reg = <0x80 0x80>;
199 cell-index = <1>;
200 interrupt-parent = <&mpic>;
201 interrupts = <21 2>;
202 };
203 dma-channel@100 {
204 compatible = "fsl,eloplus-dma-channel";
205 reg = <0x100 0x80>;
206 cell-index = <2>;
207 interrupt-parent = <&mpic>;
208 interrupts = <22 2>;
209 };
210 dma-channel@180 {
211 compatible = "fsl,eloplus-dma-channel";
212 reg = <0x180 0x80>;
213 cell-index = <3>;
214 interrupt-parent = <&mpic>;
215 interrupts = <23 2>;
216 };
217 }; 107 };
218 108
219 usb@22000 { 109 usb@22000 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl-usb2-dr";
223 reg = <0x22000 0x1000>;
224 interrupt-parent = <&mpic>;
225 interrupts = <28 0x2>;
226 phy_type = "ulpi"; 110 phy_type = "ulpi";
227 }; 111 };
228 112
229 mdio@24520 { 113 mdio@24520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-mdio";
233 reg = <0x24520 0x20>;
234 114
235 phy0: ethernet-phy@0 { 115 phy0: ethernet-phy@0 {
236 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
@@ -245,29 +125,21 @@
245 }; 125 };
246 126
247 mdio@25520 { 127 mdio@25520 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,gianfar-tbi";
251 reg = <0x26520 0x20>;
252
253 tbi0: tbi-phy@11 { 128 tbi0: tbi-phy@11 {
254 reg = <0x11>; 129 reg = <0x11>;
255 device_type = "tbi-phy"; 130 device_type = "tbi-phy";
256 }; 131 };
257 }; 132 };
258 133
134 mdio@26520 {
135 status = "disabled";
136 };
137
138 enet0: ethernet@24000 {
139 status = "disabled";
140 };
141
259 enet1: ethernet@25000 { 142 enet1: ethernet@25000 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 cell-index = <1>;
263 device_type = "network";
264 model = "eTSEC";
265 compatible = "gianfar";
266 reg = <0x25000 0x1000>;
267 ranges = <0x0 0x25000 0x1000>;
268 local-mac-address = [ 00 00 00 00 00 00 ];
269 interrupts = <35 2 36 2 40 2>;
270 interrupt-parent = <&mpic>;
271 tbi-handle = <&tbi0>; 143 tbi-handle = <&tbi0>;
272 phy-handle = <&phy0>; 144 phy-handle = <&phy0>;
273 phy-connection-type = "sgmii"; 145 phy-connection-type = "sgmii";
@@ -275,49 +147,12 @@
275 }; 147 };
276 148
277 enet2: ethernet@26000 { 149 enet2: ethernet@26000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 ranges = <0x0 0x26000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <31 2 32 2 33 2>;
288 interrupt-parent = <&mpic>;
289 phy-handle = <&phy1>; 150 phy-handle = <&phy1>;
290 phy-connection-type = "rgmii-id"; 151 phy-connection-type = "rgmii-id";
291 }; 152 };
292 153
293 sdhci@2e000 {
294 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
295 reg = <0x2e000 0x1000>;
296 interrupts = <72 0x2>;
297 interrupt-parent = <&mpic>;
298 /* Filled in by U-Boot */
299 clock-frequency = <0>;
300 };
301
302 crypto@30000 {
303 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
304 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
305 reg = <0x30000 0x10000>;
306 interrupts = <45 2 58 2>;
307 interrupt-parent = <&mpic>;
308 fsl,num-channels = <4>;
309 fsl,channel-fifo-len = <24>;
310 fsl,exec-units-mask = <0xbfe>;
311 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 };
313 154
314 mpic: pic@40000 { 155 mpic: pic@40000 {
315 interrupt-controller;
316 #address-cells = <0>;
317 #interrupt-cells = <2>;
318 reg = <0x40000 0x40000>;
319 compatible = "chrp,open-pic";
320 device_type = "open-pic";
321 protected-sources = < 156 protected-sources = <
322 42 76 77 78 79 /* serial1 , dma2 */ 157 42 76 77 78 79 /* serial1 , dma2 */
323 29 30 34 26 /* enet0, pci1 */ 158 29 30 34 26 /* enet0, pci1 */
@@ -326,26 +161,28 @@
326 >; 161 >;
327 }; 162 };
328 163
329 global-utilities@e0000 { 164 msi@41600 {
330 compatible = "fsl,p2020-guts"; 165 status = "disabled";
331 reg = <0xe0000 0x1000>;
332 fsl,has-rstcr;
333 }; 166 };
167
168
334 }; 169 };
335 170
336 pci0: pcie@ffe09000 { 171 pci0: pcie@ffe08000 {
337 compatible = "fsl,mpc8548-pcie"; 172 status = "disabled";
338 device_type = "pci"; 173 };
339 #interrupt-cells = <1>; 174
340 #size-cells = <2>; 175 pci1: pcie@ffe09000 {
341 #address-cells = <3>;
342 reg = <0 0xffe09000 0 0x1000>;
343 bus-range = <0 255>;
344 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 176 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
345 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 177 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
346 clock-frequency = <33333333>; 178 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
347 interrupt-parent = <&mpic>; 179 interrupt-map = <
348 interrupts = <25 2>; 180 /* IDSEL 0x0 */
181 0000 0x0 0x0 0x1 &mpic 0x4 0x1
182 0000 0x0 0x0 0x2 &mpic 0x5 0x1
183 0000 0x0 0x0 0x3 &mpic 0x6 0x1
184 0000 0x0 0x0 0x4 &mpic 0x7 0x1
185 >;
349 pcie@0 { 186 pcie@0 {
350 reg = <0x0 0x0 0x0 0x0 0x0>; 187 reg = <0x0 0x0 0x0 0x0 0x0>;
351 #size-cells = <2>; 188 #size-cells = <2>;
@@ -360,4 +197,8 @@
360 0x0 0x100000>; 197 0x0 0x100000>;
361 }; 198 };
362 }; 199 };
200
201 pci2: pcie@ffe0a000 {
202 status = "disabled";
203 };
363}; 204};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index e95a51285328..261c34ba45ec 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -7,7 +7,7 @@
7 * 7 *
8 * Please note to add "-b 1" for core1's dts compiling. 8 * Please note to add "-b 1" for core1's dts compiling.
9 * 9 *
10 * Copyright 2009 Freescale Semiconductor Inc. 10 * Copyright 2009-2011 Freescale Semiconductor Inc.
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -15,27 +15,21 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/dts-v1/; 18/include/ "p2020si.dtsi"
19
19/ { 20/ {
20 model = "fsl,P2020"; 21 model = "fsl,P2020RDB";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22 #address-cells = <2>;
23 #size-cells = <2>;
24 23
25 aliases { 24 aliases {
26 ethernet0 = &enet0; 25 ethernet0 = &enet0;
27 serial0 = &serial0; 26 serial0 = &serial1;
28 pci1 = &pci1; 27 pci1 = &pci1;
29 }; 28 };
30 29
31 cpus { 30 cpus {
32 #address-cells = <1>; 31 PowerPC,P2020@0 {
33 #size-cells = <0>; 32 status = "disabled";
34
35 PowerPC,P2020@1 {
36 device_type = "cpu";
37 reg = <0x1>;
38 next-level-cache = <&L2>;
39 }; 33 };
40 }; 34 };
41 35
@@ -43,20 +37,37 @@
43 device_type = "memory"; 37 device_type = "memory";
44 }; 38 };
45 39
40 localbus@ffe05000 {
41 status = "disabled";
42 };
43
46 soc@ffe00000 { 44 soc@ffe00000 {
47 #address-cells = <1>; 45 ecm-law@0 {
48 #size-cells = <1>; 46 status = "disabled";
49 device_type = "soc"; 47 };
50 compatible = "fsl,p2020-immr", "simple-bus"; 48
51 ranges = <0x0 0x0 0xffe00000 0x100000>; 49 ecm@1000 {
52 bus-frequency = <0>; // Filled out by uboot. 50 status = "disabled";
53 51 };
54 serial0: serial@4600 { 52
55 cell-index = <1>; 53 memory-controller@2000 {
56 device_type = "serial"; 54 status = "disabled";
57 compatible = "ns16550"; 55 };
58 reg = <0x4600 0x100>; 56
59 clock-frequency = <0>; 57 i2c@3000 {
58 status = "disabled";
59 };
60
61 i2c@3100 {
62 status = "disabled";
63 };
64
65 serial0: serial@4500 {
66 status = "disabled";
67 };
68
69 spi@7000 {
70 status = "disabled";
60 }; 71 };
61 72
62 dma@c300 { 73 dma@c300 {
@@ -96,6 +107,10 @@
96 }; 107 };
97 }; 108 };
98 109
110 gpio: gpio-controller@f000 {
111 status = "disabled";
112 };
113
99 L2: l2-cache-controller@20000 { 114 L2: l2-cache-controller@20000 {
100 compatible = "fsl,p2020-l2-cache-controller"; 115 compatible = "fsl,p2020-l2-cache-controller";
101 reg = <0x20000 0x1000>; 116 reg = <0x20000 0x1000>;
@@ -104,31 +119,49 @@
104 interrupt-parent = <&mpic>; 119 interrupt-parent = <&mpic>;
105 }; 120 };
106 121
122 dma@21300 {
123 status = "disabled";
124 };
125
126 usb@22000 {
127 status = "disabled";
128 };
129
130 mdio@24520 {
131 status = "disabled";
132 };
133
134 mdio@25520 {
135 status = "disabled";
136 };
137
138 mdio@26520 {
139 status = "disabled";
140 };
107 141
108 enet0: ethernet@24000 { 142 enet0: ethernet@24000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 cell-index = <0>;
112 device_type = "network";
113 model = "eTSEC";
114 compatible = "gianfar";
115 reg = <0x24000 0x1000>;
116 ranges = <0x0 0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>;
120 fixed-link = <1 1 1000 0 0>; 143 fixed-link = <1 1 1000 0 0>;
121 phy-connection-type = "rgmii-id"; 144 phy-connection-type = "rgmii-id";
122 145
123 }; 146 };
124 147
148 enet1: ethernet@25000 {
149 status = "disabled";
150 };
151
152 enet2: ethernet@26000 {
153 status = "disabled";
154 };
155
156 sdhci@2e000 {
157 status = "disabled";
158 };
159
160 crypto@30000 {
161 status = "disabled";
162 };
163
125 mpic: pic@40000 { 164 mpic: pic@40000 {
126 interrupt-controller;
127 #address-cells = <0>;
128 #interrupt-cells = <2>;
129 reg = <0x40000 0x40000>;
130 compatible = "chrp,open-pic";
131 device_type = "open-pic";
132 protected-sources = < 165 protected-sources = <
133 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */ 166 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
134 16 20 21 22 23 28 /* L2, dma1, USB */ 167 16 20 21 22 23 28 /* L2, dma1, USB */
@@ -152,28 +185,39 @@
152 0xe7 0>; 185 0xe7 0>;
153 interrupt-parent = <&mpic>; 186 interrupt-parent = <&mpic>;
154 }; 187 };
188
189 global-utilities@e0000 { //global utilities block
190 status = "disabled";
191 };
192
155 }; 193 };
156 194
157 pci1: pcie@ffe0a000 { 195 pci0: pcie@ffe08000 {
158 compatible = "fsl,mpc8548-pcie"; 196 status = "disabled";
159 device_type = "pci"; 197 };
160 #interrupt-cells = <1>; 198
161 #size-cells = <2>; 199 pci1: pcie@ffe09000 {
162 #address-cells = <3>; 200 status = "disabled";
163 reg = <0 0xffe0a000 0 0x1000>; 201 };
164 bus-range = <0 255>; 202
165 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 203 pci2: pcie@ffe0a000 {
166 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 204 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
167 clock-frequency = <33333333>; 205 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
168 interrupt-parent = <&mpic>; 206 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
169 interrupts = <26 2>; 207 interrupt-map = <
208 /* IDSEL 0x0 */
209 0000 0x0 0x0 0x1 &mpic 0x0 0x1
210 0000 0x0 0x0 0x2 &mpic 0x1 0x1
211 0000 0x0 0x0 0x3 &mpic 0x2 0x1
212 0000 0x0 0x0 0x4 &mpic 0x3 0x1
213 >;
170 pcie@0 { 214 pcie@0 {
171 reg = <0x0 0x0 0x0 0x0 0x0>; 215 reg = <0x0 0x0 0x0 0x0 0x0>;
172 #size-cells = <2>; 216 #size-cells = <2>;
173 #address-cells = <3>; 217 #address-cells = <3>;
174 device_type = "pci"; 218 device_type = "pci";
175 ranges = <0x2000000 0x0 0xc0000000 219 ranges = <0x2000000 0x0 0x80000000
176 0x2000000 0x0 0xc0000000 220 0x2000000 0x0 0x80000000
177 0x0 0x20000000 221 0x0 0x20000000
178 222
179 0x1000000 0x0 0x0 223 0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
new file mode 100644
index 000000000000..6def17f265d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020si.dtsi
@@ -0,0 +1,382 @@
1/*
2 * P2020 Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P2020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P2020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P2020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p2020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p2020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <17 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p2020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <18 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 dma@c300 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,eloplus-dma";
129 reg = <0xc300 0x4>;
130 ranges = <0x0 0xc100 0x200>;
131 cell-index = <1>;
132 dma-channel@0 {
133 compatible = "fsl,eloplus-dma-channel";
134 reg = <0x0 0x80>;
135 cell-index = <0>;
136 interrupt-parent = <&mpic>;
137 interrupts = <76 2>;
138 };
139 dma-channel@80 {
140 compatible = "fsl,eloplus-dma-channel";
141 reg = <0x80 0x80>;
142 cell-index = <1>;
143 interrupt-parent = <&mpic>;
144 interrupts = <77 2>;
145 };
146 dma-channel@100 {
147 compatible = "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>;
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
151 interrupts = <78 2>;
152 };
153 dma-channel@180 {
154 compatible = "fsl,eloplus-dma-channel";
155 reg = <0x180 0x80>;
156 cell-index = <3>;
157 interrupt-parent = <&mpic>;
158 interrupts = <79 2>;
159 };
160 };
161
162 gpio: gpio-controller@f000 {
163 #gpio-cells = <2>;
164 compatible = "fsl,mpc8572-gpio";
165 reg = <0xf000 0x100>;
166 interrupts = <47 0x2>;
167 interrupt-parent = <&mpic>;
168 gpio-controller;
169 };
170
171 L2: l2-cache-controller@20000 {
172 compatible = "fsl,p2020-l2-cache-controller";
173 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x80000>; // L2,512K
176 interrupt-parent = <&mpic>;
177 interrupts = <16 2>;
178 };
179
180 dma@21300 {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 compatible = "fsl,eloplus-dma";
184 reg = <0x21300 0x4>;
185 ranges = <0x0 0x21100 0x200>;
186 cell-index = <0>;
187 dma-channel@0 {
188 compatible = "fsl,eloplus-dma-channel";
189 reg = <0x0 0x80>;
190 cell-index = <0>;
191 interrupt-parent = <&mpic>;
192 interrupts = <20 2>;
193 };
194 dma-channel@80 {
195 compatible = "fsl,eloplus-dma-channel";
196 reg = <0x80 0x80>;
197 cell-index = <1>;
198 interrupt-parent = <&mpic>;
199 interrupts = <21 2>;
200 };
201 dma-channel@100 {
202 compatible = "fsl,eloplus-dma-channel";
203 reg = <0x100 0x80>;
204 cell-index = <2>;
205 interrupt-parent = <&mpic>;
206 interrupts = <22 2>;
207 };
208 dma-channel@180 {
209 compatible = "fsl,eloplus-dma-channel";
210 reg = <0x180 0x80>;
211 cell-index = <3>;
212 interrupt-parent = <&mpic>;
213 interrupts = <23 2>;
214 };
215 };
216
217 usb@22000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl-usb2-dr";
221 reg = <0x22000 0x1000>;
222 interrupt-parent = <&mpic>;
223 interrupts = <28 0x2>;
224 };
225
226 mdio@24520 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,gianfar-mdio";
230 reg = <0x24520 0x20>;
231 };
232
233 mdio@25520 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "fsl,gianfar-tbi";
237 reg = <0x26520 0x20>;
238 };
239
240 mdio@26520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-tbi";
244 reg = <0x520 0x20>;
245 };
246
247 enet0: ethernet@24000 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 cell-index = <0>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "gianfar";
254 reg = <0x24000 0x1000>;
255 ranges = <0x0 0x24000 0x1000>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupts = <29 2 30 2 34 2>;
258 interrupt-parent = <&mpic>;
259 };
260
261 enet1: ethernet@25000 {
262 #address-cells = <1>;
263 #size-cells = <1>;
264 cell-index = <1>;
265 device_type = "network";
266 model = "eTSEC";
267 compatible = "gianfar";
268 reg = <0x25000 0x1000>;
269 ranges = <0x0 0x25000 0x1000>;
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 interrupts = <35 2 36 2 40 2>;
272 interrupt-parent = <&mpic>;
273
274 };
275
276 enet2: ethernet@26000 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 cell-index = <2>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "gianfar";
283 reg = <0x26000 0x1000>;
284 ranges = <0x0 0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <31 2 32 2 33 2>;
287 interrupt-parent = <&mpic>;
288
289 };
290
291 sdhci@2e000 {
292 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
293 reg = <0x2e000 0x1000>;
294 interrupts = <72 0x2>;
295 interrupt-parent = <&mpic>;
296 /* Filled in by U-Boot */
297 clock-frequency = <0>;
298 };
299
300 crypto@30000 {
301 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
302 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
303 reg = <0x30000 0x10000>;
304 interrupts = <45 2 58 2>;
305 interrupt-parent = <&mpic>;
306 fsl,num-channels = <4>;
307 fsl,channel-fifo-len = <24>;
308 fsl,exec-units-mask = <0xbfe>;
309 fsl,descriptor-types-mask = <0x3ab0ebf>;
310 };
311
312 mpic: pic@40000 {
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <2>;
316 reg = <0x40000 0x40000>;
317 compatible = "chrp,open-pic";
318 device_type = "open-pic";
319 };
320
321 msi@41600 {
322 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
323 reg = <0x41600 0x80>;
324 msi-available-ranges = <0 0x100>;
325 interrupts = <
326 0xe0 0
327 0xe1 0
328 0xe2 0
329 0xe3 0
330 0xe4 0
331 0xe5 0
332 0xe6 0
333 0xe7 0>;
334 interrupt-parent = <&mpic>;
335 };
336
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,p2020-guts";
339 reg = <0xe0000 0x1000>;
340 fsl,has-rstcr;
341 };
342 };
343
344 pci0: pcie@ffe08000 {
345 compatible = "fsl,mpc8548-pcie";
346 device_type = "pci";
347 #interrupt-cells = <1>;
348 #size-cells = <2>;
349 #address-cells = <3>;
350 reg = <0 0xffe08000 0 0x1000>;
351 bus-range = <0 255>;
352 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>;
354 interrupts = <24 2>;
355 };
356
357 pci1: pcie@ffe09000 {
358 compatible = "fsl,mpc8548-pcie";
359 device_type = "pci";
360 #interrupt-cells = <1>;
361 #size-cells = <2>;
362 #address-cells = <3>;
363 reg = <0 0xffe09000 0 0x1000>;
364 bus-range = <0 255>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <25 2>;
368 };
369
370 pci2: pcie@ffe0a000 {
371 compatible = "fsl,mpc8548-pcie";
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <0 0xffe0a000 0 0x1000>;
377 bus-range = <0 255>;
378 clock-frequency = <33333333>;
379 interrupt-parent = <&mpic>;
380 interrupts = <26 2>;
381 };
382};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 2f0de24e3822..927f94d16e9b 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P4080DS Device Tree Source 2 * P4080DS Device Tree Source
3 * 3 *
4 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -33,6 +33,17 @@
33 dma1 = &dma1; 33 dma1 = &dma1;
34 sdhc = &sdhc; 34 sdhc = &sdhc;
35 35
36 crypto = &crypto;
37 sec_jr0 = &sec_jr0;
38 sec_jr1 = &sec_jr1;
39 sec_jr2 = &sec_jr2;
40 sec_jr3 = &sec_jr3;
41 rtic_a = &rtic_a;
42 rtic_b = &rtic_b;
43 rtic_c = &rtic_c;
44 rtic_d = &rtic_d;
45 sec_mon = &sec_mon;
46
36 rio0 = &rapidio0; 47 rio0 = &rapidio0;
37 }; 48 };
38 49
@@ -236,22 +247,19 @@
236 }; 247 };
237 248
238 spi@110000 { 249 spi@110000 {
239 cell-index = <0>;
240 #address-cells = <1>; 250 #address-cells = <1>;
241 #size-cells = <0>; 251 #size-cells = <0>;
242 compatible = "fsl,espi"; 252 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
243 reg = <0x110000 0x1000>; 253 reg = <0x110000 0x1000>;
244 interrupts = <53 0x2>; 254 interrupts = <53 0x2>;
245 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
246 espi,num-ss-bits = <4>; 256 fsl,espi-num-chipselects = <4>;
247 mode = "cpu";
248 257
249 fsl_m25p80@0 { 258 flash@0 {
250 #address-cells = <1>; 259 #address-cells = <1>;
251 #size-cells = <1>; 260 #size-cells = <1>;
252 compatible = "fsl,espi-flash"; 261 compatible = "spansion,s25sl12801";
253 reg = <0>; 262 reg = <0>;
254 linux,modalias = "fsl_m25p80";
255 spi-max-frequency = <40000000>; /* input clock */ 263 spi-max-frequency = <40000000>; /* input clock */
256 partition@u-boot { 264 partition@u-boot {
257 label = "u-boot"; 265 label = "u-boot";
@@ -413,6 +421,79 @@
413 dr_mode = "host"; 421 dr_mode = "host";
414 phy_type = "ulpi"; 422 phy_type = "ulpi";
415 }; 423 };
424
425 crypto: crypto@300000 {
426 compatible = "fsl,sec-v4.0";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 reg = <0x300000 0x10000>;
430 ranges = <0 0x300000 0x10000>;
431 interrupt-parent = <&mpic>;
432 interrupts = <92 2>;
433
434 sec_jr0: jr@1000 {
435 compatible = "fsl,sec-v4.0-job-ring";
436 reg = <0x1000 0x1000>;
437 interrupt-parent = <&mpic>;
438 interrupts = <88 2>;
439 };
440
441 sec_jr1: jr@2000 {
442 compatible = "fsl,sec-v4.0-job-ring";
443 reg = <0x2000 0x1000>;
444 interrupt-parent = <&mpic>;
445 interrupts = <89 2>;
446 };
447
448 sec_jr2: jr@3000 {
449 compatible = "fsl,sec-v4.0-job-ring";
450 reg = <0x3000 0x1000>;
451 interrupt-parent = <&mpic>;
452 interrupts = <90 2>;
453 };
454
455 sec_jr3: jr@4000 {
456 compatible = "fsl,sec-v4.0-job-ring";
457 reg = <0x4000 0x1000>;
458 interrupt-parent = <&mpic>;
459 interrupts = <91 2>;
460 };
461
462 rtic@6000 {
463 compatible = "fsl,sec-v4.0-rtic";
464 #address-cells = <1>;
465 #size-cells = <1>;
466 reg = <0x6000 0x100>;
467 ranges = <0x0 0x6100 0xe00>;
468
469 rtic_a: rtic-a@0 {
470 compatible = "fsl,sec-v4.0-rtic-memory";
471 reg = <0x00 0x20 0x100 0x80>;
472 };
473
474 rtic_b: rtic-b@20 {
475 compatible = "fsl,sec-v4.0-rtic-memory";
476 reg = <0x20 0x20 0x200 0x80>;
477 };
478
479 rtic_c: rtic-c@40 {
480 compatible = "fsl,sec-v4.0-rtic-memory";
481 reg = <0x40 0x20 0x300 0x80>;
482 };
483
484 rtic_d: rtic-d@60 {
485 compatible = "fsl,sec-v4.0-rtic-memory";
486 reg = <0x60 0x20 0x500 0x80>;
487 };
488 };
489 };
490
491 sec_mon: sec_mon@314000 {
492 compatible = "fsl,sec-v4.0-mon";
493 reg = <0x314000 0x1000>;
494 interrupt-parent = <&mpic>;
495 interrupts = <93 2>;
496 };
416 }; 497 };
417 498
418 rapidio0: rapidio@ffe0c0000 { 499 rapidio0: rapidio@ffe0c0000 {
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 8a4ec30b21ae..9e354997eb7e 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -12,246 +12,92 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15/dts-v1/; 15/include/ "mpc5200b.dtsi"
16 16
17/ { 17/ {
18 model = "phytec,pcm030"; 18 model = "phytec,pcm030";
19 compatible = "phytec,pcm030"; 19 compatible = "phytec,pcm030";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5200@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <0x4000>; // L1, 16K
34 i-cache-size = <0x4000>; // L1, 16K
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x04000000>; // 64MB
44 };
45 20
46 soc5200@f0000000 { 21 soc5200@f0000000 {
47 #address-cells = <1>; 22 timer@600 { // General Purpose Timer
48 #size-cells = <1>;
49 compatible = "fsl,mpc5200b-immr";
50 ranges = <0 0xf0000000 0x0000c000>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt; 23 fsl,has-wdt;
72 }; 24 };
73 25
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 gpt2: timer@620 { // General Purpose Timer in GPIO mode 26 gpt2: timer@620 { // General Purpose Timer in GPIO mode
81 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 27 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 gpio-controller; 28 gpio-controller;
85 #gpio-cells = <2>; 29 #gpio-cells = <2>;
86 }; 30 };
87 31
88 gpt3: timer@630 { // General Purpose Timer in GPIO mode 32 gpt3: timer@630 { // General Purpose Timer in GPIO mode
89 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 33 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
90 reg = <0x630 0x10>;
91 interrupts = <1 12 0>;
92 gpio-controller; 34 gpio-controller;
93 #gpio-cells = <2>; 35 #gpio-cells = <2>;
94 }; 36 };
95 37
96 gpt4: timer@640 { // General Purpose Timer in GPIO mode 38 gpt4: timer@640 { // General Purpose Timer in GPIO mode
97 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 39 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
98 reg = <0x640 0x10>;
99 interrupts = <1 13 0>;
100 gpio-controller; 40 gpio-controller;
101 #gpio-cells = <2>; 41 #gpio-cells = <2>;
102 }; 42 };
103 43
104 gpt5: timer@650 { // General Purpose Timer in GPIO mode 44 gpt5: timer@650 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 45 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 reg = <0x650 0x10>;
107 interrupts = <1 14 0>;
108 gpio-controller; 46 gpio-controller;
109 #gpio-cells = <2>; 47 #gpio-cells = <2>;
110 }; 48 };
111 49
112 gpt6: timer@660 { // General Purpose Timer in GPIO mode 50 gpt6: timer@660 { // General Purpose Timer in GPIO mode
113 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 51 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
114 reg = <0x660 0x10>;
115 interrupts = <1 15 0>;
116 gpio-controller; 52 gpio-controller;
117 #gpio-cells = <2>; 53 #gpio-cells = <2>;
118 }; 54 };
119 55
120 gpt7: timer@670 { // General Purpose Timer in GPIO mode 56 gpt7: timer@670 { // General Purpose Timer in GPIO mode
121 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 57 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
122 reg = <0x670 0x10>;
123 interrupts = <1 16 0>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 };
127
128 rtc@800 { // Real time clock
129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
130 reg = <0x800 0x100>;
131 interrupts = <1 5 0 1 6 0>;
132 };
133
134 can@900 {
135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
136 interrupts = <2 17 0>;
137 reg = <0x900 0x80>;
138 };
139
140 can@980 {
141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
142 interrupts = <2 18 0>;
143 reg = <0x980 0x80>;
144 };
145
146 gpio_simple: gpio@b00 {
147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
148 reg = <0xb00 0x40>;
149 interrupts = <1 7 0>;
150 gpio-controller; 58 gpio-controller;
151 #gpio-cells = <2>; 59 #gpio-cells = <2>;
152 }; 60 };
153 61
154 gpio_wkup: gpio@c00 { 62 psc@2000 { /* PSC1 in ac97 mode */
155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
156 reg = <0xc00 0x40>;
157 interrupts = <1 8 0 0 3 0>;
158 gpio-controller;
159 #gpio-cells = <2>;
160 };
161
162 spi@f00 {
163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
164 reg = <0xf00 0x20>;
165 interrupts = <2 13 0 2 14 0>;
166 };
167
168 usb@1000 {
169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
170 reg = <0x1000 0xff>;
171 interrupts = <2 6 0>;
172 };
173
174 dma-controller@1200 {
175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
176 reg = <0x1200 0x80>;
177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
178 3 4 0 3 5 0 3 6 0 3 7 0
179 3 8 0 3 9 0 3 10 0 3 11 0
180 3 12 0 3 13 0 3 14 0 3 15 0>;
181 };
182
183 xlb@1f00 {
184 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
185 reg = <0x1f00 0x100>;
186 };
187
188 ac97@2000 { /* PSC1 in ac97 mode */
189 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 63 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
190 cell-index = <0>; 64 cell-index = <0>;
191 reg = <0x2000 0x100>;
192 interrupts = <2 1 0>;
193 }; 65 };
194 66
195 /* PSC2 port is used by CAN1/2 */ 67 /* PSC2 port is used by CAN1/2 */
68 psc@2200 {
69 status = "disabled";
70 };
196 71
197 serial@2400 { /* PSC3 in UART mode */ 72 psc@2400 { /* PSC3 in UART mode */
198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 73 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
199 cell-index = <2>;
200 reg = <0x2400 0x100>;
201 interrupts = <2 3 0>;
202 }; 74 };
203 75
204 /* PSC4 is ??? */ 76 /* PSC4 is ??? */
77 psc@2600 {
78 status = "disabled";
79 };
205 80
206 /* PSC5 is ??? */ 81 /* PSC5 is ??? */
82 psc@2800 {
83 status = "disabled";
84 };
207 85
208 serial@2c00 { /* PSC6 in UART mode */ 86 psc@2c00 { /* PSC6 in UART mode */
209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 87 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
210 cell-index = <5>;
211 reg = <0x2c00 0x100>;
212 interrupts = <2 4 0>;
213 }; 88 };
214 89
215 ethernet@3000 { 90 ethernet@3000 {
216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
217 reg = <0x3000 0x400>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <2 5 0>;
220 phy-handle = <&phy0>; 91 phy-handle = <&phy0>;
221 }; 92 };
222 93
223 mdio@3000 { 94 mdio@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
229
230 phy0: ethernet-phy@0 { 95 phy0: ethernet-phy@0 {
231 reg = <0>; 96 reg = <0>;
232 }; 97 };
233 }; 98 };
234 99
235 ata@3a00 {
236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
237 reg = <0x3a00 0x100>;
238 interrupts = <2 7 0>;
239 };
240
241 i2c@3d00 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d00 0x40>;
246 interrupts = <2 15 0>;
247 };
248
249 i2c@3d40 { 100 i2c@3d40 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
253 reg = <0x3d40 0x40>;
254 interrupts = <2 16 0>;
255 rtc@51 { 101 rtc@51 {
256 compatible = "nxp,pcf8563"; 102 compatible = "nxp,pcf8563";
257 reg = <0x51>; 103 reg = <0x51>;
@@ -259,6 +105,7 @@
259 eeprom@52 { 105 eeprom@52 {
260 compatible = "catalyst,24c32"; 106 compatible = "catalyst,24c32";
261 reg = <0x52>; 107 reg = <0x52>;
108 pagesize = <32>;
262 }; 109 };
263 }; 110 };
264 111
@@ -269,12 +116,6 @@
269 }; 116 };
270 117
271 pci@f0000d00 { 118 pci@f0000d00 {
272 #interrupt-cells = <1>;
273 #size-cells = <2>;
274 #address-cells = <3>;
275 device_type = "pci";
276 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
277 reg = <0xf0000d00 0x100>;
278 interrupt-map-mask = <0xf800 0 0 7>; 119 interrupt-map-mask = <0xf800 0 0 7>;
279 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 120 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
280 0xc000 0 0 2 &mpc5200_pic 1 1 3 121 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -285,11 +126,12 @@
285 0xc800 0 0 2 &mpc5200_pic 1 2 3 126 0xc800 0 0 2 &mpc5200_pic 1 2 3
286 0xc800 0 0 3 &mpc5200_pic 1 3 3 127 0xc800 0 0 3 &mpc5200_pic 1 3 3
287 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 128 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
288 clock-frequency = <0>; // From boot loader
289 interrupts = <2 8 0 2 9 0 2 10 0>;
290 bus-range = <0 0>;
291 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 129 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
292 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 130 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
293 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 131 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
294 }; 132 };
133
134 localbus {
135 status = "disabled";
136 };
295}; 137};
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 85d857a5d46e..1dd478bfff96 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -12,99 +12,37 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15/dts-v1/; 15/include/ "mpc5200b.dtsi"
16 16
17/ { 17/ {
18 model = "phytec,pcm032"; 18 model = "phytec,pcm032";
19 compatible = "phytec,pcm032"; 19 compatible = "phytec,pcm032";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5200@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <0x4000>; // L1, 16K
34 i-cache-size = <0x4000>; // L1, 16K
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
38 };
39 };
40 20
41 memory { 21 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x08000000>; // 128MB 22 reg = <0x00000000 0x08000000>; // 128MB
44 }; 23 };
45 24
46 soc5200@f0000000 { 25 soc5200@f0000000 {
47 #address-cells = <1>; 26 timer@600 { // General Purpose Timer
48 #size-cells = <1>;
49 compatible = "fsl,mpc5200b-immr";
50 ranges = <0 0xf0000000 0x0000c000>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt; 27 fsl,has-wdt;
72 }; 28 };
73 29
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 gpt2: timer@620 { // General Purpose Timer in GPIO mode 30 gpt2: timer@620 { // General Purpose Timer in GPIO mode
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 gpio-controller; 31 gpio-controller;
85 #gpio-cells = <2>; 32 #gpio-cells = <2>;
86 }; 33 };
87 34
88 gpt3: timer@630 { // General Purpose Timer in GPIO mode 35 gpt3: timer@630 { // General Purpose Timer in GPIO mode
89 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
90 reg = <0x630 0x10>;
91 interrupts = <1 12 0>;
92 gpio-controller; 36 gpio-controller;
93 #gpio-cells = <2>; 37 #gpio-cells = <2>;
94 }; 38 };
95 39
96 gpt4: timer@640 { // General Purpose Timer in GPIO mode 40 gpt4: timer@640 { // General Purpose Timer in GPIO mode
97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
98 reg = <0x640 0x10>;
99 interrupts = <1 13 0>;
100 gpio-controller; 41 gpio-controller;
101 #gpio-cells = <2>; 42 #gpio-cells = <2>;
102 }; 43 };
103 44
104 gpt5: timer@650 { // General Purpose Timer in GPIO mode 45 gpt5: timer@650 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x650 0x10>;
107 interrupts = <1 14 0>;
108 gpio-controller; 46 gpio-controller;
109 #gpio-cells = <2>; 47 #gpio-cells = <2>;
110 }; 48 };
@@ -118,163 +56,62 @@
118 }; 56 };
119 57
120 gpt7: timer@670 { // General Purpose Timer in GPIO mode 58 gpt7: timer@670 { // General Purpose Timer in GPIO mode
121 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
122 reg = <0x670 0x10>;
123 interrupts = <1 16 0>;
124 gpio-controller; 59 gpio-controller;
125 #gpio-cells = <2>; 60 #gpio-cells = <2>;
126 }; 61 };
127 62
128 rtc@800 { // Real time clock 63 psc@2000 { /* PSC1 is ac97 */
129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
130 reg = <0x800 0x100>;
131 interrupts = <1 5 0 1 6 0>;
132 };
133
134 can@900 {
135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
136 interrupts = <2 17 0>;
137 reg = <0x900 0x80>;
138 };
139
140 can@980 {
141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
142 interrupts = <2 18 0>;
143 reg = <0x980 0x80>;
144 };
145
146 gpio_simple: gpio@b00 {
147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
148 reg = <0xb00 0x40>;
149 interrupts = <1 7 0>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 gpio_wkup: gpio@c00 {
155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
156 reg = <0xc00 0x40>;
157 interrupts = <1 8 0 0 3 0>;
158 gpio-controller;
159 #gpio-cells = <2>;
160 };
161
162 spi@f00 {
163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
164 reg = <0xf00 0x20>;
165 interrupts = <2 13 0 2 14 0>;
166 };
167
168 usb@1000 {
169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
170 reg = <0x1000 0xff>;
171 interrupts = <2 6 0>;
172 };
173
174 dma-controller@1200 {
175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
176 reg = <0x1200 0x80>;
177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
178 3 4 0 3 5 0 3 6 0 3 7 0
179 3 8 0 3 9 0 3 10 0 3 11 0
180 3 12 0 3 13 0 3 14 0 3 15 0>;
181 };
182
183 xlb@1f00 {
184 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
185 reg = <0x1f00 0x100>;
186 };
187
188 ac97@2000 { /* PSC1 is ac97 */
189 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 64 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
190 cell-index = <0>; 65 cell-index = <0>;
191 reg = <0x2000 0x100>;
192 interrupts = <2 1 0>;
193 }; 66 };
194 67
195 /* PSC2 port is used by CAN1/2 */ 68 /* PSC2 port is used by CAN1/2 */
69 psc@2200 {
70 status = "disabled";
71 };
196 72
197 serial@2400 { /* PSC3 in UART mode */ 73 psc@2400 { /* PSC3 in UART mode */
198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 74 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
199 cell-index = <2>;
200 reg = <0x2400 0x100>;
201 interrupts = <2 3 0>;
202 }; 75 };
203 76
204 /* PSC4 is ??? */ 77 /* PSC4 is ??? */
78 psc@2600 {
79 status = "disabled";
80 };
205 81
206 /* PSC5 is ??? */ 82 /* PSC5 is ??? */
83 psc@2800 {
84 status = "disabled";
85 };
207 86
208 serial@2c00 { /* PSC6 in UART mode */ 87 psc@2c00 { /* PSC6 in UART mode */
209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 88 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
210 cell-index = <5>;
211 reg = <0x2c00 0x100>;
212 interrupts = <2 4 0>;
213 }; 89 };
214 90
215 ethernet@3000 { 91 ethernet@3000 {
216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
217 reg = <0x3000 0x400>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <2 5 0>;
220 phy-handle = <&phy0>; 92 phy-handle = <&phy0>;
221 }; 93 };
222 94
223 mdio@3000 { 95 mdio@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
229
230 phy0: ethernet-phy@0 { 96 phy0: ethernet-phy@0 {
231 reg = <0>; 97 reg = <0>;
232 }; 98 };
233 }; 99 };
234 100
235 ata@3a00 {
236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
237 reg = <0x3a00 0x100>;
238 interrupts = <2 7 0>;
239 };
240
241 i2c@3d00 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d00 0x40>;
246 interrupts = <2 15 0>;
247 };
248
249 i2c@3d40 { 101 i2c@3d40 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
253 reg = <0x3d40 0x40>;
254 interrupts = <2 16 0>;
255 rtc@51 { 102 rtc@51 {
256 compatible = "nxp,pcf8563"; 103 compatible = "nxp,pcf8563";
257 reg = <0x51>; 104 reg = <0x51>;
258 }; 105 };
259 eeprom@52 { 106 eeprom@52 {
260 compatible = "at24,24c32"; 107 compatible = "catalyst,24c32";
261 reg = <0x52>; 108 reg = <0x52>;
109 pagesize = <32>;
262 }; 110 };
263 }; 111 };
264
265 sram@8000 {
266 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
267 reg = <0x8000 0x4000>;
268 };
269 }; 112 };
270 113
271 pci@f0000d00 { 114 pci@f0000d00 {
272 #interrupt-cells = <1>;
273 #size-cells = <2>;
274 #address-cells = <3>;
275 device_type = "pci";
276 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
277 reg = <0xf0000d00 0x100>;
278 interrupt-map-mask = <0xf800 0 0 7>; 115 interrupt-map-mask = <0xf800 0 0 7>;
279 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 116 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
280 0xc000 0 0 2 &mpc5200_pic 1 1 3 117 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -285,20 +122,12 @@
285 0xc800 0 0 2 &mpc5200_pic 1 2 3 122 0xc800 0 0 2 &mpc5200_pic 1 2 3
286 0xc800 0 0 3 &mpc5200_pic 1 3 3 123 0xc800 0 0 3 &mpc5200_pic 1 3 3
287 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 124 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
288 clock-frequency = <0>; // From boot loader
289 interrupts = <2 8 0 2 9 0 2 10 0>;
290 bus-range = <0 0>;
291 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 125 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
292 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 126 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
293 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 127 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
294 }; 128 };
295 129
296 localbus { 130 localbus {
297 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
298
299 #address-cells = <2>;
300 #size-cells = <1>;
301
302 ranges = <0 0 0xfe000000 0x02000000 131 ranges = <0 0 0xfe000000 0x02000000
303 1 0 0xfc000000 0x02000000 132 1 0 0xfc000000 0x02000000
304 2 0 0xfbe00000 0x00200000 133 2 0 0xfbe00000 0x00200000
@@ -351,40 +180,39 @@
351 bank-width = <2>; 180 bank-width = <2>;
352 }; 181 };
353 182
354 /* 183 /*
355 * example snippets for FPGA 184 * example snippets for FPGA
356 * 185 *
357 * fpga@3,0 { 186 * fpga@3,0 {
358 * compatible = "fpga_driver"; 187 * compatible = "fpga_driver";
359 * reg = <3 0 0x02000000>; 188 * reg = <3 0 0x02000000>;
360 * bank-width = <4>; 189 * bank-width = <4>;
361 * }; 190 * };
362 * 191 *
363 * fpga@4,0 { 192 * fpga@4,0 {
364 * compatible = "fpga_driver"; 193 * compatible = "fpga_driver";
365 * reg = <4 0 0x02000000>; 194 * reg = <4 0 0x02000000>;
366 * bank-width = <4>; 195 * bank-width = <4>;
367 * }; 196 * };
368 */ 197 */
369 198
370 /* 199 /*
371 * example snippets for free chipselects 200 * example snippets for free chipselects
372 * 201 *
373 * device@5,0 { 202 * device@5,0 {
374 * compatible = "custom_driver"; 203 * compatible = "custom_driver";
375 * reg = <5 0 0x02000000>; 204 * reg = <5 0 0x02000000>;
376 * }; 205 * };
377 * 206 *
378 * device@6,0 { 207 * device@6,0 {
379 * compatible = "custom_driver"; 208 * compatible = "custom_driver";
380 * reg = <6 0 0x02000000>; 209 * reg = <6 0 0x02000000>;
381 * }; 210 * };
382 * 211 *
383 * device@7,0 { 212 * device@7,0 {
384 * compatible = "custom_driver"; 213 * compatible = "custom_driver";
385 * reg = <7 0 0x02000000>; 214 * reg = <7 0 0x02000000>;
386 * }; 215 * };
387 */ 216 */
388 }; 217 };
389}; 218};
390
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
index 81636c01d906..d86a3a498118 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -358,8 +358,28 @@
358 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; 358 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
359 }; 359 };
360 360
361 MSI: ppc4xx-msi@400300000 {
362 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
363 reg = < 0x4 0x00300000 0x100
364 0x4 0x00300000 0x100>;
365 sdr-base = <0x3B0>;
366 msi-data = <0x00000000>;
367 msi-mask = <0x44440000>;
368 interrupt-count = <3>;
369 interrupts =<0 1 2 3>;
370 interrupt-parent = <&UIC0>;
371 #interrupt-cells = <1>;
372 #address-cells = <0>;
373 #size-cells = <0>;
374 interrupt-map = <0 &UIC0 0xC 1
375 1 &UIC0 0x0D 1
376 2 &UIC0 0x0E 1
377 3 &UIC0 0x0F 1>;
378 };
379
361 }; 380 };
362 381
382
363 chosen { 383 chosen {
364 linux,stdout-path = "/plb/opb/serial@ef600200"; 384 linux,stdout-path = "/plb/opb/serial@ef600200";
365 }; 385 };
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
index 019264c62904..ba83d5488ec6 100644
--- a/arch/powerpc/boot/dts/uc101.dts
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -11,79 +11,24 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "manroland,uc101"; 17 model = "manroland,uc101";
18 compatible = "manroland,uc101"; 18 compatible = "manroland,uc101";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44 19
45 soc5200@f0000000 { 20 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // General Purpose Timer in GPIO mode 21 gpt0: timer@600 { // General Purpose Timer in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller; 22 gpio-controller;
72 #gpio-cells = <2>; 23 #gpio-cells = <2>;
73 }; 24 };
74 25
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode 26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller; 27 gpio-controller;
80 #gpio-cells = <2>; 28 #gpio-cells = <2>;
81 }; 29 };
82 30
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode 31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller; 32 gpio-controller;
88 #gpio-cells = <2>; 33 #gpio-cells = <2>;
89 }; 34 };
@@ -97,118 +42,85 @@
97 }; 42 };
98 43
99 gpt4: timer@640 { // General Purpose Timer in GPIO mode 44 gpt4: timer@640 { // General Purpose Timer in GPIO mode
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 reg = <0x640 0x10>;
102 interrupts = <1 13 0>;
103 gpio-controller; 45 gpio-controller;
104 #gpio-cells = <2>; 46 #gpio-cells = <2>;
105 }; 47 };
106 48
107 gpt5: timer@650 { // General Purpose Timer in GPIO mode 49 gpt5: timer@650 { // General Purpose Timer in GPIO mode
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 gpio-controller; 50 gpio-controller;
112 #gpio-cells = <2>; 51 #gpio-cells = <2>;
113 }; 52 };
114 53
115 gpt6: timer@660 { // General Purpose Timer in GPIO mode 54 gpt6: timer@660 { // General Purpose Timer in GPIO mode
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x660 0x10>;
118 interrupts = <1 15 0>;
119 gpio-controller; 55 gpio-controller;
120 #gpio-cells = <2>; 56 #gpio-cells = <2>;
121 }; 57 };
122 58
123 gpt7: timer@670 { // General Purpose Timer in GPIO mode 59 gpt7: timer@670 { // General Purpose Timer in GPIO mode
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 reg = <0x670 0x10>;
126 interrupts = <1 16 0>;
127 gpio-controller; 60 gpio-controller;
128 #gpio-cells = <2>; 61 #gpio-cells = <2>;
129 }; 62 };
130 63
131 gpio_simple: gpio@b00 { 64 rtc@800 {
132 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 65 status = "disabled";
133 reg = <0xb00 0x40>;
134 interrupts = <1 7 0>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 }; 66 };
138 67
139 gpio_wkup: gpio@c00 { 68 can@900 {
140 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 69 status = "disabled";
141 reg = <0xc00 0x40>; 70 };
142 interrupts = <1 8 0 0 3 0>; 71
143 gpio-controller; 72 can@980 {
144 #gpio-cells = <2>; 73 status = "disabled";
145 }; 74 };
146 75
147 dma-controller@1200 { 76 spi@f00 {
148 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 77 status = "disabled";
149 reg = <0x1200 0x80>;
150 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
151 3 4 0 3 5 0 3 6 0 3 7 0
152 3 8 0 3 9 0 3 10 0 3 11 0
153 3 12 0 3 13 0 3 14 0 3 15 0>;
154 }; 78 };
155 79
156 xlb@1f00 { 80 usb@1000 {
157 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 81 status = "disabled";
158 reg = <0x1f00 0x100>;
159 }; 82 };
160 83
161 serial@2000 { /* PSC1 in UART mode */ 84 psc@2000 { // PSC1
162 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 85 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
163 reg = <0x2000 0x100>;
164 interrupts = <2 1 0>;
165 }; 86 };
166 87
167 serial@2200 { /* PSC2 in UART mode */ 88 psc@2200 { // PSC2
168 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 89 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
169 reg = <0x2200 0x100>;
170 interrupts = <2 2 0>;
171 }; 90 };
172 91
173 serial@2c00 { /* PSC6 in UART mode */ 92 psc@2400 { // PSC3
93 status = "disabled";
94 };
95
96 psc@2600 { // PSC4
97 status = "disabled";
98 };
99
100 psc@2800 { // PSC5
101 status = "disabled";
102 };
103
104 psc@2c00 { // PSC6
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 105 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 reg = <0x2c00 0x100>;
176 interrupts = <2 4 0>;
177 }; 106 };
178 107
179 ethernet@3000 { 108 ethernet@3000 {
180 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
181 reg = <0x3000 0x400>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <2 5 0>;
184 phy-handle = <&phy0>; 109 phy-handle = <&phy0>;
185 }; 110 };
186 111
187 mdio@3000 { 112 mdio@3000 {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
191 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
192 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
193
194 phy0: ethernet-phy@0 { 113 phy0: ethernet-phy@0 {
195 compatible = "intel,lxt971"; 114 compatible = "intel,lxt971";
196 reg = <0>; 115 reg = <0>;
197 }; 116 };
198 }; 117 };
199 118
200 ata@3a00 { 119 i2c@3d00 {
201 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 120 status = "disabled";
202 reg = <0x3a00 0x100>;
203 interrupts = <2 7 0>;
204 }; 121 };
205 122
206 i2c@3d40 { 123 i2c@3d40 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
210 reg = <0x3d40 0x40>;
211 interrupts = <2 16 0>;
212 fsl,preserve-clocking; 124 fsl,preserve-clocking;
213 clock-frequency = <400000>; 125 clock-frequency = <400000>;
214 126
@@ -221,19 +133,13 @@
221 reg = <0x51>; 133 reg = <0x51>;
222 }; 134 };
223 }; 135 };
136 };
224 137
225 sram@8000 { 138 pci@f0000d00 {
226 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 139 status = "disabled";
227 reg = <0x8000 0x4000>;
228 };
229 }; 140 };
230 141
231 localbus { 142 localbus {
232 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
233
234 #address-cells = <2>;
235 #size-cells = <1>;
236
237 ranges = <0 0 0xff800000 0x00800000 143 ranges = <0 0 0xff800000 0x00800000
238 1 0 0x80000000 0x00800000 144 1 0 0x80000000 0x00800000
239 3 0 0x80000000 0x00800000>; 145 3 0 0x80000000 0x00800000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-23 09:06:32 -0400