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Diffstat (limited to 'arch/powerpc/boot/dts/walnut.dts')
-rw-r--r--arch/powerpc/boot/dts/walnut.dts118
1 files changed, 60 insertions, 58 deletions
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
index a328607c8f84..4a9f726ada13 100644
--- a/arch/powerpc/boot/dts/walnut.dts
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -9,12 +9,14 @@
9 * any warranty of any kind, whether express or implied. 9 * any warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 #address-cells = <1>; 15 #address-cells = <1>;
14 #size-cells = <1>; 16 #size-cells = <1>;
15 model = "ibm,walnut"; 17 model = "ibm,walnut";
16 compatible = "ibm,walnut"; 18 compatible = "ibm,walnut";
17 dcr-parent = <&/cpus/cpu@0>; 19 dcr-parent = <&{/cpus/cpu@0}>;
18 20
19 aliases { 21 aliases {
20 ethernet0 = &EMAC; 22 ethernet0 = &EMAC;
@@ -29,13 +31,13 @@
29 cpu@0 { 31 cpu@0 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 model = "PowerPC,405GP"; 33 model = "PowerPC,405GP";
32 reg = <0>; 34 reg = <0x00000000>;
33 clock-frequency = <bebc200>; /* Filled in by zImage */ 35 clock-frequency = <200000000>; /* Filled in by zImage */
34 timebase-frequency = <0>; /* Filled in by zImage */ 36 timebase-frequency = <0>; /* Filled in by zImage */
35 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
36 d-cache-line-size = <20>; 38 d-cache-line-size = <32>;
37 i-cache-size = <4000>; 39 i-cache-size = <16384>;
38 d-cache-size = <4000>; 40 d-cache-size = <16384>;
39 dcr-controller; 41 dcr-controller;
40 dcr-access-method = "native"; 42 dcr-access-method = "native";
41 }; 43 };
@@ -43,14 +45,14 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0 0>; /* Filled in by zImage */ 48 reg = <0x00000000 0x00000000>; /* Filled in by zImage */
47 }; 49 };
48 50
49 UIC0: interrupt-controller { 51 UIC0: interrupt-controller {
50 compatible = "ibm,uic"; 52 compatible = "ibm,uic";
51 interrupt-controller; 53 interrupt-controller;
52 cell-index = <0>; 54 cell-index = <0>;
53 dcr-reg = <0c0 9>; 55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>; 56 #address-cells = <0>;
55 #size-cells = <0>; 57 #size-cells = <0>;
56 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
@@ -65,63 +67,63 @@
65 67
66 SDRAM0: memory-controller { 68 SDRAM0: memory-controller {
67 compatible = "ibm,sdram-405gp"; 69 compatible = "ibm,sdram-405gp";
68 dcr-reg = <010 2>; 70 dcr-reg = <0x010 0x002>;
69 }; 71 };
70 72
71 MAL: mcmal { 73 MAL: mcmal {
72 compatible = "ibm,mcmal-405gp", "ibm,mcmal"; 74 compatible = "ibm,mcmal-405gp", "ibm,mcmal";
73 dcr-reg = <180 62>; 75 dcr-reg = <0x180 0x062>;
74 num-tx-chans = <1>; 76 num-tx-chans = <1>;
75 num-rx-chans = <1>; 77 num-rx-chans = <1>;
76 interrupt-parent = <&UIC0>; 78 interrupt-parent = <&UIC0>;
77 interrupts = < 79 interrupts = <
78 b 4 /* TXEOB */ 80 0xb 0x4 /* TXEOB */
79 c 4 /* RXEOB */ 81 0xc 0x4 /* RXEOB */
80 a 4 /* SERR */ 82 0xa 0x4 /* SERR */
81 d 4 /* TXDE */ 83 0xd 0x4 /* TXDE */
82 e 4 /* RXDE */>; 84 0xe 0x4 /* RXDE */>;
83 }; 85 };
84 86
85 POB0: opb { 87 POB0: opb {
86 compatible = "ibm,opb-405gp", "ibm,opb"; 88 compatible = "ibm,opb-405gp", "ibm,opb";
87 #address-cells = <1>; 89 #address-cells = <1>;
88 #size-cells = <1>; 90 #size-cells = <1>;
89 ranges = <ef600000 ef600000 a00000>; 91 ranges = <0xef600000 0xef600000 0x00a00000>;
90 dcr-reg = <0a0 5>; 92 dcr-reg = <0x0a0 0x005>;
91 clock-frequency = <0>; /* Filled in by zImage */ 93 clock-frequency = <0>; /* Filled in by zImage */
92 94
93 UART0: serial@ef600300 { 95 UART0: serial@ef600300 {
94 device_type = "serial"; 96 device_type = "serial";
95 compatible = "ns16550"; 97 compatible = "ns16550";
96 reg = <ef600300 8>; 98 reg = <0xef600300 0x00000008>;
97 virtual-reg = <ef600300>; 99 virtual-reg = <0xef600300>;
98 clock-frequency = <0>; /* Filled in by zImage */ 100 clock-frequency = <0>; /* Filled in by zImage */
99 current-speed = <2580>; 101 current-speed = <9600>;
100 interrupt-parent = <&UIC0>; 102 interrupt-parent = <&UIC0>;
101 interrupts = <0 4>; 103 interrupts = <0x0 0x4>;
102 }; 104 };
103 105
104 UART1: serial@ef600400 { 106 UART1: serial@ef600400 {
105 device_type = "serial"; 107 device_type = "serial";
106 compatible = "ns16550"; 108 compatible = "ns16550";
107 reg = <ef600400 8>; 109 reg = <0xef600400 0x00000008>;
108 virtual-reg = <ef600400>; 110 virtual-reg = <0xef600400>;
109 clock-frequency = <0>; /* Filled in by zImage */ 111 clock-frequency = <0>; /* Filled in by zImage */
110 current-speed = <2580>; 112 current-speed = <9600>;
111 interrupt-parent = <&UIC0>; 113 interrupt-parent = <&UIC0>;
112 interrupts = <1 4>; 114 interrupts = <0x1 0x4>;
113 }; 115 };
114 116
115 IIC: i2c@ef600500 { 117 IIC: i2c@ef600500 {
116 compatible = "ibm,iic-405gp", "ibm,iic"; 118 compatible = "ibm,iic-405gp", "ibm,iic";
117 reg = <ef600500 11>; 119 reg = <0xef600500 0x00000011>;
118 interrupt-parent = <&UIC0>; 120 interrupt-parent = <&UIC0>;
119 interrupts = <2 4>; 121 interrupts = <0x2 0x4>;
120 }; 122 };
121 123
122 GPIO: gpio@ef600700 { 124 GPIO: gpio@ef600700 {
123 compatible = "ibm,gpio-405gp"; 125 compatible = "ibm,gpio-405gp";
124 reg = <ef600700 20>; 126 reg = <0xef600700 0x00000020>;
125 }; 127 };
126 128
127 EMAC: ethernet@ef600800 { 129 EMAC: ethernet@ef600800 {
@@ -129,26 +131,26 @@
129 compatible = "ibm,emac-405gp", "ibm,emac"; 131 compatible = "ibm,emac-405gp", "ibm,emac";
130 interrupt-parent = <&UIC0>; 132 interrupt-parent = <&UIC0>;
131 interrupts = < 133 interrupts = <
132 f 4 /* Ethernet */ 134 0xf 0x4 /* Ethernet */
133 9 4 /* Ethernet Wake Up */>; 135 0x9 0x4 /* Ethernet Wake Up */>;
134 local-mac-address = [000000000000]; /* Filled in by zImage */ 136 local-mac-address = [000000000000]; /* Filled in by zImage */
135 reg = <ef600800 70>; 137 reg = <0xef600800 0x00000070>;
136 mal-device = <&MAL>; 138 mal-device = <&MAL>;
137 mal-tx-channel = <0>; 139 mal-tx-channel = <0>;
138 mal-rx-channel = <0>; 140 mal-rx-channel = <0>;
139 cell-index = <0>; 141 cell-index = <0>;
140 max-frame-size = <5dc>; 142 max-frame-size = <1500>;
141 rx-fifo-size = <1000>; 143 rx-fifo-size = <4096>;
142 tx-fifo-size = <800>; 144 tx-fifo-size = <2048>;
143 phy-mode = "rmii"; 145 phy-mode = "rmii";
144 phy-map = <00000001>; 146 phy-map = <0x00000001>;
145 }; 147 };
146 148
147 }; 149 };
148 150
149 EBC0: ebc { 151 EBC0: ebc {
150 compatible = "ibm,ebc-405gp", "ibm,ebc"; 152 compatible = "ibm,ebc-405gp", "ibm,ebc";
151 dcr-reg = <012 2>; 153 dcr-reg = <0x012 0x002>;
152 #address-cells = <2>; 154 #address-cells = <2>;
153 #size-cells = <1>; 155 #size-cells = <1>;
154 /* The ranges property is supplied by the bootwrapper 156 /* The ranges property is supplied by the bootwrapper
@@ -158,18 +160,18 @@
158 clock-frequency = <0>; /* Filled in by zImage */ 160 clock-frequency = <0>; /* Filled in by zImage */
159 161
160 sram@0,0 { 162 sram@0,0 {
161 reg = <0 0 80000>; 163 reg = <0x00000000 0x00000000 0x00080000>;
162 }; 164 };
163 165
164 flash@0,80000 { 166 flash@0,80000 {
165 compatible = "jedec-flash"; 167 compatible = "jedec-flash";
166 bank-width = <1>; 168 bank-width = <1>;
167 reg = <0 80000 80000>; 169 reg = <0x00000000 0x00080000 0x00080000>;
168 #address-cells = <1>; 170 #address-cells = <1>;
169 #size-cells = <1>; 171 #size-cells = <1>;
170 partition@0 { 172 partition@0 {
171 label = "OpenBIOS"; 173 label = "OpenBIOS";
172 reg = <0 80000>; 174 reg = <0x00000000 0x00080000>;
173 read-only; 175 read-only;
174 }; 176 };
175 }; 177 };
@@ -177,24 +179,24 @@
177 nvram@1,0 { 179 nvram@1,0 {
178 /* NVRAM and RTC */ 180 /* NVRAM and RTC */
179 compatible = "ds1743-nvram"; 181 compatible = "ds1743-nvram";
180 #bytes = <2000>; 182 #bytes = <0x2000>;
181 reg = <1 0 2000>; 183 reg = <0x00000001 0x00000000 0x00002000>;
182 }; 184 };
183 185
184 keyboard@2,0 { 186 keyboard@2,0 {
185 compatible = "intel,82C42PC"; 187 compatible = "intel,82C42PC";
186 reg = <2 0 2>; 188 reg = <0x00000002 0x00000000 0x00000002>;
187 }; 189 };
188 190
189 ir@3,0 { 191 ir@3,0 {
190 compatible = "ti,TIR2000PAG"; 192 compatible = "ti,TIR2000PAG";
191 reg = <3 0 10>; 193 reg = <0x00000003 0x00000000 0x00000010>;
192 }; 194 };
193 195
194 fpga@7,0 { 196 fpga@7,0 {
195 compatible = "Walnut-FPGA"; 197 compatible = "Walnut-FPGA";
196 reg = <7 0 10>; 198 reg = <0x00000007 0x00000000 0x00000010>;
197 virtual-reg = <f0300005>; 199 virtual-reg = <0xf0300005>;
198 }; 200 };
199 }; 201 };
200 202
@@ -205,35 +207,35 @@
205 #address-cells = <3>; 207 #address-cells = <3>;
206 compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; 208 compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
207 primary; 209 primary;
208 reg = <eec00000 8 /* Config space access */ 210 reg = <0xeec00000 0x00000008 /* Config space access */
209 eed80000 4 /* IACK */ 211 0xeed80000 0x00000004 /* IACK */
210 eed80000 4 /* Special cycle */ 212 0xeed80000 0x00000004 /* Special cycle */
211 ef480000 40>; /* Internal registers */ 213 0xef480000 0x00000040>; /* Internal registers */
212 214
213 /* Outbound ranges, one memory and one IO, 215 /* Outbound ranges, one memory and one IO,
214 * later cannot be changed. Chip supports a second 216 * later cannot be changed. Chip supports a second
215 * IO range but we don't use it for now 217 * IO range but we don't use it for now
216 */ 218 */
217 ranges = <02000000 0 80000000 80000000 0 20000000 219 ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
218 01000000 0 00000000 e8000000 0 00010000>; 220 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
219 221
220 /* Inbound 2GB range starting at 0 */ 222 /* Inbound 2GB range starting at 0 */
221 dma-ranges = <42000000 0 0 0 0 80000000>; 223 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
222 224
223 /* Walnut has all 4 IRQ pins tied together per slot */ 225 /* Walnut has all 4 IRQ pins tied together per slot */
224 interrupt-map-mask = <f800 0 0 0>; 226 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
225 interrupt-map = < 227 interrupt-map = <
226 /* IDSEL 1 */ 228 /* IDSEL 1 */
227 0800 0 0 0 &UIC0 1c 8 229 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
228 230
229 /* IDSEL 2 */ 231 /* IDSEL 2 */
230 1000 0 0 0 &UIC0 1d 8 232 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
231 233
232 /* IDSEL 3 */ 234 /* IDSEL 3 */
233 1800 0 0 0 &UIC0 1e 8 235 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
234 236
235 /* IDSEL 4 */ 237 /* IDSEL 4 */
236 2000 0 0 0 &UIC0 1f 8 238 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
237 >; 239 >;
238 }; 240 };
239 }; 241 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 16:12:58 -0500