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diff --git a/arch/powerpc/boot/dts/t4240rdb.dts b/arch/powerpc/boot/dts/t4240rdb.dts
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1/*
2 * T4240RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t4240si-pre.dtsi"
36
37/ {
38 model = "fsl,T4240RDB";
39 compatible = "fsl,T4240RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 ifc: localbus@ffe124000 {
45 reg = <0xf 0xfe124000 0 0x2000>;
46 ranges = <0 0 0xf 0xe8000000 0x08000000
47 2 0 0xf 0xff800000 0x00010000
48 3 0 0xf 0xffdf0000 0x00008000>;
49
50 nor@0,0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "cfi-flash";
54 reg = <0x0 0x0 0x8000000>;
55
56 bank-width = <2>;
57 device-width = <1>;
58 };
59
60 nand@2,0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,ifc-nand";
64 reg = <0x2 0x0 0x10000>;
65 };
66 };
67
68 memory {
69 device_type = "memory";
70 };
71
72 dcsr: dcsr@f00000000 {
73 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
74 };
75
76 soc: soc@ffe000000 {
77 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
78 reg = <0xf 0xfe000000 0 0x00001000>;
79 spi@110000 {
80 flash@0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "sst,sst25wf040";
84 reg = <0>;
85 spi-max-frequency = <40000000>; /* input clock */
86 };
87 };
88
89 i2c@118000 {
90 eeprom@52 {
91 compatible = "at24,24c256";
92 reg = <0x52>;
93 };
94 eeprom@54 {
95 compatible = "at24,24c256";
96 reg = <0x54>;
97 };
98 eeprom@56 {
99 compatible = "at24,24c256";
100 reg = <0x56>;
101 };
102 rtc@68 {
103 compatible = "dallas,ds1374";
104 reg = <0x68>;
105 interrupts = <0x1 0x1 0 0>;
106 };
107 };
108
109 sdhc@114000 {
110 voltage-ranges = <1800 1800 3300 3300>;
111 };
112 };
113
114 pci0: pcie@ffe240000 {
115 reg = <0xf 0xfe240000 0 0x10000>;
116 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
117 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
118 pcie@0 {
119 ranges = <0x02000000 0 0xe0000000
120 0x02000000 0 0xe0000000
121 0 0x20000000
122
123 0x01000000 0 0x00000000
124 0x01000000 0 0x00000000
125 0 0x00010000>;
126 };
127 };
128
129 pci1: pcie@ffe250000 {
130 reg = <0xf 0xfe250000 0 0x10000>;
131 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
132 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
133 pcie@0 {
134 ranges = <0x02000000 0 0xe0000000
135 0x02000000 0 0xe0000000
136 0 0x20000000
137
138 0x01000000 0 0x00000000
139 0x01000000 0 0x00000000
140 0 0x00010000>;
141 };
142 };
143
144 pci2: pcie@ffe260000 {
145 reg = <0xf 0xfe260000 0 0x1000>;
146 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
147 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
148 pcie@0 {
149 ranges = <0x02000000 0 0xe0000000
150 0x02000000 0 0xe0000000
151 0 0x20000000
152
153 0x01000000 0 0x00000000
154 0x01000000 0 0x00000000
155 0 0x00010000>;
156 };
157 };
158
159 pci3: pcie@ffe270000 {
160 reg = <0xf 0xfe270000 0 0x10000>;
161 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
162 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
163 pcie@0 {
164 ranges = <0x02000000 0 0xe0000000
165 0x02000000 0 0xe0000000
166 0 0x20000000
167
168 0x01000000 0 0x00000000
169 0x01000000 0 0x00000000
170 0 0x00010000>;
171 };
172 };
173
174 rio: rapidio@ffe0c0000 {
175 reg = <0xf 0xfe0c0000 0 0x11000>;
176
177 port1 {
178 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
179 };
180 port2 {
181 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
182 };
183 };
184};
185
186/include/ "fsl/t4240si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 00:33:56 -0500