diff options
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8540ads.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8540ads.dts | 175 |
1 files changed, 86 insertions, 89 deletions
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index fc8dff9f6201..6442a717ec3b 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | timebase-frequency = <0>; // 33 MHz, from uboot | 30 | timebase-frequency = <0>; // 33 MHz, from uboot |
| 31 | bus-frequency = <0>; // 166 MHz | 31 | bus-frequency = <0>; // 166 MHz |
| 32 | clock-frequency = <0>; // 825 MHz, from uboot | 32 | clock-frequency = <0>; // 825 MHz, from uboot |
| 33 | 32-bit; | ||
| 34 | }; | 33 | }; |
| 35 | }; | 34 | }; |
| 36 | 35 | ||
| @@ -42,7 +41,6 @@ | |||
| 42 | soc8540@e0000000 { | 41 | soc8540@e0000000 { |
| 43 | #address-cells = <1>; | 42 | #address-cells = <1>; |
| 44 | #size-cells = <1>; | 43 | #size-cells = <1>; |
| 45 | #interrupt-cells = <2>; | ||
| 46 | device_type = "soc"; | 44 | device_type = "soc"; |
| 47 | ranges = <0 e0000000 00100000>; | 45 | ranges = <0 e0000000 00100000>; |
| 48 | reg = <e0000000 00100000>; // CCSRBAR 1M | 46 | reg = <e0000000 00100000>; // CCSRBAR 1M |
| @@ -173,105 +171,104 @@ | |||
| 173 | interrupts = <2a 2>; | 171 | interrupts = <2a 2>; |
| 174 | interrupt-parent = <&mpic>; | 172 | interrupt-parent = <&mpic>; |
| 175 | }; | 173 | }; |
| 176 | pci@8000 { | 174 | mpic: pic@40000 { |
| 177 | interrupt-map-mask = <f800 0 0 7>; | 175 | clock-frequency = <0>; |
| 178 | interrupt-map = < | 176 | interrupt-controller; |
| 177 | #address-cells = <0>; | ||
| 178 | #interrupt-cells = <2>; | ||
| 179 | reg = <40000 40000>; | ||
| 180 | compatible = "chrp,open-pic"; | ||
| 181 | device_type = "open-pic"; | ||
| 182 | big-endian; | ||
| 183 | }; | ||
| 184 | }; | ||
| 179 | 185 | ||
| 180 | /* IDSEL 0x02 */ | 186 | pci@e0008000 { |
| 181 | 1000 0 0 1 &mpic 1 1 | 187 | interrupt-map-mask = <f800 0 0 7>; |
| 182 | 1000 0 0 2 &mpic 2 1 | 188 | interrupt-map = < |
| 183 | 1000 0 0 3 &mpic 3 1 | ||
| 184 | 1000 0 0 4 &mpic 4 1 | ||
| 185 | 189 | ||
| 186 | /* IDSEL 0x03 */ | 190 | /* IDSEL 0x02 */ |
| 187 | 1800 0 0 1 &mpic 4 1 | 191 | 1000 0 0 1 &mpic 1 1 |
| 188 | 1800 0 0 2 &mpic 1 1 | 192 | 1000 0 0 2 &mpic 2 1 |
| 189 | 1800 0 0 3 &mpic 2 1 | 193 | 1000 0 0 3 &mpic 3 1 |
| 190 | 1800 0 0 4 &mpic 3 1 | 194 | 1000 0 0 4 &mpic 4 1 |
| 191 | 195 | ||
| 192 | /* IDSEL 0x04 */ | 196 | /* IDSEL 0x03 */ |
| 193 | 2000 0 0 1 &mpic 3 1 | 197 | 1800 0 0 1 &mpic 4 1 |
| 194 | 2000 0 0 2 &mpic 4 1 | 198 | 1800 0 0 2 &mpic 1 1 |
| 195 | 2000 0 0 3 &mpic 1 1 | 199 | 1800 0 0 3 &mpic 2 1 |
| 196 | 2000 0 0 4 &mpic 2 1 | 200 | 1800 0 0 4 &mpic 3 1 |
| 197 | 201 | ||
| 198 | /* IDSEL 0x05 */ | 202 | /* IDSEL 0x04 */ |
| 199 | 2800 0 0 1 &mpic 2 1 | 203 | 2000 0 0 1 &mpic 3 1 |
| 200 | 2800 0 0 2 &mpic 3 1 | 204 | 2000 0 0 2 &mpic 4 1 |
| 201 | 2800 0 0 3 &mpic 4 1 | 205 | 2000 0 0 3 &mpic 1 1 |
| 202 | 2800 0 0 4 &mpic 1 1 | 206 | 2000 0 0 4 &mpic 2 1 |
| 203 | 207 | ||
| 204 | /* IDSEL 0x0c */ | 208 | /* IDSEL 0x05 */ |
| 205 | 6000 0 0 1 &mpic 1 1 | 209 | 2800 0 0 1 &mpic 2 1 |
| 206 | 6000 0 0 2 &mpic 2 1 | 210 | 2800 0 0 2 &mpic 3 1 |
| 207 | 6000 0 0 3 &mpic 3 1 | 211 | 2800 0 0 3 &mpic 4 1 |
| 208 | 6000 0 0 4 &mpic 4 1 | 212 | 2800 0 0 4 &mpic 1 1 |
| 209 | 213 | ||
| 210 | /* IDSEL 0x0d */ | 214 | /* IDSEL 0x0c */ |
| 211 | 6800 0 0 1 &mpic 4 1 | 215 | 6000 0 0 1 &mpic 1 1 |
| 212 | 6800 0 0 2 &mpic 1 1 | 216 | 6000 0 0 2 &mpic 2 1 |
| 213 | 6800 0 0 3 &mpic 2 1 | 217 | 6000 0 0 3 &mpic 3 1 |
| 214 | 6800 0 0 4 &mpic 3 1 | 218 | 6000 0 0 4 &mpic 4 1 |
| 215 | 219 | ||
| 216 | /* IDSEL 0x0e */ | 220 | /* IDSEL 0x0d */ |
| 217 | 7000 0 0 1 &mpic 3 1 | 221 | 6800 0 0 1 &mpic 4 1 |
| 218 | 7000 0 0 2 &mpic 4 1 | 222 | 6800 0 0 2 &mpic 1 1 |
| 219 | 7000 0 0 3 &mpic 1 1 | 223 | 6800 0 0 3 &mpic 2 1 |
| 220 | 7000 0 0 4 &mpic 2 1 | 224 | 6800 0 0 4 &mpic 3 1 |
| 221 | 225 | ||
| 222 | /* IDSEL 0x0f */ | 226 | /* IDSEL 0x0e */ |
| 223 | 7800 0 0 1 &mpic 2 1 | 227 | 7000 0 0 1 &mpic 3 1 |
| 224 | 7800 0 0 2 &mpic 3 1 | 228 | 7000 0 0 2 &mpic 4 1 |
| 225 | 7800 0 0 3 &mpic 4 1 | 229 | 7000 0 0 3 &mpic 1 1 |
| 226 | 7800 0 0 4 &mpic 1 1 | 230 | 7000 0 0 4 &mpic 2 1 |
| 227 | 231 | ||
| 228 | /* IDSEL 0x12 */ | 232 | /* IDSEL 0x0f */ |
| 229 | 9000 0 0 1 &mpic 1 1 | 233 | 7800 0 0 1 &mpic 2 1 |
| 230 | 9000 0 0 2 &mpic 2 1 | 234 | 7800 0 0 2 &mpic 3 1 |
| 231 | 9000 0 0 3 &mpic 3 1 | 235 | 7800 0 0 3 &mpic 4 1 |
| 232 | 9000 0 0 4 &mpic 4 1 | 236 | 7800 0 0 4 &mpic 1 1 |
| 233 | 237 | ||
| 234 | /* IDSEL 0x13 */ | 238 | /* IDSEL 0x12 */ |
| 235 | 9800 0 0 1 &mpic 4 1 | 239 | 9000 0 0 1 &mpic 1 1 |
| 236 | 9800 0 0 2 &mpic 1 1 | 240 | 9000 0 0 2 &mpic 2 1 |
| 237 | 9800 0 0 3 &mpic 2 1 | 241 | 9000 0 0 3 &mpic 3 1 |
| 238 | 9800 0 0 4 &mpic 3 1 | 242 | 9000 0 0 4 &mpic 4 1 |
| 239 | 243 | ||
| 240 | /* IDSEL 0x14 */ | 244 | /* IDSEL 0x13 */ |
| 241 | a000 0 0 1 &mpic 3 1 | 245 | 9800 0 0 1 &mpic 4 1 |
| 242 | a000 0 0 2 &mpic 4 1 | 246 | 9800 0 0 2 &mpic 1 1 |
| 243 | a000 0 0 3 &mpic 1 1 | 247 | 9800 0 0 3 &mpic 2 1 |
| 244 | a000 0 0 4 &mpic 2 1 | 248 | 9800 0 0 4 &mpic 3 1 |
| 245 | 249 | ||
| 246 | /* IDSEL 0x15 */ | 250 | /* IDSEL 0x14 */ |
| 247 | a800 0 0 1 &mpic 2 1 | 251 | a000 0 0 1 &mpic 3 1 |
| 248 | a800 0 0 2 &mpic 3 1 | 252 | a000 0 0 2 &mpic 4 1 |
| 249 | a800 0 0 3 &mpic 4 1 | 253 | a000 0 0 3 &mpic 1 1 |
| 250 | a800 0 0 4 &mpic 1 1>; | 254 | a000 0 0 4 &mpic 2 1 |
| 251 | interrupt-parent = <&mpic>; | ||
| 252 | interrupts = <18 2>; | ||
| 253 | bus-range = <0 0>; | ||
| 254 | ranges = <02000000 0 80000000 80000000 0 20000000 | ||
| 255 | 01000000 0 00000000 e2000000 0 00100000>; | ||
| 256 | clock-frequency = <3f940aa>; | ||
| 257 | #interrupt-cells = <1>; | ||
| 258 | #size-cells = <2>; | ||
| 259 | #address-cells = <3>; | ||
| 260 | reg = <8000 1000>; | ||
| 261 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | ||
| 262 | device_type = "pci"; | ||
| 263 | }; | ||
| 264 | 255 | ||
| 265 | mpic: pic@40000 { | 256 | /* IDSEL 0x15 */ |
| 266 | clock-frequency = <0>; | 257 | a800 0 0 1 &mpic 2 1 |
| 267 | interrupt-controller; | 258 | a800 0 0 2 &mpic 3 1 |
| 268 | #address-cells = <0>; | 259 | a800 0 0 3 &mpic 4 1 |
| 269 | #interrupt-cells = <2>; | 260 | a800 0 0 4 &mpic 1 1>; |
| 270 | reg = <40000 40000>; | 261 | interrupt-parent = <&mpic>; |
| 271 | built-in; | 262 | interrupts = <18 2>; |
| 272 | compatible = "chrp,open-pic"; | 263 | bus-range = <0 0>; |
| 273 | device_type = "open-pic"; | 264 | ranges = <02000000 0 80000000 80000000 0 20000000 |
| 274 | big-endian; | 265 | 01000000 0 00000000 e2000000 0 00100000>; |
| 275 | }; | 266 | clock-frequency = <3f940aa>; |
| 267 | #interrupt-cells = <1>; | ||
| 268 | #size-cells = <2>; | ||
| 269 | #address-cells = <3>; | ||
| 270 | reg = <e0008000 1000>; | ||
| 271 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | ||
| 272 | device_type = "pci"; | ||
| 276 | }; | 273 | }; |
| 277 | }; | 274 | }; |