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Diffstat (limited to 'arch/powerpc/boot/dts/mpc836x_rdk.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc836x_rdk.dts432
1 files changed, 432 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
new file mode 100644
index 000000000000..8acd1d6577f2
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -0,0 +1,432 @@
1/*
2 * MPC8360E RDK Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2007-2008 MontaVista Software, Inc.
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "fsl,mpc8360rdk";
21
22 aliases {
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 ethernet0 = &enet0;
28 ethernet1 = &enet1;
29 ethernet2 = &enet2;
30 ethernet3 = &enet3;
31 pci0 = &pci0;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 PowerPC,8360@0 {
39 device_type = "cpu";
40 reg = <0>;
41 d-cache-line-size = <32>;
42 i-cache-line-size = <32>;
43 d-cache-size = <32768>;
44 i-cache-size = <32768>;
45 /* filled by u-boot */
46 timebase-frequency = <0>;
47 bus-frequency = <0>;
48 clock-frequency = <0>;
49 };
50 };
51
52 memory {
53 device_type = "memory";
54 /* filled by u-boot */
55 reg = <0 0>;
56 };
57
58 soc@e0000000 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 device_type = "soc";
62 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
63 "simple-bus";
64 ranges = <0 0xe0000000 0x200000>;
65 reg = <0xe0000000 0x200>;
66 /* filled by u-boot */
67 bus-frequency = <0>;
68
69 wdt@200 {
70 compatible = "mpc83xx_wdt";
71 reg = <0x200 0x100>;
72 };
73
74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <14 8>;
81 interrupt-parent = <&ipic>;
82 dfsrr;
83 };
84
85 i2c@3100 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 cell-index = <1>;
89 compatible = "fsl-i2c";
90 reg = <0x3100 0x100>;
91 interrupts = <16 8>;
92 interrupt-parent = <&ipic>;
93 dfsrr;
94 };
95
96 serial0: serial@4500 {
97 device_type = "serial";
98 compatible = "ns16550";
99 reg = <0x4500 0x100>;
100 interrupts = <9 8>;
101 interrupt-parent = <&ipic>;
102 /* filled by u-boot */
103 clock-frequency = <0>;
104 };
105
106 serial1: serial@4600 {
107 device_type = "serial";
108 compatible = "ns16550";
109 reg = <0x4600 0x100>;
110 interrupts = <10 8>;
111 interrupt-parent = <&ipic>;
112 /* filled by u-boot */
113 clock-frequency = <0>;
114 };
115
116 dma@82a8 {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
120 reg = <0x82a8 4>;
121 ranges = <0 0x8100 0x1a8>;
122 interrupt-parent = <&ipic>;
123 interrupts = <71 8>;
124 cell-index = <0>;
125 dma-channel@0 {
126 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
127 reg = <0 0x80>;
128 interrupt-parent = <&ipic>;
129 interrupts = <71 8>;
130 };
131 dma-channel@80 {
132 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
133 reg = <0x80 0x80>;
134 interrupt-parent = <&ipic>;
135 interrupts = <71 8>;
136 };
137 dma-channel@100 {
138 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
139 reg = <0x100 0x80>;
140 interrupt-parent = <&ipic>;
141 interrupts = <71 8>;
142 };
143 dma-channel@180 {
144 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
145 reg = <0x180 0x28>;
146 interrupt-parent = <&ipic>;
147 interrupts = <71 8>;
148 };
149 };
150
151 crypto@30000 {
152 compatible = "fsl,sec2-crypto";
153 reg = <0x30000 0x10000>;
154 interrupts = <11 8>;
155 interrupt-parent = <&ipic>;
156 num-channels = <4>;
157 channel-fifo-len = <24>;
158 exec-units-mask = <0x7e>;
159 /*
160 * desc mask is for rev1.x, we need runtime fixup
161 * for >=2.x
162 */
163 descriptor-types-mask = <0x1010ebf>;
164 };
165
166 ipic: interrupt-controller@700 {
167 #address-cells = <0>;
168 #interrupt-cells = <2>;
169 compatible = "fsl,pq2pro-pic", "fsl,ipic";
170 interrupt-controller;
171 reg = <0x700 0x100>;
172 };
173
174 qe_pio_b: gpio-controller@1418 {
175 #gpio-cells = <2>;
176 compatible = "fsl,mpc8360-qe-pario-bank",
177 "fsl,mpc8323-qe-pario-bank";
178 reg = <0x1418 0x18>;
179 gpio-controller;
180 };
181
182 qe_pio_e: gpio-controller@1460 {
183 #gpio-cells = <2>;
184 compatible = "fsl,mpc8360-qe-pario-bank",
185 "fsl,mpc8323-qe-pario-bank";
186 reg = <0x1460 0x18>;
187 gpio-controller;
188 };
189
190 qe@100000 {
191 #address-cells = <1>;
192 #size-cells = <1>;
193 device_type = "qe";
194 compatible = "fsl,qe", "simple-bus";
195 ranges = <0 0x100000 0x100000>;
196 reg = <0x100000 0x480>;
197 /* filled by u-boot */
198 clock-frequency = <0>;
199 bus-frequency = <0>;
200 brg-frequency = <0>;
201
202 muram@10000 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "fsl,qe-muram", "fsl,cpm-muram";
206 ranges = <0 0x10000 0xc000>;
207
208 data-only@0 {
209 compatible = "fsl,qe-muram-data",
210 "fsl,cpm-muram-data";
211 reg = <0 0xc000>;
212 };
213 };
214
215 timer@440 {
216 compatible = "fsl,mpc8360-qe-gtm",
217 "fsl,qe-gtm", "fsl,gtm";
218 reg = <0x440 0x40>;
219 interrupts = <12 13 14 15>;
220 interrupt-parent = <&qeic>;
221 /* filled by u-boot */
222 clock-frequency = <0>;
223 };
224
225 spi@4c0 {
226 cell-index = <0>;
227 compatible = "fsl,spi";
228 reg = <0x4c0 0x40>;
229 interrupts = <2>;
230 interrupt-parent = <&qeic>;
231 mode = "cpu-qe";
232 };
233
234 spi@500 {
235 cell-index = <1>;
236 compatible = "fsl,spi";
237 reg = <0x500 0x40>;
238 interrupts = <1>;
239 interrupt-parent = <&qeic>;
240 mode = "cpu-qe";
241 };
242
243 enet0: ucc@2000 {
244 device_type = "network";
245 compatible = "ucc_geth";
246 cell-index = <1>;
247 reg = <0x2000 0x200>;
248 interrupts = <32>;
249 interrupt-parent = <&qeic>;
250 rx-clock-name = "none";
251 tx-clock-name = "clk9";
252 phy-handle = <&phy2>;
253 phy-connection-type = "rgmii-rxid";
254 /* filled by u-boot */
255 local-mac-address = [ 00 00 00 00 00 00 ];
256 };
257
258 enet1: ucc@3000 {
259 device_type = "network";
260 compatible = "ucc_geth";
261 cell-index = <2>;
262 reg = <0x3000 0x200>;
263 interrupts = <33>;
264 interrupt-parent = <&qeic>;
265 rx-clock-name = "none";
266 tx-clock-name = "clk4";
267 phy-handle = <&phy4>;
268 phy-connection-type = "rgmii-rxid";
269 /* filled by u-boot */
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 };
272
273 enet2: ucc@2600 {
274 device_type = "network";
275 compatible = "ucc_geth";
276 cell-index = <7>;
277 reg = <0x2600 0x200>;
278 interrupts = <42>;
279 interrupt-parent = <&qeic>;
280 rx-clock-name = "clk20";
281 tx-clock-name = "clk19";
282 phy-handle = <&phy1>;
283 phy-connection-type = "mii";
284 /* filled by u-boot */
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 };
287
288 enet3: ucc@3200 {
289 device_type = "network";
290 compatible = "ucc_geth";
291 cell-index = <4>;
292 reg = <0x3200 0x200>;
293 interrupts = <35>;
294 interrupt-parent = <&qeic>;
295 rx-clock-name = "clk8";
296 tx-clock-name = "clk7";
297 phy-handle = <&phy3>;
298 phy-connection-type = "mii";
299 /* filled by u-boot */
300 local-mac-address = [ 00 00 00 00 00 00 ];
301 };
302
303 mdio@2120 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 compatible = "fsl,ucc-mdio";
307 reg = <0x2120 0x18>;
308
309 phy1: ethernet-phy@1 {
310 device_type = "ethernet-phy";
311 compatible = "national,DP83848VV";
312 reg = <1>;
313 };
314
315 phy2: ethernet-phy@2 {
316 device_type = "ethernet-phy";
317 compatible = "broadcom,BCM5481UA2KMLG";
318 reg = <2>;
319 };
320
321 phy3: ethernet-phy@3 {
322 device_type = "ethernet-phy";
323 compatible = "national,DP83848VV";
324 reg = <3>;
325 };
326
327 phy4: ethernet-phy@4 {
328 device_type = "ethernet-phy";
329 compatible = "broadcom,BCM5481UA2KMLG";
330 reg = <4>;
331 };
332 };
333
334 serial2: ucc@2400 {
335 device_type = "serial";
336 compatible = "ucc_uart";
337 reg = <0x2400 0x200>;
338 cell-index = <5>;
339 port-number = <0>;
340 rx-clock-name = "brg7";
341 tx-clock-name = "brg8";
342 interrupts = <40>;
343 interrupt-parent = <&qeic>;
344 soft-uart;
345 };
346
347 serial3: ucc@3400 {
348 device_type = "serial";
349 compatible = "ucc_uart";
350 reg = <0x3400 0x200>;
351 cell-index = <6>;
352 port-number = <1>;
353 rx-clock-name = "brg13";
354 tx-clock-name = "brg14";
355 interrupts = <41>;
356 interrupt-parent = <&qeic>;
357 soft-uart;
358 };
359
360 qeic: interrupt-controller@80 {
361 #address-cells = <0>;
362 #interrupt-cells = <1>;
363 compatible = "fsl,qe-ic";
364 interrupt-controller;
365 reg = <0x80 0x80>;
366 big-endian;
367 interrupts = <32 8 33 8>;
368 interrupt-parent = <&ipic>;
369 };
370 };
371 };
372
373 localbus@e0005000 {
374 #address-cells = <2>;
375 #size-cells = <1>;
376 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
377 "simple-bus";
378 reg = <0xe0005000 0xd8>;
379 ranges = <0 0 0xff800000 0x0800000
380 1 0 0x60000000 0x0001000
381 2 0 0x70000000 0x4000000>;
382
383 flash@0,0 {
384 compatible = "intel,PC28F640P30T85", "cfi-flash";
385 reg = <0 0 0x800000>;
386 bank-width = <2>;
387 device-width = <1>;
388 };
389
390 display@2,0 {
391 device_type = "display";
392 compatible = "fujitsu,MB86277", "fujitsu,mint";
393 reg = <2 0 0x4000000>;
394 fujitsu,sh3;
395 little-endian;
396 /* filled by u-boot */
397 address = <0>;
398 depth = <0>;
399 width = <0>;
400 height = <0>;
401 linebytes = <0>;
402 /* linux,opened; - added by uboot */
403 };
404 };
405
406 pci0: pci@e0008500 {
407 #address-cells = <3>;
408 #size-cells = <2>;
409 #interrupt-cells = <1>;
410 device_type = "pci";
411 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
412 reg = <0xe0008500 0x100>;
413 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
414 0x42000000 0 0x80000000 0x80000000 0 0x10000000
415 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
416 interrupts = <66 8>;
417 interrupt-parent = <&ipic>;
418 interrupt-map-mask = <0xf800 0 0 7>;
419 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
420 0xa000 0 0 1 &ipic 18 8
421 0xa000 0 0 2 &ipic 19 8
422
423 /* PCI1 IDSEL 0x15 AD21 */
424 0xa800 0 0 1 &ipic 19 8
425 0xa800 0 0 2 &ipic 20 8
426 0xa800 0 0 3 &ipic 21 8
427 0xa800 0 0 4 &ipic 18 8>;
428 /* filled by u-boot */
429 bus-range = <0 0>;
430 clock-frequency = <0>;
431 };
432};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 13:13:39 -0500