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-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts220
1 files changed, 14 insertions, 206 deletions
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 59702ace900f..fb288bb882b6 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -10,256 +10,75 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "fsl,lite5200b"; 16 model = "fsl,lite5200b";
17 compatible = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38 18
39 memory { 19 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x10000000>; // 256MB 20 reg = <0x00000000 0x10000000>; // 256MB
42 }; 21 };
43 22
44 soc5200@f0000000 { 23 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 24 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 25 fsl,has-wdt;
71 }; 26 };
72 27
73 timer@610 { // General Purpose Timer 28 psc@2000 { // PSC1
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 29 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
75 reg = <0x610 0x10>; 30 cell-index = <0>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
107 };
108
109 timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
113 };
114
115 rtc@800 { // Real time clock
116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117 reg = <0x800 0x100>;
118 interrupts = <1 5 0 1 6 0>;
119 };
120
121 can@900 {
122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
123 interrupts = <2 17 0>;
124 reg = <0x900 0x80>;
125 };
126
127 can@980 {
128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
129 interrupts = <2 18 0>;
130 reg = <0x980 0x80>;
131 };
132
133 gpio_simple: gpio@b00 {
134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
135 reg = <0xb00 0x40>;
136 interrupts = <1 7 0>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 gpio_wkup: gpio@c00 {
142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
143 reg = <0xc00 0x40>;
144 interrupts = <1 8 0 0 3 0>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 }; 31 };
148 32
149 spi@f00 { 33 psc@2200 { // PSC2
150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 34 status = "disabled";
151 reg = <0xf00 0x20>;
152 interrupts = <2 13 0 2 14 0>;
153 }; 35 };
154 36
155 usb@1000 { 37 psc@2400 { // PSC3
156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 38 status = "disabled";
157 reg = <0x1000 0xff>;
158 interrupts = <2 6 0>;
159 }; 39 };
160 40
161 dma-controller@1200 { 41 psc@2600 { // PSC4
162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 42 status = "disabled";
163 reg = <0x1200 0x80>;
164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
165 3 4 0 3 5 0 3 6 0 3 7 0
166 3 8 0 3 9 0 3 10 0 3 11 0
167 3 12 0 3 13 0 3 14 0 3 15 0>;
168 }; 43 };
169 44
170 xlb@1f00 { 45 psc@2800 { // PSC5
171 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 46 status = "disabled";
172 reg = <0x1f00 0x100>;
173 }; 47 };
174 48
175 serial@2000 { // PSC1 49 psc@2c00 { // PSC6
176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 50 status = "disabled";
177 cell-index = <0>;
178 reg = <0x2000 0x100>;
179 interrupts = <2 1 0>;
180 }; 51 };
181 52
182 // PSC2 in ac97 mode example 53 // PSC2 in ac97 mode example
183 //ac97@2200 { // PSC2 54 //ac97@2200 { // PSC2
184 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 55 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
185 // cell-index = <1>; 56 // cell-index = <1>;
186 // reg = <0x2200 0x100>;
187 // interrupts = <2 2 0>;
188 //}; 57 //};
189 58
190 // PSC3 in CODEC mode example 59 // PSC3 in CODEC mode example
191 //i2s@2400 { // PSC3 60 //i2s@2400 { // PSC3
192 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible 61 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
193 // cell-index = <2>; 62 // cell-index = <2>;
194 // reg = <0x2400 0x100>;
195 // interrupts = <2 3 0>;
196 //};
197
198 // PSC4 in uart mode example
199 //serial@2600 { // PSC4
200 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
201 // cell-index = <3>;
202 // reg = <0x2600 0x100>;
203 // interrupts = <2 11 0>;
204 //};
205
206 // PSC5 in uart mode example
207 //serial@2800 { // PSC5
208 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
209 // cell-index = <4>;
210 // reg = <0x2800 0x100>;
211 // interrupts = <2 12 0>;
212 //}; 63 //};
213 64
214 // PSC6 in spi mode example 65 // PSC6 in spi mode example
215 //spi@2c00 { // PSC6 66 //spi@2c00 { // PSC6
216 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 67 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
217 // cell-index = <5>; 68 // cell-index = <5>;
218 // reg = <0x2c00 0x100>;
219 // interrupts = <2 4 0>;
220 //}; 69 //};
221 70
222 ethernet@3000 { 71 ethernet@3000 {
223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
224 reg = <0x3000 0x400>;
225 local-mac-address = [ 00 00 00 00 00 00 ];
226 interrupts = <2 5 0>;
227 phy-handle = <&phy0>; 72 phy-handle = <&phy0>;
228 }; 73 };
229 74
230 mdio@3000 { 75 mdio@3000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
234 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
235 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
236
237 phy0: ethernet-phy@0 { 76 phy0: ethernet-phy@0 {
238 reg = <0>; 77 reg = <0>;
239 }; 78 };
240 }; 79 };
241 80
242 ata@3a00 {
243 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
244 reg = <0x3a00 0x100>;
245 interrupts = <2 7 0>;
246 };
247
248 i2c@3d00 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
252 reg = <0x3d00 0x40>;
253 interrupts = <2 15 0>;
254 };
255
256 i2c@3d40 { 81 i2c@3d40 {
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
260 reg = <0x3d40 0x40>;
261 interrupts = <2 16 0>;
262
263 eeprom@50 { 82 eeprom@50 {
264 compatible = "atmel,24c02"; 83 compatible = "atmel,24c02";
265 reg = <0x50>; 84 reg = <0x50>;
@@ -273,12 +92,6 @@
273 }; 92 };
274 93
275 pci@f0000d00 { 94 pci@f0000d00 {
276 #interrupt-cells = <1>;
277 #size-cells = <2>;
278 #address-cells = <3>;
279 device_type = "pci";
280 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
281 reg = <0xf0000d00 0x100>;
282 interrupt-map-mask = <0xf800 0 0 7>; 95 interrupt-map-mask = <0xf800 0 0 7>;
283 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 96 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
284 0xc000 0 0 2 &mpc5200_pic 1 1 3 97 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -298,11 +111,6 @@
298 }; 111 };
299 112
300 localbus { 113 localbus {
301 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
302
303 #address-cells = <2>;
304 #size-cells = <1>;
305
306 ranges = <0 0 0xfe000000 0x02000000>; 114 ranges = <0 0 0xfe000000 0x02000000>;
307 115
308 flash@0,0 { 116 flash@0,0 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 04:23:19 -0500