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-rw-r--r--arch/powerpc/boot/dts/ebony.dts164
1 files changed, 83 insertions, 81 deletions
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index 5079dc890e0e..ec2d142291b4 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -11,12 +11,14 @@
11 * any warranty of any kind, whether express or implied. 11 * any warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14/dts-v1/;
15
14/ { 16/ {
15 #address-cells = <2>; 17 #address-cells = <2>;
16 #size-cells = <1>; 18 #size-cells = <1>;
17 model = "ibm,ebony"; 19 model = "ibm,ebony";
18 compatible = "ibm,ebony"; 20 compatible = "ibm,ebony";
19 dcr-parent = <&/cpus/cpu@0>; 21 dcr-parent = <&{/cpus/cpu@0}>;
20 22
21 aliases { 23 aliases {
22 ethernet0 = &EMAC0; 24 ethernet0 = &EMAC0;
@@ -32,13 +34,13 @@
32 cpu@0 { 34 cpu@0 {
33 device_type = "cpu"; 35 device_type = "cpu";
34 model = "PowerPC,440GP"; 36 model = "PowerPC,440GP";
35 reg = <0>; 37 reg = <0x00000000>;
36 clock-frequency = <0>; // Filled in by zImage 38 clock-frequency = <0>; // Filled in by zImage
37 timebase-frequency = <0>; // Filled in by zImage 39 timebase-frequency = <0>; // Filled in by zImage
38 i-cache-line-size = <20>; 40 i-cache-line-size = <32>;
39 d-cache-line-size = <20>; 41 d-cache-line-size = <32>;
40 i-cache-size = <8000>; /* 32 kB */ 42 i-cache-size = <32768>; /* 32 kB */
41 d-cache-size = <8000>; /* 32 kB */ 43 d-cache-size = <32768>; /* 32 kB */
42 dcr-controller; 44 dcr-controller;
43 dcr-access-method = "native"; 45 dcr-access-method = "native";
44 }; 46 };
@@ -46,14 +48,14 @@
46 48
47 memory { 49 memory {
48 device_type = "memory"; 50 device_type = "memory";
49 reg = <0 0 0>; // Filled in by zImage 51 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
50 }; 52 };
51 53
52 UIC0: interrupt-controller0 { 54 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440gp", "ibm,uic"; 55 compatible = "ibm,uic-440gp", "ibm,uic";
54 interrupt-controller; 56 interrupt-controller;
55 cell-index = <0>; 57 cell-index = <0>;
56 dcr-reg = <0c0 009>; 58 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>; 59 #address-cells = <0>;
58 #size-cells = <0>; 60 #size-cells = <0>;
59 #interrupt-cells = <2>; 61 #interrupt-cells = <2>;
@@ -64,17 +66,17 @@
64 compatible = "ibm,uic-440gp", "ibm,uic"; 66 compatible = "ibm,uic-440gp", "ibm,uic";
65 interrupt-controller; 67 interrupt-controller;
66 cell-index = <1>; 68 cell-index = <1>;
67 dcr-reg = <0d0 009>; 69 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>; 70 #address-cells = <0>;
69 #size-cells = <0>; 71 #size-cells = <0>;
70 #interrupt-cells = <2>; 72 #interrupt-cells = <2>;
71 interrupts = <1e 4 1f 4>; /* cascade */ 73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
72 interrupt-parent = <&UIC0>; 74 interrupt-parent = <&UIC0>;
73 }; 75 };
74 76
75 CPC0: cpc { 77 CPC0: cpc {
76 compatible = "ibm,cpc-440gp"; 78 compatible = "ibm,cpc-440gp";
77 dcr-reg = <0b0 003 0e0 010>; 79 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
78 // FIXME: anything else? 80 // FIXME: anything else?
79 }; 81 };
80 82
@@ -87,37 +89,37 @@
87 89
88 SDRAM0: memory-controller { 90 SDRAM0: memory-controller {
89 compatible = "ibm,sdram-440gp"; 91 compatible = "ibm,sdram-440gp";
90 dcr-reg = <010 2>; 92 dcr-reg = <0x010 0x002>;
91 // FIXME: anything else? 93 // FIXME: anything else?
92 }; 94 };
93 95
94 SRAM0: sram { 96 SRAM0: sram {
95 compatible = "ibm,sram-440gp"; 97 compatible = "ibm,sram-440gp";
96 dcr-reg = <020 8 00a 1>; 98 dcr-reg = <0x020 0x008 0x00a 0x001>;
97 }; 99 };
98 100
99 DMA0: dma { 101 DMA0: dma {
100 // FIXME: ??? 102 // FIXME: ???
101 compatible = "ibm,dma-440gp"; 103 compatible = "ibm,dma-440gp";
102 dcr-reg = <100 027>; 104 dcr-reg = <0x100 0x027>;
103 }; 105 };
104 106
105 MAL0: mcmal { 107 MAL0: mcmal {
106 compatible = "ibm,mcmal-440gp", "ibm,mcmal"; 108 compatible = "ibm,mcmal-440gp", "ibm,mcmal";
107 dcr-reg = <180 62>; 109 dcr-reg = <0x180 0x062>;
108 num-tx-chans = <4>; 110 num-tx-chans = <4>;
109 num-rx-chans = <4>; 111 num-rx-chans = <4>;
110 interrupt-parent = <&MAL0>; 112 interrupt-parent = <&MAL0>;
111 interrupts = <0 1 2 3 4>; 113 interrupts = <0x0 0x1 0x2 0x3 0x4>;
112 #interrupt-cells = <1>; 114 #interrupt-cells = <1>;
113 #address-cells = <0>; 115 #address-cells = <0>;
114 #size-cells = <0>; 116 #size-cells = <0>;
115 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 117 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
116 /*RXEOB*/ 1 &UIC0 b 4 118 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
117 /*SERR*/ 2 &UIC1 0 4 119 /*SERR*/ 0x2 &UIC1 0x0 0x4
118 /*TXDE*/ 3 &UIC1 1 4 120 /*TXDE*/ 0x3 &UIC1 0x1 0x4
119 /*RXDE*/ 4 &UIC1 2 4>; 121 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
120 interrupt-map-mask = <ffffffff>; 122 interrupt-map-mask = <0xffffffff>;
121 }; 123 };
122 124
123 POB0: opb { 125 POB0: opb {
@@ -126,34 +128,34 @@
126 #size-cells = <1>; 128 #size-cells = <1>;
127 /* Wish there was a nicer way of specifying a full 32-bit 129 /* Wish there was a nicer way of specifying a full 32-bit
128 range */ 130 range */
129 ranges = <00000000 1 00000000 80000000 131 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
130 80000000 1 80000000 80000000>; 132 0x80000000 0x00000001 0x80000000 0x80000000>;
131 dcr-reg = <090 00b>; 133 dcr-reg = <0x090 0x00b>;
132 interrupt-parent = <&UIC1>; 134 interrupt-parent = <&UIC1>;
133 interrupts = <7 4>; 135 interrupts = <0x7 0x4>;
134 clock-frequency = <0>; // Filled in by zImage 136 clock-frequency = <0>; // Filled in by zImage
135 137
136 EBC0: ebc { 138 EBC0: ebc {
137 compatible = "ibm,ebc-440gp", "ibm,ebc"; 139 compatible = "ibm,ebc-440gp", "ibm,ebc";
138 dcr-reg = <012 2>; 140 dcr-reg = <0x012 0x002>;
139 #address-cells = <2>; 141 #address-cells = <2>;
140 #size-cells = <1>; 142 #size-cells = <1>;
141 clock-frequency = <0>; // Filled in by zImage 143 clock-frequency = <0>; // Filled in by zImage
142 // ranges property is supplied by zImage 144 // ranges property is supplied by zImage
143 // based on firmware's configuration of the 145 // based on firmware's configuration of the
144 // EBC bridge 146 // EBC bridge
145 interrupts = <5 4>; 147 interrupts = <0x5 0x4>;
146 interrupt-parent = <&UIC1>; 148 interrupt-parent = <&UIC1>;
147 149
148 small-flash@0,80000 { 150 small-flash@0,80000 {
149 compatible = "jedec-flash"; 151 compatible = "jedec-flash";
150 bank-width = <1>; 152 bank-width = <1>;
151 reg = <0 80000 80000>; 153 reg = <0x00000000 0x00080000 0x00080000>;
152 #address-cells = <1>; 154 #address-cells = <1>;
153 #size-cells = <1>; 155 #size-cells = <1>;
154 partition@0 { 156 partition@0 {
155 label = "OpenBIOS"; 157 label = "OpenBIOS";
156 reg = <0 80000>; 158 reg = <0x00000000 0x00080000>;
157 read-only; 159 read-only;
158 }; 160 };
159 }; 161 };
@@ -161,101 +163,101 @@
161 nvram@1,0 { 163 nvram@1,0 {
162 /* NVRAM & RTC */ 164 /* NVRAM & RTC */
163 compatible = "ds1743-nvram"; 165 compatible = "ds1743-nvram";
164 #bytes = <2000>; 166 #bytes = <0x2000>;
165 reg = <1 0 2000>; 167 reg = <0x00000001 0x00000000 0x00002000>;
166 }; 168 };
167 169
168 large-flash@2,0 { 170 large-flash@2,0 {
169 compatible = "jedec-flash"; 171 compatible = "jedec-flash";
170 bank-width = <1>; 172 bank-width = <1>;
171 reg = <2 0 400000>; 173 reg = <0x00000002 0x00000000 0x00400000>;
172 #address-cells = <1>; 174 #address-cells = <1>;
173 #size-cells = <1>; 175 #size-cells = <1>;
174 partition@0 { 176 partition@0 {
175 label = "fs"; 177 label = "fs";
176 reg = <0 380000>; 178 reg = <0x00000000 0x00380000>;
177 }; 179 };
178 partition@380000 { 180 partition@380000 {
179 label = "firmware"; 181 label = "firmware";
180 reg = <380000 80000>; 182 reg = <0x00380000 0x00080000>;
181 }; 183 };
182 }; 184 };
183 185
184 ir@3,0 { 186 ir@3,0 {
185 reg = <3 0 10>; 187 reg = <0x00000003 0x00000000 0x00000010>;
186 }; 188 };
187 189
188 fpga@7,0 { 190 fpga@7,0 {
189 compatible = "Ebony-FPGA"; 191 compatible = "Ebony-FPGA";
190 reg = <7 0 10>; 192 reg = <0x00000007 0x00000000 0x00000010>;
191 virtual-reg = <e8300000>; 193 virtual-reg = <0xe8300000>;
192 }; 194 };
193 }; 195 };
194 196
195 UART0: serial@40000200 { 197 UART0: serial@40000200 {
196 device_type = "serial"; 198 device_type = "serial";
197 compatible = "ns16550"; 199 compatible = "ns16550";
198 reg = <40000200 8>; 200 reg = <0x40000200 0x00000008>;
199 virtual-reg = <e0000200>; 201 virtual-reg = <0xe0000200>;
200 clock-frequency = <A8C000>; 202 clock-frequency = <11059200>;
201 current-speed = <2580>; 203 current-speed = <9600>;
202 interrupt-parent = <&UIC0>; 204 interrupt-parent = <&UIC0>;
203 interrupts = <0 4>; 205 interrupts = <0x0 0x4>;
204 }; 206 };
205 207
206 UART1: serial@40000300 { 208 UART1: serial@40000300 {
207 device_type = "serial"; 209 device_type = "serial";
208 compatible = "ns16550"; 210 compatible = "ns16550";
209 reg = <40000300 8>; 211 reg = <0x40000300 0x00000008>;
210 virtual-reg = <e0000300>; 212 virtual-reg = <0xe0000300>;
211 clock-frequency = <A8C000>; 213 clock-frequency = <11059200>;
212 current-speed = <2580>; 214 current-speed = <9600>;
213 interrupt-parent = <&UIC0>; 215 interrupt-parent = <&UIC0>;
214 interrupts = <1 4>; 216 interrupts = <0x1 0x4>;
215 }; 217 };
216 218
217 IIC0: i2c@40000400 { 219 IIC0: i2c@40000400 {
218 /* FIXME */ 220 /* FIXME */
219 compatible = "ibm,iic-440gp", "ibm,iic"; 221 compatible = "ibm,iic-440gp", "ibm,iic";
220 reg = <40000400 14>; 222 reg = <0x40000400 0x00000014>;
221 interrupt-parent = <&UIC0>; 223 interrupt-parent = <&UIC0>;
222 interrupts = <2 4>; 224 interrupts = <0x2 0x4>;
223 }; 225 };
224 IIC1: i2c@40000500 { 226 IIC1: i2c@40000500 {
225 /* FIXME */ 227 /* FIXME */
226 compatible = "ibm,iic-440gp", "ibm,iic"; 228 compatible = "ibm,iic-440gp", "ibm,iic";
227 reg = <40000500 14>; 229 reg = <0x40000500 0x00000014>;
228 interrupt-parent = <&UIC0>; 230 interrupt-parent = <&UIC0>;
229 interrupts = <3 4>; 231 interrupts = <0x3 0x4>;
230 }; 232 };
231 233
232 GPIO0: gpio@40000700 { 234 GPIO0: gpio@40000700 {
233 /* FIXME */ 235 /* FIXME */
234 compatible = "ibm,gpio-440gp"; 236 compatible = "ibm,gpio-440gp";
235 reg = <40000700 20>; 237 reg = <0x40000700 0x00000020>;
236 }; 238 };
237 239
238 ZMII0: emac-zmii@40000780 { 240 ZMII0: emac-zmii@40000780 {
239 compatible = "ibm,zmii-440gp", "ibm,zmii"; 241 compatible = "ibm,zmii-440gp", "ibm,zmii";
240 reg = <40000780 c>; 242 reg = <0x40000780 0x0000000c>;
241 }; 243 };
242 244
243 EMAC0: ethernet@40000800 { 245 EMAC0: ethernet@40000800 {
244 device_type = "network"; 246 device_type = "network";
245 compatible = "ibm,emac-440gp", "ibm,emac"; 247 compatible = "ibm,emac-440gp", "ibm,emac";
246 interrupt-parent = <&UIC1>; 248 interrupt-parent = <&UIC1>;
247 interrupts = <1c 4 1d 4>; 249 interrupts = <0x1c 0x4 0x1d 0x4>;
248 reg = <40000800 70>; 250 reg = <0x40000800 0x00000070>;
249 local-mac-address = [000000000000]; // Filled in by zImage 251 local-mac-address = [000000000000]; // Filled in by zImage
250 mal-device = <&MAL0>; 252 mal-device = <&MAL0>;
251 mal-tx-channel = <0 1>; 253 mal-tx-channel = <0 1>;
252 mal-rx-channel = <0>; 254 mal-rx-channel = <0>;
253 cell-index = <0>; 255 cell-index = <0>;
254 max-frame-size = <5dc>; 256 max-frame-size = <1500>;
255 rx-fifo-size = <1000>; 257 rx-fifo-size = <4096>;
256 tx-fifo-size = <800>; 258 tx-fifo-size = <2048>;
257 phy-mode = "rmii"; 259 phy-mode = "rmii";
258 phy-map = <00000001>; 260 phy-map = <0x00000001>;
259 zmii-device = <&ZMII0>; 261 zmii-device = <&ZMII0>;
260 zmii-channel = <0>; 262 zmii-channel = <0>;
261 }; 263 };
@@ -263,18 +265,18 @@
263 device_type = "network"; 265 device_type = "network";
264 compatible = "ibm,emac-440gp", "ibm,emac"; 266 compatible = "ibm,emac-440gp", "ibm,emac";
265 interrupt-parent = <&UIC1>; 267 interrupt-parent = <&UIC1>;
266 interrupts = <1e 4 1f 4>; 268 interrupts = <0x1e 0x4 0x1f 0x4>;
267 reg = <40000900 70>; 269 reg = <0x40000900 0x00000070>;
268 local-mac-address = [000000000000]; // Filled in by zImage 270 local-mac-address = [000000000000]; // Filled in by zImage
269 mal-device = <&MAL0>; 271 mal-device = <&MAL0>;
270 mal-tx-channel = <2 3>; 272 mal-tx-channel = <2 3>;
271 mal-rx-channel = <1>; 273 mal-rx-channel = <1>;
272 cell-index = <1>; 274 cell-index = <1>;
273 max-frame-size = <5dc>; 275 max-frame-size = <1500>;
274 rx-fifo-size = <1000>; 276 rx-fifo-size = <4096>;
275 tx-fifo-size = <800>; 277 tx-fifo-size = <2048>;
276 phy-mode = "rmii"; 278 phy-mode = "rmii";
277 phy-map = <00000001>; 279 phy-map = <0x00000001>;
278 zmii-device = <&ZMII0>; 280 zmii-device = <&ZMII0>;
279 zmii-channel = <1>; 281 zmii-channel = <1>;
280 }; 282 };
@@ -282,9 +284,9 @@
282 284
283 GPT0: gpt@40000a00 { 285 GPT0: gpt@40000a00 {
284 /* FIXME */ 286 /* FIXME */
285 reg = <40000a00 d4>; 287 reg = <0x40000a00 0x000000d4>;
286 interrupt-parent = <&UIC0>; 288 interrupt-parent = <&UIC0>;
287 interrupts = <12 4 13 4 14 4 15 4 16 4>; 289 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
288 }; 290 };
289 291
290 }; 292 };
@@ -296,35 +298,35 @@
296 #address-cells = <3>; 298 #address-cells = <3>;
297 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; 299 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
298 primary; 300 primary;
299 reg = <2 0ec00000 8 /* Config space access */ 301 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
300 0 0 0 /* no IACK cycles */ 302 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
301 2 0ed00000 4 /* Special cycles */ 303 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
302 2 0ec80000 f0 /* Internal registers */ 304 0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
303 2 0ec80100 fc>; /* Internal messaging registers */ 305 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
304 306
305 /* Outbound ranges, one memory and one IO, 307 /* Outbound ranges, one memory and one IO,
306 * later cannot be changed 308 * later cannot be changed
307 */ 309 */
308 ranges = <02000000 0 80000000 00000003 80000000 0 80000000 310 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
309 01000000 0 00000000 00000002 08000000 0 00010000>; 311 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
310 312
311 /* Inbound 2GB range starting at 0 */ 313 /* Inbound 2GB range starting at 0 */
312 dma-ranges = <42000000 0 0 0 0 0 80000000>; 314 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
313 315
314 /* Ebony has all 4 IRQ pins tied together per slot */ 316 /* Ebony has all 4 IRQ pins tied together per slot */
315 interrupt-map-mask = <f800 0 0 0>; 317 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
316 interrupt-map = < 318 interrupt-map = <
317 /* IDSEL 1 */ 319 /* IDSEL 1 */
318 0800 0 0 0 &UIC0 17 8 320 0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
319 321
320 /* IDSEL 2 */ 322 /* IDSEL 2 */
321 1000 0 0 0 &UIC0 18 8 323 0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
322 324
323 /* IDSEL 3 */ 325 /* IDSEL 3 */
324 1800 0 0 0 &UIC0 19 8 326 0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
325 327
326 /* IDSEL 4 */ 328 /* IDSEL 4 */
327 2000 0 0 0 &UIC0 1a 8 329 0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
328 >; 330 >;
329 }; 331 };
330 }; 332 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 23:23:19 -0400