diff options
Diffstat (limited to 'arch/powerpc/boot/dcr.h')
-rw-r--r-- | arch/powerpc/boot/dcr.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index 14b44aa96fea..83b88aa92888 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h | |||
@@ -121,4 +121,22 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C | |||
121 | #define DCRN_CPC0_MIRQ1 0x0ed | 121 | #define DCRN_CPC0_MIRQ1 0x0ed |
122 | #define DCRN_CPC0_JTAGID 0x0ef | 122 | #define DCRN_CPC0_JTAGID 0x0ef |
123 | 123 | ||
124 | #define DCRN_MAL0_CFG 0x180 | ||
125 | #define MAL_RESET 0x80000000 | ||
126 | |||
127 | /* 440EP Clock/Power-on Reset regs */ | ||
128 | #define DCRN_CPR0_ADDR 0xc | ||
129 | #define DCRN_CPR0_DATA 0xd | ||
130 | #define CPR0_PLLD0 0x60 | ||
131 | #define CPR0_OPBD0 0xc0 | ||
132 | #define CPR0_PERD0 0xe0 | ||
133 | #define CPR0_PRIMBD0 0xa0 | ||
134 | #define CPR0_SCPID 0x120 | ||
135 | #define CPR0_PLLC0 0x40 | ||
136 | |||
137 | /* 405GP Clocking/Power Management/Chip Control regs */ | ||
138 | #define DCRN_CPC0_PLLMR 0xb0 | ||
139 | #define DCRN_405_CPC0_CR0 0xb1 | ||
140 | #define DCRN_405_CPC0_CR1 0xb2 | ||
141 | |||
124 | #endif /* _PPC_BOOT_DCR_H_ */ | 142 | #endif /* _PPC_BOOT_DCR_H_ */ |