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1/* 32 and 64-bit millicode, original author Hewlett-Packard
2 adapted for gcc by Paul Bame <bame@debian.org>
3 and Alan Modra <alan@linuxcare.com.au>.
4
5 Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
6
7 This file is part of GCC and is released under the terms of
8 of the GNU General Public License as published by the Free Software
9 Foundation; either version 2, or (at your option) any later version.
10 See the file COPYING in the top-level GCC source directory for a copy
11 of the license. */
12
13#ifdef CONFIG_64BIT
14 .level 2.0w
15#endif
16
17/* Hardware General Registers. */
18r0: .reg %r0
19r1: .reg %r1
20r2: .reg %r2
21r3: .reg %r3
22r4: .reg %r4
23r5: .reg %r5
24r6: .reg %r6
25r7: .reg %r7
26r8: .reg %r8
27r9: .reg %r9
28r10: .reg %r10
29r11: .reg %r11
30r12: .reg %r12
31r13: .reg %r13
32r14: .reg %r14
33r15: .reg %r15
34r16: .reg %r16
35r17: .reg %r17
36r18: .reg %r18
37r19: .reg %r19
38r20: .reg %r20
39r21: .reg %r21
40r22: .reg %r22
41r23: .reg %r23
42r24: .reg %r24
43r25: .reg %r25
44r26: .reg %r26
45r27: .reg %r27
46r28: .reg %r28
47r29: .reg %r29
48r30: .reg %r30
49r31: .reg %r31
50
51/* Hardware Space Registers. */
52sr0: .reg %sr0
53sr1: .reg %sr1
54sr2: .reg %sr2
55sr3: .reg %sr3
56sr4: .reg %sr4
57sr5: .reg %sr5
58sr6: .reg %sr6
59sr7: .reg %sr7
60
61/* Hardware Floating Point Registers. */
62fr0: .reg %fr0
63fr1: .reg %fr1
64fr2: .reg %fr2
65fr3: .reg %fr3
66fr4: .reg %fr4
67fr5: .reg %fr5
68fr6: .reg %fr6
69fr7: .reg %fr7
70fr8: .reg %fr8
71fr9: .reg %fr9
72fr10: .reg %fr10
73fr11: .reg %fr11
74fr12: .reg %fr12
75fr13: .reg %fr13
76fr14: .reg %fr14
77fr15: .reg %fr15
78
79/* Hardware Control Registers. */
80cr11: .reg %cr11
81sar: .reg %cr11 /* Shift Amount Register */
82
83/* Software Architecture General Registers. */
84rp: .reg r2 /* return pointer */
85#ifdef CONFIG_64BIT
86mrp: .reg r2 /* millicode return pointer */
87#else
88mrp: .reg r31 /* millicode return pointer */
89#endif
90ret0: .reg r28 /* return value */
91ret1: .reg r29 /* return value (high part of double) */
92sp: .reg r30 /* stack pointer */
93dp: .reg r27 /* data pointer */
94arg0: .reg r26 /* argument */
95arg1: .reg r25 /* argument or high part of double argument */
96arg2: .reg r24 /* argument */
97arg3: .reg r23 /* argument or high part of double argument */
98
99/* Software Architecture Space Registers. */
100/* sr0 ; return link from BLE */
101sret: .reg sr1 /* return value */
102sarg: .reg sr1 /* argument */
103/* sr4 ; PC SPACE tracker */
104/* sr5 ; process private data */
105
106/* Frame Offsets (millicode convention!) Used when calling other
107 millicode routines. Stack unwinding is dependent upon these
108 definitions. */
109r31_slot: .equ -20 /* "current RP" slot */
110sr0_slot: .equ -16 /* "static link" slot */
111#if defined(CONFIG_64BIT)
112mrp_slot: .equ -16 /* "current RP" slot */
113psp_slot: .equ -8 /* "previous SP" slot */
114#else
115mrp_slot: .equ -20 /* "current RP" slot (replacing "r31_slot") */
116#endif
117
118
119#define DEFINE(name,value)name: .EQU value
120#define RDEFINE(name,value)name: .REG value
121#ifdef milliext
122#define MILLI_BE(lbl) BE lbl(sr7,r0)
123#define MILLI_BEN(lbl) BE,n lbl(sr7,r0)
124#define MILLI_BLE(lbl) BLE lbl(sr7,r0)
125#define MILLI_BLEN(lbl) BLE,n lbl(sr7,r0)
126#define MILLIRETN BE,n 0(sr0,mrp)
127#define MILLIRET BE 0(sr0,mrp)
128#define MILLI_RETN BE,n 0(sr0,mrp)
129#define MILLI_RET BE 0(sr0,mrp)
130#else
131#define MILLI_BE(lbl) B lbl
132#define MILLI_BEN(lbl) B,n lbl
133#define MILLI_BLE(lbl) BL lbl,mrp
134#define MILLI_BLEN(lbl) BL,n lbl,mrp
135#define MILLIRETN BV,n 0(mrp)
136#define MILLIRET BV 0(mrp)
137#define MILLI_RETN BV,n 0(mrp)
138#define MILLI_RET BV 0(mrp)
139#endif
140
141#define CAT(a,b) a##b
142
143#define SUBSPA_MILLI .section .text
144#define SUBSPA_MILLI_DIV .section .text.div,"ax",@progbits! .align 16
145#define SUBSPA_MILLI_MUL .section .text.mul,"ax",@progbits! .align 16
146#define ATTR_MILLI
147#define SUBSPA_DATA .section .data
148#define ATTR_DATA
149#define GLOBAL $global$
150#define GSYM(sym) !sym:
151#define LSYM(sym) !CAT(.L,sym:)
152#define LREF(sym) CAT(.L,sym)
153
154#ifdef L_dyncall
155 SUBSPA_MILLI
156 ATTR_DATA
157GSYM($$dyncall)
158 .export $$dyncall,millicode
159 .proc
160 .callinfo millicode
161 .entry
162 bb,>=,n %r22,30,LREF(1) ; branch if not plabel address
163 depi 0,31,2,%r22 ; clear the two least significant bits
164 ldw 4(%r22),%r19 ; load new LTP value
165 ldw 0(%r22),%r22 ; load address of target
166LSYM(1)
167 bv %r0(%r22) ; branch to the real target
168 stw %r2,-24(%r30) ; save return address into frame marker
169 .exit
170 .procend
171#endif
172
173#ifdef L_divI
174/* ROUTINES: $$divI, $$divoI
175
176 Single precision divide for signed binary integers.
177
178 The quotient is truncated towards zero.
179 The sign of the quotient is the XOR of the signs of the dividend and
180 divisor.
181 Divide by zero is trapped.
182 Divide of -2**31 by -1 is trapped for $$divoI but not for $$divI.
183
184 INPUT REGISTERS:
185 . arg0 == dividend
186 . arg1 == divisor
187 . mrp == return pc
188 . sr0 == return space when called externally
189
190 OUTPUT REGISTERS:
191 . arg0 = undefined
192 . arg1 = undefined
193 . ret1 = quotient
194
195 OTHER REGISTERS AFFECTED:
196 . r1 = undefined
197
198 SIDE EFFECTS:
199 . Causes a trap under the following conditions:
200 . divisor is zero (traps with ADDIT,= 0,25,0)
201 . dividend==-2**31 and divisor==-1 and routine is $$divoI
202 . (traps with ADDO 26,25,0)
203 . Changes memory at the following places:
204 . NONE
205
206 PERMISSIBLE CONTEXT:
207 . Unwindable.
208 . Suitable for internal or external millicode.
209 . Assumes the special millicode register conventions.
210
211 DISCUSSION:
212 . Branchs to other millicode routines using BE
213 . $$div_# for # being 2,3,4,5,6,7,8,9,10,12,14,15
214 .
215 . For selected divisors, calls a divide by constant routine written by
216 . Karl Pettis. Eligible divisors are 1..15 excluding 11 and 13.
217 .
218 . The only overflow case is -2**31 divided by -1.
219 . Both routines return -2**31 but only $$divoI traps. */
220
221RDEFINE(temp,r1)
222RDEFINE(retreg,ret1) /* r29 */
223RDEFINE(temp1,arg0)
224 SUBSPA_MILLI_DIV
225 ATTR_MILLI
226 .import $$divI_2,millicode
227 .import $$divI_3,millicode
228 .import $$divI_4,millicode
229 .import $$divI_5,millicode
230 .import $$divI_6,millicode
231 .import $$divI_7,millicode
232 .import $$divI_8,millicode
233 .import $$divI_9,millicode
234 .import $$divI_10,millicode
235 .import $$divI_12,millicode
236 .import $$divI_14,millicode
237 .import $$divI_15,millicode
238 .export $$divI,millicode
239 .export $$divoI,millicode
240 .proc
241 .callinfo millicode
242 .entry
243GSYM($$divoI)
244 comib,=,n -1,arg1,LREF(negative1) /* when divisor == -1 */
245GSYM($$divI)
246 ldo -1(arg1),temp /* is there at most one bit set ? */
247 and,<> arg1,temp,r0 /* if not, don't use power of 2 divide */
248 addi,> 0,arg1,r0 /* if divisor > 0, use power of 2 divide */
249 b,n LREF(neg_denom)
250LSYM(pow2)
251 addi,>= 0,arg0,retreg /* if numerator is negative, add the */
252 add arg0,temp,retreg /* (denominaotr -1) to correct for shifts */
253 extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
254 extrs retreg,15,16,retreg /* retreg = retreg >> 16 */
255 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
256 ldi 0xcc,temp1 /* setup 0xcc in temp1 */
257 extru,= arg1,23,8,temp /* test denominator with 0xff00 */
258 extrs retreg,23,24,retreg /* retreg = retreg >> 8 */
259 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
260 ldi 0xaa,temp /* setup 0xaa in temp */
261 extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
262 extrs retreg,27,28,retreg /* retreg = retreg >> 4 */
263 and,= arg1,temp1,r0 /* test denominator with 0xcc */
264 extrs retreg,29,30,retreg /* retreg = retreg >> 2 */
265 and,= arg1,temp,r0 /* test denominator with 0xaa */
266 extrs retreg,30,31,retreg /* retreg = retreg >> 1 */
267 MILLIRETN
268LSYM(neg_denom)
269 addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power of 2 */
270 b,n LREF(regular_seq)
271 sub r0,arg1,temp /* make denominator positive */
272 comb,=,n arg1,temp,LREF(regular_seq) /* test against 0x80000000 and 0 */
273 ldo -1(temp),retreg /* is there at most one bit set ? */
274 and,= temp,retreg,r0 /* if so, the denominator is power of 2 */
275 b,n LREF(regular_seq)
276 sub r0,arg0,retreg /* negate numerator */
277 comb,=,n arg0,retreg,LREF(regular_seq) /* test against 0x80000000 */
278 copy retreg,arg0 /* set up arg0, arg1 and temp */
279 copy temp,arg1 /* before branching to pow2 */
280 b LREF(pow2)
281 ldo -1(arg1),temp
282LSYM(regular_seq)
283 comib,>>=,n 15,arg1,LREF(small_divisor)
284 add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
285LSYM(normal)
286 subi 0,retreg,retreg /* make it positive */
287 sub 0,arg1,temp /* clear carry, */
288 /* negate the divisor */
289 ds 0,temp,0 /* set V-bit to the comple- */
290 /* ment of the divisor sign */
291 add retreg,retreg,retreg /* shift msb bit into carry */
292 ds r0,arg1,temp /* 1st divide step, if no carry */
293 addc retreg,retreg,retreg /* shift retreg with/into carry */
294 ds temp,arg1,temp /* 2nd divide step */
295 addc retreg,retreg,retreg /* shift retreg with/into carry */
296 ds temp,arg1,temp /* 3rd divide step */
297 addc retreg,retreg,retreg /* shift retreg with/into carry */
298 ds temp,arg1,temp /* 4th divide step */
299 addc retreg,retreg,retreg /* shift retreg with/into carry */
300 ds temp,arg1,temp /* 5th divide step */
301 addc retreg,retreg,retreg /* shift retreg with/into carry */
302 ds temp,arg1,temp /* 6th divide step */
303 addc retreg,retreg,retreg /* shift retreg with/into carry */
304 ds temp,arg1,temp /* 7th divide step */
305 addc retreg,retreg,retreg /* shift retreg with/into carry */
306 ds temp,arg1,temp /* 8th divide step */
307 addc retreg,retreg,retreg /* shift retreg with/into carry */
308 ds temp,arg1,temp /* 9th divide step */
309 addc retreg,retreg,retreg /* shift retreg with/into carry */
310 ds temp,arg1,temp /* 10th divide step */
311 addc retreg,retreg,retreg /* shift retreg with/into carry */
312 ds temp,arg1,temp /* 11th divide step */
313 addc retreg,retreg,retreg /* shift retreg with/into carry */
314 ds temp,arg1,temp /* 12th divide step */
315 addc retreg,retreg,retreg /* shift retreg with/into carry */
316 ds temp,arg1,temp /* 13th divide step */
317 addc retreg,retreg,retreg /* shift retreg with/into carry */
318 ds temp,arg1,temp /* 14th divide step */
319 addc retreg,retreg,retreg /* shift retreg with/into carry */
320 ds temp,arg1,temp /* 15th divide step */
321 addc retreg,retreg,retreg /* shift retreg with/into carry */
322 ds temp,arg1,temp /* 16th divide step */
323 addc retreg,retreg,retreg /* shift retreg with/into carry */
324 ds temp,arg1,temp /* 17th divide step */
325 addc retreg,retreg,retreg /* shift retreg with/into carry */
326 ds temp,arg1,temp /* 18th divide step */
327 addc retreg,retreg,retreg /* shift retreg with/into carry */
328 ds temp,arg1,temp /* 19th divide step */
329 addc retreg,retreg,retreg /* shift retreg with/into carry */
330 ds temp,arg1,temp /* 20th divide step */
331 addc retreg,retreg,retreg /* shift retreg with/into carry */
332 ds temp,arg1,temp /* 21st divide step */
333 addc retreg,retreg,retreg /* shift retreg with/into carry */
334 ds temp,arg1,temp /* 22nd divide step */
335 addc retreg,retreg,retreg /* shift retreg with/into carry */
336 ds temp,arg1,temp /* 23rd divide step */
337 addc retreg,retreg,retreg /* shift retreg with/into carry */
338 ds temp,arg1,temp /* 24th divide step */
339 addc retreg,retreg,retreg /* shift retreg with/into carry */
340 ds temp,arg1,temp /* 25th divide step */
341 addc retreg,retreg,retreg /* shift retreg with/into carry */
342 ds temp,arg1,temp /* 26th divide step */
343 addc retreg,retreg,retreg /* shift retreg with/into carry */
344 ds temp,arg1,temp /* 27th divide step */
345 addc retreg,retreg,retreg /* shift retreg with/into carry */
346 ds temp,arg1,temp /* 28th divide step */
347 addc retreg,retreg,retreg /* shift retreg with/into carry */
348 ds temp,arg1,temp /* 29th divide step */
349 addc retreg,retreg,retreg /* shift retreg with/into carry */
350 ds temp,arg1,temp /* 30th divide step */
351 addc retreg,retreg,retreg /* shift retreg with/into carry */
352 ds temp,arg1,temp /* 31st divide step */
353 addc retreg,retreg,retreg /* shift retreg with/into carry */
354 ds temp,arg1,temp /* 32nd divide step, */
355 addc retreg,retreg,retreg /* shift last retreg bit into retreg */
356 xor,>= arg0,arg1,0 /* get correct sign of quotient */
357 sub 0,retreg,retreg /* based on operand signs */
358 MILLIRETN
359 nop
360
361LSYM(small_divisor)
362
363#if defined(CONFIG_64BIT)
364/* Clear the upper 32 bits of the arg1 register. We are working with */
365/* small divisors (and 32-bit integers) We must not be mislead */
366/* by "1" bits left in the upper 32 bits. */
367 depd %r0,31,32,%r25
368#endif
369 blr,n arg1,r0
370 nop
371/* table for divisor == 0,1, ... ,15 */
372 addit,= 0,arg1,r0 /* trap if divisor == 0 */
373 nop
374 MILLIRET /* divisor == 1 */
375 copy arg0,retreg
376 MILLI_BEN($$divI_2) /* divisor == 2 */
377 nop
378 MILLI_BEN($$divI_3) /* divisor == 3 */
379 nop
380 MILLI_BEN($$divI_4) /* divisor == 4 */
381 nop
382 MILLI_BEN($$divI_5) /* divisor == 5 */
383 nop
384 MILLI_BEN($$divI_6) /* divisor == 6 */
385 nop
386 MILLI_BEN($$divI_7) /* divisor == 7 */
387 nop
388 MILLI_BEN($$divI_8) /* divisor == 8 */
389 nop
390 MILLI_BEN($$divI_9) /* divisor == 9 */
391 nop
392 MILLI_BEN($$divI_10) /* divisor == 10 */
393 nop
394 b LREF(normal) /* divisor == 11 */
395 add,>= 0,arg0,retreg
396 MILLI_BEN($$divI_12) /* divisor == 12 */
397 nop
398 b LREF(normal) /* divisor == 13 */
399 add,>= 0,arg0,retreg
400 MILLI_BEN($$divI_14) /* divisor == 14 */
401 nop
402 MILLI_BEN($$divI_15) /* divisor == 15 */
403 nop
404
405LSYM(negative1)
406 sub 0,arg0,retreg /* result is negation of dividend */
407 MILLIRET
408 addo arg0,arg1,r0 /* trap iff dividend==0x80000000 && divisor==-1 */
409 .exit
410 .procend
411 .end
412#endif
413
414#ifdef L_divU
415/* ROUTINE: $$divU
416 .
417 . Single precision divide for unsigned integers.
418 .
419 . Quotient is truncated towards zero.
420 . Traps on divide by zero.
421
422 INPUT REGISTERS:
423 . arg0 == dividend
424 . arg1 == divisor
425 . mrp == return pc
426 . sr0 == return space when called externally
427
428 OUTPUT REGISTERS:
429 . arg0 = undefined
430 . arg1 = undefined
431 . ret1 = quotient
432
433 OTHER REGISTERS AFFECTED:
434 . r1 = undefined
435
436 SIDE EFFECTS:
437 . Causes a trap under the following conditions:
438 . divisor is zero
439 . Changes memory at the following places:
440 . NONE
441
442 PERMISSIBLE CONTEXT:
443 . Unwindable.
444 . Does not create a stack frame.
445 . Suitable for internal or external millicode.
446 . Assumes the special millicode register conventions.
447
448 DISCUSSION:
449 . Branchs to other millicode routines using BE:
450 . $$divU_# for 3,5,6,7,9,10,12,14,15
451 .
452 . For selected small divisors calls the special divide by constant
453 . routines written by Karl Pettis. These are: 3,5,6,7,9,10,12,14,15. */
454
455RDEFINE(temp,r1)
456RDEFINE(retreg,ret1) /* r29 */
457RDEFINE(temp1,arg0)
458 SUBSPA_MILLI_DIV
459 ATTR_MILLI
460 .export $$divU,millicode
461 .import $$divU_3,millicode
462 .import $$divU_5,millicode
463 .import $$divU_6,millicode
464 .import $$divU_7,millicode
465 .import $$divU_9,millicode
466 .import $$divU_10,millicode
467 .import $$divU_12,millicode
468 .import $$divU_14,millicode
469 .import $$divU_15,millicode
470 .proc
471 .callinfo millicode
472 .entry
473GSYM($$divU)
474/* The subtract is not nullified since it does no harm and can be used
475 by the two cases that branch back to "normal". */
476 ldo -1(arg1),temp /* is there at most one bit set ? */
477 and,= arg1,temp,r0 /* if so, denominator is power of 2 */
478 b LREF(regular_seq)
479 addit,= 0,arg1,0 /* trap for zero dvr */
480 copy arg0,retreg
481 extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
482 extru retreg,15,16,retreg /* retreg = retreg >> 16 */
483 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
484 ldi 0xcc,temp1 /* setup 0xcc in temp1 */
485 extru,= arg1,23,8,temp /* test denominator with 0xff00 */
486 extru retreg,23,24,retreg /* retreg = retreg >> 8 */
487 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
488 ldi 0xaa,temp /* setup 0xaa in temp */
489 extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
490 extru retreg,27,28,retreg /* retreg = retreg >> 4 */
491 and,= arg1,temp1,r0 /* test denominator with 0xcc */
492 extru retreg,29,30,retreg /* retreg = retreg >> 2 */
493 and,= arg1,temp,r0 /* test denominator with 0xaa */
494 extru retreg,30,31,retreg /* retreg = retreg >> 1 */
495 MILLIRETN
496 nop
497LSYM(regular_seq)
498 comib,>= 15,arg1,LREF(special_divisor)
499 subi 0,arg1,temp /* clear carry, negate the divisor */
500 ds r0,temp,r0 /* set V-bit to 1 */
501LSYM(normal)
502 add arg0,arg0,retreg /* shift msb bit into carry */
503 ds r0,arg1,temp /* 1st divide step, if no carry */
504 addc retreg,retreg,retreg /* shift retreg with/into carry */
505 ds temp,arg1,temp /* 2nd divide step */
506 addc retreg,retreg,retreg /* shift retreg with/into carry */
507 ds temp,arg1,temp /* 3rd divide step */
508 addc retreg,retreg,retreg /* shift retreg with/into carry */
509 ds temp,arg1,temp /* 4th divide step */
510 addc retreg,retreg,retreg /* shift retreg with/into carry */
511 ds temp,arg1,temp /* 5th divide step */
512 addc retreg,retreg,retreg /* shift retreg with/into carry */
513 ds temp,arg1,temp /* 6th divide step */
514 addc retreg,retreg,retreg /* shift retreg with/into carry */
515 ds temp,arg1,temp /* 7th divide step */
516 addc retreg,retreg,retreg /* shift retreg with/into carry */
517 ds temp,arg1,temp /* 8th divide step */
518 addc retreg,retreg,retreg /* shift retreg with/into carry */
519 ds temp,arg1,temp /* 9th divide step */
520 addc retreg,retreg,retreg /* shift retreg with/into carry */
521 ds temp,arg1,temp /* 10th divide step */
522 addc retreg,retreg,retreg /* shift retreg with/into carry */
523 ds temp,arg1,temp /* 11th divide step */
524 addc retreg,retreg,retreg /* shift retreg with/into carry */
525 ds temp,arg1,temp /* 12th divide step */
526 addc retreg,retreg,retreg /* shift retreg with/into carry */
527 ds temp,arg1,temp /* 13th divide step */
528 addc retreg,retreg,retreg /* shift retreg with/into carry */
529 ds temp,arg1,temp /* 14th divide step */
530 addc retreg,retreg,retreg /* shift retreg with/into carry */
531 ds temp,arg1,temp /* 15th divide step */
532 addc retreg,retreg,retreg /* shift retreg with/into carry */
533 ds temp,arg1,temp /* 16th divide step */
534 addc retreg,retreg,retreg /* shift retreg with/into carry */
535 ds temp,arg1,temp /* 17th divide step */
536 addc retreg,retreg,retreg /* shift retreg with/into carry */
537 ds temp,arg1,temp /* 18th divide step */
538 addc retreg,retreg,retreg /* shift retreg with/into carry */
539 ds temp,arg1,temp /* 19th divide step */
540 addc retreg,retreg,retreg /* shift retreg with/into carry */
541 ds temp,arg1,temp /* 20th divide step */
542 addc retreg,retreg,retreg /* shift retreg with/into carry */
543 ds temp,arg1,temp /* 21st divide step */
544 addc retreg,retreg,retreg /* shift retreg with/into carry */
545 ds temp,arg1,temp /* 22nd divide step */
546 addc retreg,retreg,retreg /* shift retreg with/into carry */
547 ds temp,arg1,temp /* 23rd divide step */
548 addc retreg,retreg,retreg /* shift retreg with/into carry */
549 ds temp,arg1,temp /* 24th divide step */
550 addc retreg,retreg,retreg /* shift retreg with/into carry */
551 ds temp,arg1,temp /* 25th divide step */
552 addc retreg,retreg,retreg /* shift retreg with/into carry */
553 ds temp,arg1,temp /* 26th divide step */
554 addc retreg,retreg,retreg /* shift retreg with/into carry */
555 ds temp,arg1,temp /* 27th divide step */
556 addc retreg,retreg,retreg /* shift retreg with/into carry */
557 ds temp,arg1,temp /* 28th divide step */
558 addc retreg,retreg,retreg /* shift retreg with/into carry */
559 ds temp,arg1,temp /* 29th divide step */
560 addc retreg,retreg,retreg /* shift retreg with/into carry */
561 ds temp,arg1,temp /* 30th divide step */
562 addc retreg,retreg,retreg /* shift retreg with/into carry */
563 ds temp,arg1,temp /* 31st divide step */
564 addc retreg,retreg,retreg /* shift retreg with/into carry */
565 ds temp,arg1,temp /* 32nd divide step, */
566 MILLIRET
567 addc retreg,retreg,retreg /* shift last retreg bit into retreg */
568
569/* Handle the cases where divisor is a small constant or has high bit on. */
570LSYM(special_divisor)
571/* blr arg1,r0 */
572/* comib,>,n 0,arg1,LREF(big_divisor) ; nullify previous instruction */
573
574/* Pratap 8/13/90. The 815 Stirling chip set has a bug that prevents us from
575 generating such a blr, comib sequence. A problem in nullification. So I
576 rewrote this code. */
577
578#if defined(CONFIG_64BIT)
579/* Clear the upper 32 bits of the arg1 register. We are working with
580 small divisors (and 32-bit unsigned integers) We must not be mislead
581 by "1" bits left in the upper 32 bits. */
582 depd %r0,31,32,%r25
583#endif
584 comib,> 0,arg1,LREF(big_divisor)
585 nop
586 blr arg1,r0
587 nop
588
589LSYM(zero_divisor) /* this label is here to provide external visibility */
590 addit,= 0,arg1,0 /* trap for zero dvr */
591 nop
592 MILLIRET /* divisor == 1 */
593 copy arg0,retreg
594 MILLIRET /* divisor == 2 */
595 extru arg0,30,31,retreg
596 MILLI_BEN($$divU_3) /* divisor == 3 */
597 nop
598 MILLIRET /* divisor == 4 */
599 extru arg0,29,30,retreg
600 MILLI_BEN($$divU_5) /* divisor == 5 */
601 nop
602 MILLI_BEN($$divU_6) /* divisor == 6 */
603 nop
604 MILLI_BEN($$divU_7) /* divisor == 7 */
605 nop
606 MILLIRET /* divisor == 8 */
607 extru arg0,28,29,retreg
608 MILLI_BEN($$divU_9) /* divisor == 9 */
609 nop
610 MILLI_BEN($$divU_10) /* divisor == 10 */
611 nop
612 b LREF(normal) /* divisor == 11 */
613 ds r0,temp,r0 /* set V-bit to 1 */
614 MILLI_BEN($$divU_12) /* divisor == 12 */
615 nop
616 b LREF(normal) /* divisor == 13 */
617 ds r0,temp,r0 /* set V-bit to 1 */
618 MILLI_BEN($$divU_14) /* divisor == 14 */
619 nop
620 MILLI_BEN($$divU_15) /* divisor == 15 */
621 nop
622
623/* Handle the case where the high bit is on in the divisor.
624 Compute: if( dividend>=divisor) quotient=1; else quotient=0;
625 Note: dividend>==divisor iff dividend-divisor does not borrow
626 and not borrow iff carry. */
627LSYM(big_divisor)
628 sub arg0,arg1,r0
629 MILLIRET
630 addc r0,r0,retreg
631 .exit
632 .procend
633 .end
634#endif
635
636#ifdef L_remI
637/* ROUTINE: $$remI
638
639 DESCRIPTION:
640 . $$remI returns the remainder of the division of two signed 32-bit
641 . integers. The sign of the remainder is the same as the sign of
642 . the dividend.
643
644
645 INPUT REGISTERS:
646 . arg0 == dividend
647 . arg1 == divisor
648 . mrp == return pc
649 . sr0 == return space when called externally
650
651 OUTPUT REGISTERS:
652 . arg0 = destroyed
653 . arg1 = destroyed
654 . ret1 = remainder
655
656 OTHER REGISTERS AFFECTED:
657 . r1 = undefined
658
659 SIDE EFFECTS:
660 . Causes a trap under the following conditions: DIVIDE BY ZERO
661 . Changes memory at the following places: NONE
662
663 PERMISSIBLE CONTEXT:
664 . Unwindable
665 . Does not create a stack frame
666 . Is usable for internal or external microcode
667
668 DISCUSSION:
669 . Calls other millicode routines via mrp: NONE
670 . Calls other millicode routines: NONE */
671
672RDEFINE(tmp,r1)
673RDEFINE(retreg,ret1)
674
675 SUBSPA_MILLI
676 ATTR_MILLI
677 .proc
678 .callinfo millicode
679 .entry
680GSYM($$remI)
681GSYM($$remoI)
682 .export $$remI,MILLICODE
683 .export $$remoI,MILLICODE
684 ldo -1(arg1),tmp /* is there at most one bit set ? */
685 and,<> arg1,tmp,r0 /* if not, don't use power of 2 */
686 addi,> 0,arg1,r0 /* if denominator > 0, use power */
687 /* of 2 */
688 b,n LREF(neg_denom)
689LSYM(pow2)
690 comb,>,n 0,arg0,LREF(neg_num) /* is numerator < 0 ? */
691 and arg0,tmp,retreg /* get the result */
692 MILLIRETN
693LSYM(neg_num)
694 subi 0,arg0,arg0 /* negate numerator */
695 and arg0,tmp,retreg /* get the result */
696 subi 0,retreg,retreg /* negate result */
697 MILLIRETN
698LSYM(neg_denom)
699 addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power */
700 /* of 2 */
701 b,n LREF(regular_seq)
702 sub r0,arg1,tmp /* make denominator positive */
703 comb,=,n arg1,tmp,LREF(regular_seq) /* test against 0x80000000 and 0 */
704 ldo -1(tmp),retreg /* is there at most one bit set ? */
705 and,= tmp,retreg,r0 /* if not, go to regular_seq */
706 b,n LREF(regular_seq)
707 comb,>,n 0,arg0,LREF(neg_num_2) /* if arg0 < 0, negate it */
708 and arg0,retreg,retreg
709 MILLIRETN
710LSYM(neg_num_2)
711 subi 0,arg0,tmp /* test against 0x80000000 */
712 and tmp,retreg,retreg
713 subi 0,retreg,retreg
714 MILLIRETN
715LSYM(regular_seq)
716 addit,= 0,arg1,0 /* trap if div by zero */
717 add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
718 sub 0,retreg,retreg /* make it positive */
719 sub 0,arg1, tmp /* clear carry, */
720 /* negate the divisor */
721 ds 0, tmp,0 /* set V-bit to the comple- */
722 /* ment of the divisor sign */
723 or 0,0, tmp /* clear tmp */
724 add retreg,retreg,retreg /* shift msb bit into carry */
725 ds tmp,arg1, tmp /* 1st divide step, if no carry */
726 /* out, msb of quotient = 0 */
727 addc retreg,retreg,retreg /* shift retreg with/into carry */
728LSYM(t1)
729 ds tmp,arg1, tmp /* 2nd divide step */
730 addc retreg,retreg,retreg /* shift retreg with/into carry */
731 ds tmp,arg1, tmp /* 3rd divide step */
732 addc retreg,retreg,retreg /* shift retreg with/into carry */
733 ds tmp,arg1, tmp /* 4th divide step */
734 addc retreg,retreg,retreg /* shift retreg with/into carry */
735 ds tmp,arg1, tmp /* 5th divide step */
736 addc retreg,retreg,retreg /* shift retreg with/into carry */
737 ds tmp,arg1, tmp /* 6th divide step */
738 addc retreg,retreg,retreg /* shift retreg with/into carry */
739 ds tmp,arg1, tmp /* 7th divide step */
740 addc retreg,retreg,retreg /* shift retreg with/into carry */
741 ds tmp,arg1, tmp /* 8th divide step */
742 addc retreg,retreg,retreg /* shift retreg with/into carry */
743 ds tmp,arg1, tmp /* 9th divide step */
744 addc retreg,retreg,retreg /* shift retreg with/into carry */
745 ds tmp,arg1, tmp /* 10th divide step */
746 addc retreg,retreg,retreg /* shift retreg with/into carry */
747 ds tmp,arg1, tmp /* 11th divide step */
748 addc retreg,retreg,retreg /* shift retreg with/into carry */
749 ds tmp,arg1, tmp /* 12th divide step */
750 addc retreg,retreg,retreg /* shift retreg with/into carry */
751 ds tmp,arg1, tmp /* 13th divide step */
752 addc retreg,retreg,retreg /* shift retreg with/into carry */
753 ds tmp,arg1, tmp /* 14th divide step */
754 addc retreg,retreg,retreg /* shift retreg with/into carry */
755 ds tmp,arg1, tmp /* 15th divide step */
756 addc retreg,retreg,retreg /* shift retreg with/into carry */
757 ds tmp,arg1, tmp /* 16th divide step */
758 addc retreg,retreg,retreg /* shift retreg with/into carry */
759 ds tmp,arg1, tmp /* 17th divide step */
760 addc retreg,retreg,retreg /* shift retreg with/into carry */
761 ds tmp,arg1, tmp /* 18th divide step */
762 addc retreg,retreg,retreg /* shift retreg with/into carry */
763 ds tmp,arg1, tmp /* 19th divide step */
764 addc retreg,retreg,retreg /* shift retreg with/into carry */
765 ds tmp,arg1, tmp /* 20th divide step */
766 addc retreg,retreg,retreg /* shift retreg with/into carry */
767 ds tmp,arg1, tmp /* 21st divide step */
768 addc retreg,retreg,retreg /* shift retreg with/into carry */
769 ds tmp,arg1, tmp /* 22nd divide step */
770 addc retreg,retreg,retreg /* shift retreg with/into carry */
771 ds tmp,arg1, tmp /* 23rd divide step */
772 addc retreg,retreg,retreg /* shift retreg with/into carry */
773 ds tmp,arg1, tmp /* 24th divide step */
774 addc retreg,retreg,retreg /* shift retreg with/into carry */
775 ds tmp,arg1, tmp /* 25th divide step */
776 addc retreg,retreg,retreg /* shift retreg with/into carry */
777 ds tmp,arg1, tmp /* 26th divide step */
778 addc retreg,retreg,retreg /* shift retreg with/into carry */
779 ds tmp,arg1, tmp /* 27th divide step */
780 addc retreg,retreg,retreg /* shift retreg with/into carry */
781 ds tmp,arg1, tmp /* 28th divide step */
782 addc retreg,retreg,retreg /* shift retreg with/into carry */
783 ds tmp,arg1, tmp /* 29th divide step */
784 addc retreg,retreg,retreg /* shift retreg with/into carry */
785 ds tmp,arg1, tmp /* 30th divide step */
786 addc retreg,retreg,retreg /* shift retreg with/into carry */
787 ds tmp,arg1, tmp /* 31st divide step */
788 addc retreg,retreg,retreg /* shift retreg with/into carry */
789 ds tmp,arg1, tmp /* 32nd divide step, */
790 addc retreg,retreg,retreg /* shift last bit into retreg */
791 movb,>=,n tmp,retreg,LREF(finish) /* branch if pos. tmp */
792 add,< arg1,0,0 /* if arg1 > 0, add arg1 */
793 add,tr tmp,arg1,retreg /* for correcting remainder tmp */
794 sub tmp,arg1,retreg /* else add absolute value arg1 */
795LSYM(finish)
796 add,>= arg0,0,0 /* set sign of remainder */
797 sub 0,retreg,retreg /* to sign of dividend */
798 MILLIRET
799 nop
800 .exit
801 .procend
802#ifdef milliext
803 .origin 0x00000200
804#endif
805 .end
806#endif
807
808#ifdef L_remU
809/* ROUTINE: $$remU
810 . Single precision divide for remainder with unsigned binary integers.
811 .
812 . The remainder must be dividend-(dividend/divisor)*divisor.
813 . Divide by zero is trapped.
814
815 INPUT REGISTERS:
816 . arg0 == dividend
817 . arg1 == divisor
818 . mrp == return pc
819 . sr0 == return space when called externally
820
821 OUTPUT REGISTERS:
822 . arg0 = undefined
823 . arg1 = undefined
824 . ret1 = remainder
825
826 OTHER REGISTERS AFFECTED:
827 . r1 = undefined
828
829 SIDE EFFECTS:
830 . Causes a trap under the following conditions: DIVIDE BY ZERO
831 . Changes memory at the following places: NONE
832
833 PERMISSIBLE CONTEXT:
834 . Unwindable.
835 . Does not create a stack frame.
836 . Suitable for internal or external millicode.
837 . Assumes the special millicode register conventions.
838
839 DISCUSSION:
840 . Calls other millicode routines using mrp: NONE
841 . Calls other millicode routines: NONE */
842
843
844RDEFINE(temp,r1)
845RDEFINE(rmndr,ret1) /* r29 */
846 SUBSPA_MILLI
847 ATTR_MILLI
848 .export $$remU,millicode
849 .proc
850 .callinfo millicode
851 .entry
852GSYM($$remU)
853 ldo -1(arg1),temp /* is there at most one bit set ? */
854 and,= arg1,temp,r0 /* if not, don't use power of 2 */
855 b LREF(regular_seq)
856 addit,= 0,arg1,r0 /* trap on div by zero */
857 and arg0,temp,rmndr /* get the result for power of 2 */
858 MILLIRETN
859LSYM(regular_seq)
860 comib,>=,n 0,arg1,LREF(special_case)
861 subi 0,arg1,rmndr /* clear carry, negate the divisor */
862 ds r0,rmndr,r0 /* set V-bit to 1 */
863 add arg0,arg0,temp /* shift msb bit into carry */
864 ds r0,arg1,rmndr /* 1st divide step, if no carry */
865 addc temp,temp,temp /* shift temp with/into carry */
866 ds rmndr,arg1,rmndr /* 2nd divide step */
867 addc temp,temp,temp /* shift temp with/into carry */
868 ds rmndr,arg1,rmndr /* 3rd divide step */
869 addc temp,temp,temp /* shift temp with/into carry */
870 ds rmndr,arg1,rmndr /* 4th divide step */
871 addc temp,temp,temp /* shift temp with/into carry */
872 ds rmndr,arg1,rmndr /* 5th divide step */
873 addc temp,temp,temp /* shift temp with/into carry */
874 ds rmndr,arg1,rmndr /* 6th divide step */
875 addc temp,temp,temp /* shift temp with/into carry */
876 ds rmndr,arg1,rmndr /* 7th divide step */
877 addc temp,temp,temp /* shift temp with/into carry */
878 ds rmndr,arg1,rmndr /* 8th divide step */
879 addc temp,temp,temp /* shift temp with/into carry */
880 ds rmndr,arg1,rmndr /* 9th divide step */
881 addc temp,temp,temp /* shift temp with/into carry */
882 ds rmndr,arg1,rmndr /* 10th divide step */
883 addc temp,temp,temp /* shift temp with/into carry */
884 ds rmndr,arg1,rmndr /* 11th divide step */
885 addc temp,temp,temp /* shift temp with/into carry */
886 ds rmndr,arg1,rmndr /* 12th divide step */
887 addc temp,temp,temp /* shift temp with/into carry */
888 ds rmndr,arg1,rmndr /* 13th divide step */
889 addc temp,temp,temp /* shift temp with/into carry */
890 ds rmndr,arg1,rmndr /* 14th divide step */
891 addc temp,temp,temp /* shift temp with/into carry */
892 ds rmndr,arg1,rmndr /* 15th divide step */
893 addc temp,temp,temp /* shift temp with/into carry */
894 ds rmndr,arg1,rmndr /* 16th divide step */
895 addc temp,temp,temp /* shift temp with/into carry */
896 ds rmndr,arg1,rmndr /* 17th divide step */
897 addc temp,temp,temp /* shift temp with/into carry */
898 ds rmndr,arg1,rmndr /* 18th divide step */
899 addc temp,temp,temp /* shift temp with/into carry */
900 ds rmndr,arg1,rmndr /* 19th divide step */
901 addc temp,temp,temp /* shift temp with/into carry */
902 ds rmndr,arg1,rmndr /* 20th divide step */
903 addc temp,temp,temp /* shift temp with/into carry */
904 ds rmndr,arg1,rmndr /* 21st divide step */
905 addc temp,temp,temp /* shift temp with/into carry */
906 ds rmndr,arg1,rmndr /* 22nd divide step */
907 addc temp,temp,temp /* shift temp with/into carry */
908 ds rmndr,arg1,rmndr /* 23rd divide step */
909 addc temp,temp,temp /* shift temp with/into carry */
910 ds rmndr,arg1,rmndr /* 24th divide step */
911 addc temp,temp,temp /* shift temp with/into carry */
912 ds rmndr,arg1,rmndr /* 25th divide step */
913 addc temp,temp,temp /* shift temp with/into carry */
914 ds rmndr,arg1,rmndr /* 26th divide step */
915 addc temp,temp,temp /* shift temp with/into carry */
916 ds rmndr,arg1,rmndr /* 27th divide step */
917 addc temp,temp,temp /* shift temp with/into carry */
918 ds rmndr,arg1,rmndr /* 28th divide step */
919 addc temp,temp,temp /* shift temp with/into carry */
920 ds rmndr,arg1,rmndr /* 29th divide step */
921 addc temp,temp,temp /* shift temp with/into carry */
922 ds rmndr,arg1,rmndr /* 30th divide step */
923 addc temp,temp,temp /* shift temp with/into carry */
924 ds rmndr,arg1,rmndr /* 31st divide step */
925 addc temp,temp,temp /* shift temp with/into carry */
926 ds rmndr,arg1,rmndr /* 32nd divide step, */
927 comiclr,<= 0,rmndr,r0
928 add rmndr,arg1,rmndr /* correction */
929 MILLIRETN
930 nop
931
932/* Putting >= on the last DS and deleting COMICLR does not work! */
933LSYM(special_case)
934 sub,>>= arg0,arg1,rmndr
935 copy arg0,rmndr
936 MILLIRETN
937 nop
938 .exit
939 .procend
940 .end
941#endif
942
943#ifdef L_div_const
944/* ROUTINE: $$divI_2
945 . $$divI_3 $$divU_3
946 . $$divI_4
947 . $$divI_5 $$divU_5
948 . $$divI_6 $$divU_6
949 . $$divI_7 $$divU_7
950 . $$divI_8
951 . $$divI_9 $$divU_9
952 . $$divI_10 $$divU_10
953 .
954 . $$divI_12 $$divU_12
955 .
956 . $$divI_14 $$divU_14
957 . $$divI_15 $$divU_15
958 . $$divI_16
959 . $$divI_17 $$divU_17
960 .
961 . Divide by selected constants for single precision binary integers.
962
963 INPUT REGISTERS:
964 . arg0 == dividend
965 . mrp == return pc
966 . sr0 == return space when called externally
967
968 OUTPUT REGISTERS:
969 . arg0 = undefined
970 . arg1 = undefined
971 . ret1 = quotient
972
973 OTHER REGISTERS AFFECTED:
974 . r1 = undefined
975
976 SIDE EFFECTS:
977 . Causes a trap under the following conditions: NONE
978 . Changes memory at the following places: NONE
979
980 PERMISSIBLE CONTEXT:
981 . Unwindable.
982 . Does not create a stack frame.
983 . Suitable for internal or external millicode.
984 . Assumes the special millicode register conventions.
985
986 DISCUSSION:
987 . Calls other millicode routines using mrp: NONE
988 . Calls other millicode routines: NONE */
989
990
991/* TRUNCATED DIVISION BY SMALL INTEGERS
992
993 We are interested in q(x) = floor(x/y), where x >= 0 and y > 0
994 (with y fixed).
995
996 Let a = floor(z/y), for some choice of z. Note that z will be
997 chosen so that division by z is cheap.
998
999 Let r be the remainder(z/y). In other words, r = z - ay.
1000
1001 Now, our method is to choose a value for b such that
1002
1003 q'(x) = floor((ax+b)/z)
1004
1005 is equal to q(x) over as large a range of x as possible. If the
1006 two are equal over a sufficiently large range, and if it is easy to
1007 form the product (ax), and it is easy to divide by z, then we can
1008 perform the division much faster than the general division algorithm.
1009
1010 So, we want the following to be true:
1011
1012 . For x in the following range:
1013 .
1014 . ky <= x < (k+1)y
1015 .
1016 . implies that
1017 .
1018 . k <= (ax+b)/z < (k+1)
1019
1020 We want to determine b such that this is true for all k in the
1021 range {0..K} for some maximum K.
1022
1023 Since (ax+b) is an increasing function of x, we can take each
1024 bound separately to determine the "best" value for b.
1025
1026 (ax+b)/z < (k+1) implies
1027
1028 (a((k+1)y-1)+b < (k+1)z implies
1029
1030 b < a + (k+1)(z-ay) implies
1031
1032 b < a + (k+1)r
1033
1034 This needs to be true for all k in the range {0..K}. In
1035 particular, it is true for k = 0 and this leads to a maximum
1036 acceptable value for b.
1037
1038 b < a+r or b <= a+r-1
1039
1040 Taking the other bound, we have
1041
1042 k <= (ax+b)/z implies
1043
1044 k <= (aky+b)/z implies
1045
1046 k(z-ay) <= b implies
1047
1048 kr <= b
1049
1050 Clearly, the largest range for k will be achieved by maximizing b,
1051 when r is not zero. When r is zero, then the simplest choice for b
1052 is 0. When r is not 0, set
1053
1054 . b = a+r-1
1055
1056 Now, by construction, q'(x) = floor((ax+b)/z) = q(x) = floor(x/y)
1057 for all x in the range:
1058
1059 . 0 <= x < (K+1)y
1060
1061 We need to determine what K is. Of our two bounds,
1062
1063 . b < a+(k+1)r is satisfied for all k >= 0, by construction.
1064
1065 The other bound is
1066
1067 . kr <= b
1068
1069 This is always true if r = 0. If r is not 0 (the usual case), then
1070 K = floor((a+r-1)/r), is the maximum value for k.
1071
1072 Therefore, the formula q'(x) = floor((ax+b)/z) yields the correct
1073 answer for q(x) = floor(x/y) when x is in the range
1074
1075 (0,(K+1)y-1) K = floor((a+r-1)/r)
1076
1077 To be most useful, we want (K+1)y-1 = (max x) >= 2**32-1 so that
1078 the formula for q'(x) yields the correct value of q(x) for all x
1079 representable by a single word in HPPA.
1080
1081 We are also constrained in that computing the product (ax), adding
1082 b, and dividing by z must all be done quickly, otherwise we will be
1083 better off going through the general algorithm using the DS
1084 instruction, which uses approximately 70 cycles.
1085
1086 For each y, there is a choice of z which satisfies the constraints
1087 for (K+1)y >= 2**32. We may not, however, be able to satisfy the
1088 timing constraints for arbitrary y. It seems that z being equal to
1089 a power of 2 or a power of 2 minus 1 is as good as we can do, since
1090 it minimizes the time to do division by z. We want the choice of z
1091 to also result in a value for (a) that minimizes the computation of
1092 the product (ax). This is best achieved if (a) has a regular bit
1093 pattern (so the multiplication can be done with shifts and adds).
1094 The value of (a) also needs to be less than 2**32 so the product is
1095 always guaranteed to fit in 2 words.
1096
1097 In actual practice, the following should be done:
1098
1099 1) For negative x, you should take the absolute value and remember
1100 . the fact so that the result can be negated. This obviously does
1101 . not apply in the unsigned case.
1102 2) For even y, you should factor out the power of 2 that divides y
1103 . and divide x by it. You can then proceed by dividing by the
1104 . odd factor of y.
1105
1106 Here is a table of some odd values of y, and corresponding choices
1107 for z which are "good".
1108
1109 y z r a (hex) max x (hex)
1110
1111 3 2**32 1 55555555 100000001
1112 5 2**32 1 33333333 100000003
1113 7 2**24-1 0 249249 (infinite)
1114 9 2**24-1 0 1c71c7 (infinite)
1115 11 2**20-1 0 1745d (infinite)
1116 13 2**24-1 0 13b13b (infinite)
1117 15 2**32 1 11111111 10000000d
1118 17 2**32 1 f0f0f0f 10000000f
1119
1120 If r is 1, then b = a+r-1 = a. This simplifies the computation
1121 of (ax+b), since you can compute (x+1)(a) instead. If r is 0,
1122 then b = 0 is ok to use which simplifies (ax+b).
1123
1124 The bit patterns for 55555555, 33333333, and 11111111 are obviously
1125 very regular. The bit patterns for the other values of a above are:
1126
1127 y (hex) (binary)
1128
1129 7 249249 001001001001001001001001 << regular >>
1130 9 1c71c7 000111000111000111000111 << regular >>
1131 11 1745d 000000010111010001011101 << irregular >>
1132 13 13b13b 000100111011000100111011 << irregular >>
1133
1134 The bit patterns for (a) corresponding to (y) of 11 and 13 may be
1135 too irregular to warrant using this method.
1136
1137 When z is a power of 2 minus 1, then the division by z is slightly
1138 more complicated, involving an iterative solution.
1139
1140 The code presented here solves division by 1 through 17, except for
1141 11 and 13. There are algorithms for both signed and unsigned
1142 quantities given.
1143
1144 TIMINGS (cycles)
1145
1146 divisor positive negative unsigned
1147
1148 . 1 2 2 2
1149 . 2 4 4 2
1150 . 3 19 21 19
1151 . 4 4 4 2
1152 . 5 18 22 19
1153 . 6 19 22 19
1154 . 8 4 4 2
1155 . 10 18 19 17
1156 . 12 18 20 18
1157 . 15 16 18 16
1158 . 16 4 4 2
1159 . 17 16 18 16
1160
1161 Now, the algorithm for 7, 9, and 14 is an iterative one. That is,
1162 a loop body is executed until the tentative quotient is 0. The
1163 number of times the loop body is executed varies depending on the
1164 dividend, but is never more than two times. If the dividend is
1165 less than the divisor, then the loop body is not executed at all.
1166 Each iteration adds 4 cycles to the timings.
1167
1168 divisor positive negative unsigned
1169
1170 . 7 19+4n 20+4n 20+4n n = number of iterations
1171 . 9 21+4n 22+4n 21+4n
1172 . 14 21+4n 22+4n 20+4n
1173
1174 To give an idea of how the number of iterations varies, here is a
1175 table of dividend versus number of iterations when dividing by 7.
1176
1177 smallest largest required
1178 dividend dividend iterations
1179
1180 . 0 6 0
1181 . 7 0x6ffffff 1
1182 0x1000006 0xffffffff 2
1183
1184 There is some overlap in the range of numbers requiring 1 and 2
1185 iterations. */
1186
1187RDEFINE(t2,r1)
1188RDEFINE(x2,arg0) /* r26 */
1189RDEFINE(t1,arg1) /* r25 */
1190RDEFINE(x1,ret1) /* r29 */
1191
1192 SUBSPA_MILLI_DIV
1193 ATTR_MILLI
1194
1195 .proc
1196 .callinfo millicode
1197 .entry
1198/* NONE of these routines require a stack frame
1199 ALL of these routines are unwindable from millicode */
1200
1201GSYM($$divide_by_constant)
1202 .export $$divide_by_constant,millicode
1203/* Provides a "nice" label for the code covered by the unwind descriptor
1204 for things like gprof. */
1205
1206/* DIVISION BY 2 (shift by 1) */
1207GSYM($$divI_2)
1208 .export $$divI_2,millicode
1209 comclr,>= arg0,0,0
1210 addi 1,arg0,arg0
1211 MILLIRET
1212 extrs arg0,30,31,ret1
1213
1214
1215/* DIVISION BY 4 (shift by 2) */
1216GSYM($$divI_4)
1217 .export $$divI_4,millicode
1218 comclr,>= arg0,0,0
1219 addi 3,arg0,arg0
1220 MILLIRET
1221 extrs arg0,29,30,ret1
1222
1223
1224/* DIVISION BY 8 (shift by 3) */
1225GSYM($$divI_8)
1226 .export $$divI_8,millicode
1227 comclr,>= arg0,0,0
1228 addi 7,arg0,arg0
1229 MILLIRET
1230 extrs arg0,28,29,ret1
1231
1232/* DIVISION BY 16 (shift by 4) */
1233GSYM($$divI_16)
1234 .export $$divI_16,millicode
1235 comclr,>= arg0,0,0
1236 addi 15,arg0,arg0
1237 MILLIRET
1238 extrs arg0,27,28,ret1
1239
1240/****************************************************************************
1241*
1242* DIVISION BY DIVISORS OF FFFFFFFF, and powers of 2 times these
1243*
1244* includes 3,5,15,17 and also 6,10,12
1245*
1246****************************************************************************/
1247
1248/* DIVISION BY 3 (use z = 2**32; a = 55555555) */
1249
1250GSYM($$divI_3)
1251 .export $$divI_3,millicode
1252 comb,<,N x2,0,LREF(neg3)
1253
1254 addi 1,x2,x2 /* this cannot overflow */
1255 extru x2,1,2,x1 /* multiply by 5 to get started */
1256 sh2add x2,x2,x2
1257 b LREF(pos)
1258 addc x1,0,x1
1259
1260LSYM(neg3)
1261 subi 1,x2,x2 /* this cannot overflow */
1262 extru x2,1,2,x1 /* multiply by 5 to get started */
1263 sh2add x2,x2,x2
1264 b LREF(neg)
1265 addc x1,0,x1
1266
1267GSYM($$divU_3)
1268 .export $$divU_3,millicode
1269 addi 1,x2,x2 /* this CAN overflow */
1270 addc 0,0,x1
1271 shd x1,x2,30,t1 /* multiply by 5 to get started */
1272 sh2add x2,x2,x2
1273 b LREF(pos)
1274 addc x1,t1,x1
1275
1276/* DIVISION BY 5 (use z = 2**32; a = 33333333) */
1277
1278GSYM($$divI_5)
1279 .export $$divI_5,millicode
1280 comb,<,N x2,0,LREF(neg5)
1281
1282 addi 3,x2,t1 /* this cannot overflow */
1283 sh1add x2,t1,x2 /* multiply by 3 to get started */
1284 b LREF(pos)
1285 addc 0,0,x1
1286
1287LSYM(neg5)
1288 sub 0,x2,x2 /* negate x2 */
1289 addi 1,x2,x2 /* this cannot overflow */
1290 shd 0,x2,31,x1 /* get top bit (can be 1) */
1291 sh1add x2,x2,x2 /* multiply by 3 to get started */
1292 b LREF(neg)
1293 addc x1,0,x1
1294
1295GSYM($$divU_5)
1296 .export $$divU_5,millicode
1297 addi 1,x2,x2 /* this CAN overflow */
1298 addc 0,0,x1
1299 shd x1,x2,31,t1 /* multiply by 3 to get started */
1300 sh1add x2,x2,x2
1301 b LREF(pos)
1302 addc t1,x1,x1
1303
1304/* DIVISION BY 6 (shift to divide by 2 then divide by 3) */
1305GSYM($$divI_6)
1306 .export $$divI_6,millicode
1307 comb,<,N x2,0,LREF(neg6)
1308 extru x2,30,31,x2 /* divide by 2 */
1309 addi 5,x2,t1 /* compute 5*(x2+1) = 5*x2+5 */
1310 sh2add x2,t1,x2 /* multiply by 5 to get started */
1311 b LREF(pos)
1312 addc 0,0,x1
1313
1314LSYM(neg6)
1315 subi 2,x2,x2 /* negate, divide by 2, and add 1 */
1316 /* negation and adding 1 are done */
1317 /* at the same time by the SUBI */
1318 extru x2,30,31,x2
1319 shd 0,x2,30,x1
1320 sh2add x2,x2,x2 /* multiply by 5 to get started */
1321 b LREF(neg)
1322 addc x1,0,x1
1323
1324GSYM($$divU_6)
1325 .export $$divU_6,millicode
1326 extru x2,30,31,x2 /* divide by 2 */
1327 addi 1,x2,x2 /* cannot carry */
1328 shd 0,x2,30,x1 /* multiply by 5 to get started */
1329 sh2add x2,x2,x2
1330 b LREF(pos)
1331 addc x1,0,x1
1332
1333/* DIVISION BY 10 (shift to divide by 2 then divide by 5) */
1334GSYM($$divU_10)
1335 .export $$divU_10,millicode
1336 extru x2,30,31,x2 /* divide by 2 */
1337 addi 3,x2,t1 /* compute 3*(x2+1) = (3*x2)+3 */
1338 sh1add x2,t1,x2 /* multiply by 3 to get started */
1339 addc 0,0,x1
1340LSYM(pos)
1341 shd x1,x2,28,t1 /* multiply by 0x11 */
1342 shd x2,0,28,t2
1343 add x2,t2,x2
1344 addc x1,t1,x1
1345LSYM(pos_for_17)
1346 shd x1,x2,24,t1 /* multiply by 0x101 */
1347 shd x2,0,24,t2
1348 add x2,t2,x2
1349 addc x1,t1,x1
1350
1351 shd x1,x2,16,t1 /* multiply by 0x10001 */
1352 shd x2,0,16,t2
1353 add x2,t2,x2
1354 MILLIRET
1355 addc x1,t1,x1
1356
1357GSYM($$divI_10)
1358 .export $$divI_10,millicode
1359 comb,< x2,0,LREF(neg10)
1360 copy 0,x1
1361 extru x2,30,31,x2 /* divide by 2 */
1362 addib,TR 1,x2,LREF(pos) /* add 1 (cannot overflow) */
1363 sh1add x2,x2,x2 /* multiply by 3 to get started */
1364
1365LSYM(neg10)
1366 subi 2,x2,x2 /* negate, divide by 2, and add 1 */
1367 /* negation and adding 1 are done */
1368 /* at the same time by the SUBI */
1369 extru x2,30,31,x2
1370 sh1add x2,x2,x2 /* multiply by 3 to get started */
1371LSYM(neg)
1372 shd x1,x2,28,t1 /* multiply by 0x11 */
1373 shd x2,0,28,t2
1374 add x2,t2,x2
1375 addc x1,t1,x1
1376LSYM(neg_for_17)
1377 shd x1,x2,24,t1 /* multiply by 0x101 */
1378 shd x2,0,24,t2
1379 add x2,t2,x2
1380 addc x1,t1,x1
1381
1382 shd x1,x2,16,t1 /* multiply by 0x10001 */
1383 shd x2,0,16,t2
1384 add x2,t2,x2
1385 addc x1,t1,x1
1386 MILLIRET
1387 sub 0,x1,x1
1388
1389/* DIVISION BY 12 (shift to divide by 4 then divide by 3) */
1390GSYM($$divI_12)
1391 .export $$divI_12,millicode
1392 comb,< x2,0,LREF(neg12)
1393 copy 0,x1
1394 extru x2,29,30,x2 /* divide by 4 */
1395 addib,tr 1,x2,LREF(pos) /* compute 5*(x2+1) = 5*x2+5 */
1396 sh2add x2,x2,x2 /* multiply by 5 to get started */
1397
1398LSYM(neg12)
1399 subi 4,x2,x2 /* negate, divide by 4, and add 1 */
1400 /* negation and adding 1 are done */
1401 /* at the same time by the SUBI */
1402 extru x2,29,30,x2
1403 b LREF(neg)
1404 sh2add x2,x2,x2 /* multiply by 5 to get started */
1405
1406GSYM($$divU_12)
1407 .export $$divU_12,millicode
1408 extru x2,29,30,x2 /* divide by 4 */
1409 addi 5,x2,t1 /* cannot carry */
1410 sh2add x2,t1,x2 /* multiply by 5 to get started */
1411 b LREF(pos)
1412 addc 0,0,x1
1413
1414/* DIVISION BY 15 (use z = 2**32; a = 11111111) */
1415GSYM($$divI_15)
1416 .export $$divI_15,millicode
1417 comb,< x2,0,LREF(neg15)
1418 copy 0,x1
1419 addib,tr 1,x2,LREF(pos)+4
1420 shd x1,x2,28,t1
1421
1422LSYM(neg15)
1423 b LREF(neg)
1424 subi 1,x2,x2
1425
1426GSYM($$divU_15)
1427 .export $$divU_15,millicode
1428 addi 1,x2,x2 /* this CAN overflow */
1429 b LREF(pos)
1430 addc 0,0,x1
1431
1432/* DIVISION BY 17 (use z = 2**32; a = f0f0f0f) */
1433GSYM($$divI_17)
1434 .export $$divI_17,millicode
1435 comb,<,n x2,0,LREF(neg17)
1436 addi 1,x2,x2 /* this cannot overflow */
1437 shd 0,x2,28,t1 /* multiply by 0xf to get started */
1438 shd x2,0,28,t2
1439 sub t2,x2,x2
1440 b LREF(pos_for_17)
1441 subb t1,0,x1
1442
1443LSYM(neg17)
1444 subi 1,x2,x2 /* this cannot overflow */
1445 shd 0,x2,28,t1 /* multiply by 0xf to get started */
1446 shd x2,0,28,t2
1447 sub t2,x2,x2
1448 b LREF(neg_for_17)
1449 subb t1,0,x1
1450
1451GSYM($$divU_17)
1452 .export $$divU_17,millicode
1453 addi 1,x2,x2 /* this CAN overflow */
1454 addc 0,0,x1
1455 shd x1,x2,28,t1 /* multiply by 0xf to get started */
1456LSYM(u17)
1457 shd x2,0,28,t2
1458 sub t2,x2,x2
1459 b LREF(pos_for_17)
1460 subb t1,x1,x1
1461
1462
1463/* DIVISION BY DIVISORS OF FFFFFF, and powers of 2 times these
1464 includes 7,9 and also 14
1465
1466
1467 z = 2**24-1
1468 r = z mod x = 0
1469
1470 so choose b = 0
1471
1472 Also, in order to divide by z = 2**24-1, we approximate by dividing
1473 by (z+1) = 2**24 (which is easy), and then correcting.
1474
1475 (ax) = (z+1)q' + r
1476 . = zq' + (q'+r)
1477
1478 So to compute (ax)/z, compute q' = (ax)/(z+1) and r = (ax) mod (z+1)
1479 Then the true remainder of (ax)/z is (q'+r). Repeat the process
1480 with this new remainder, adding the tentative quotients together,
1481 until a tentative quotient is 0 (and then we are done). There is
1482 one last correction to be done. It is possible that (q'+r) = z.
1483 If so, then (q'+r)/(z+1) = 0 and it looks like we are done. But,
1484 in fact, we need to add 1 more to the quotient. Now, it turns
1485 out that this happens if and only if the original value x is
1486 an exact multiple of y. So, to avoid a three instruction test at
1487 the end, instead use 1 instruction to add 1 to x at the beginning. */
1488
1489/* DIVISION BY 7 (use z = 2**24-1; a = 249249) */
1490GSYM($$divI_7)
1491 .export $$divI_7,millicode
1492 comb,<,n x2,0,LREF(neg7)
1493LSYM(7)
1494 addi 1,x2,x2 /* cannot overflow */
1495 shd 0,x2,29,x1
1496 sh3add x2,x2,x2
1497 addc x1,0,x1
1498LSYM(pos7)
1499 shd x1,x2,26,t1
1500 shd x2,0,26,t2
1501 add x2,t2,x2
1502 addc x1,t1,x1
1503
1504 shd x1,x2,20,t1
1505 shd x2,0,20,t2
1506 add x2,t2,x2
1507 addc x1,t1,t1
1508
1509 /* computed <t1,x2>. Now divide it by (2**24 - 1) */
1510
1511 copy 0,x1
1512 shd,= t1,x2,24,t1 /* tentative quotient */
1513LSYM(1)
1514 addb,tr t1,x1,LREF(2) /* add to previous quotient */
1515 extru x2,31,24,x2 /* new remainder (unadjusted) */
1516
1517 MILLIRETN
1518
1519LSYM(2)
1520 addb,tr t1,x2,LREF(1) /* adjust remainder */
1521 extru,= x2,7,8,t1 /* new quotient */
1522
1523LSYM(neg7)
1524 subi 1,x2,x2 /* negate x2 and add 1 */
1525LSYM(8)
1526 shd 0,x2,29,x1
1527 sh3add x2,x2,x2
1528 addc x1,0,x1
1529
1530LSYM(neg7_shift)
1531 shd x1,x2,26,t1
1532 shd x2,0,26,t2
1533 add x2,t2,x2
1534 addc x1,t1,x1
1535
1536 shd x1,x2,20,t1
1537 shd x2,0,20,t2
1538 add x2,t2,x2
1539 addc x1,t1,t1
1540
1541 /* computed <t1,x2>. Now divide it by (2**24 - 1) */
1542
1543 copy 0,x1
1544 shd,= t1,x2,24,t1 /* tentative quotient */
1545LSYM(3)
1546 addb,tr t1,x1,LREF(4) /* add to previous quotient */
1547 extru x2,31,24,x2 /* new remainder (unadjusted) */
1548
1549 MILLIRET
1550 sub 0,x1,x1 /* negate result */
1551
1552LSYM(4)
1553 addb,tr t1,x2,LREF(3) /* adjust remainder */
1554 extru,= x2,7,8,t1 /* new quotient */
1555
1556GSYM($$divU_7)
1557 .export $$divU_7,millicode
1558 addi 1,x2,x2 /* can carry */
1559 addc 0,0,x1
1560 shd x1,x2,29,t1
1561 sh3add x2,x2,x2
1562 b LREF(pos7)
1563 addc t1,x1,x1
1564
1565/* DIVISION BY 9 (use z = 2**24-1; a = 1c71c7) */
1566GSYM($$divI_9)
1567 .export $$divI_9,millicode
1568 comb,<,n x2,0,LREF(neg9)
1569 addi 1,x2,x2 /* cannot overflow */
1570 shd 0,x2,29,t1
1571 shd x2,0,29,t2
1572 sub t2,x2,x2
1573 b LREF(pos7)
1574 subb t1,0,x1
1575
1576LSYM(neg9)
1577 subi 1,x2,x2 /* negate and add 1 */
1578 shd 0,x2,29,t1
1579 shd x2,0,29,t2
1580 sub t2,x2,x2
1581 b LREF(neg7_shift)
1582 subb t1,0,x1
1583
1584GSYM($$divU_9)
1585 .export $$divU_9,millicode
1586 addi 1,x2,x2 /* can carry */
1587 addc 0,0,x1
1588 shd x1,x2,29,t1
1589 shd x2,0,29,t2
1590 sub t2,x2,x2
1591 b LREF(pos7)
1592 subb t1,x1,x1
1593
1594/* DIVISION BY 14 (shift to divide by 2 then divide by 7) */
1595GSYM($$divI_14)
1596 .export $$divI_14,millicode
1597 comb,<,n x2,0,LREF(neg14)
1598GSYM($$divU_14)
1599 .export $$divU_14,millicode
1600 b LREF(7) /* go to 7 case */
1601 extru x2,30,31,x2 /* divide by 2 */
1602
1603LSYM(neg14)
1604 subi 2,x2,x2 /* negate (and add 2) */
1605 b LREF(8)
1606 extru x2,30,31,x2 /* divide by 2 */
1607 .exit
1608 .procend
1609 .end
1610#endif
1611
1612#ifdef L_mulI
1613/* VERSION "@(#)$$mulI $ Revision: 12.4 $ $ Date: 94/03/17 17:18:51 $" */
1614/******************************************************************************
1615This routine is used on PA2.0 processors when gcc -mno-fpregs is used
1616
1617ROUTINE: $$mulI
1618
1619
1620DESCRIPTION:
1621
1622 $$mulI multiplies two single word integers, giving a single
1623 word result.
1624
1625
1626INPUT REGISTERS:
1627
1628 arg0 = Operand 1
1629 arg1 = Operand 2
1630 r31 == return pc
1631 sr0 == return space when called externally
1632
1633
1634OUTPUT REGISTERS:
1635
1636 arg0 = undefined
1637 arg1 = undefined
1638 ret1 = result
1639
1640OTHER REGISTERS AFFECTED:
1641
1642 r1 = undefined
1643
1644SIDE EFFECTS:
1645
1646 Causes a trap under the following conditions: NONE
1647 Changes memory at the following places: NONE
1648
1649PERMISSIBLE CONTEXT:
1650
1651 Unwindable
1652 Does not create a stack frame
1653 Is usable for internal or external microcode
1654
1655DISCUSSION:
1656
1657 Calls other millicode routines via mrp: NONE
1658 Calls other millicode routines: NONE
1659
1660***************************************************************************/
1661
1662
1663#define a0 %arg0
1664#define a1 %arg1
1665#define t0 %r1
1666#define r %ret1
1667
1668#define a0__128a0 zdep a0,24,25,a0
1669#define a0__256a0 zdep a0,23,24,a0
1670#define a1_ne_0_b_l0 comb,<> a1,0,LREF(l0)
1671#define a1_ne_0_b_l1 comb,<> a1,0,LREF(l1)
1672#define a1_ne_0_b_l2 comb,<> a1,0,LREF(l2)
1673#define b_n_ret_t0 b,n LREF(ret_t0)
1674#define b_e_shift b LREF(e_shift)
1675#define b_e_t0ma0 b LREF(e_t0ma0)
1676#define b_e_t0 b LREF(e_t0)
1677#define b_e_t0a0 b LREF(e_t0a0)
1678#define b_e_t02a0 b LREF(e_t02a0)
1679#define b_e_t04a0 b LREF(e_t04a0)
1680#define b_e_2t0 b LREF(e_2t0)
1681#define b_e_2t0a0 b LREF(e_2t0a0)
1682#define b_e_2t04a0 b LREF(e2t04a0)
1683#define b_e_3t0 b LREF(e_3t0)
1684#define b_e_4t0 b LREF(e_4t0)
1685#define b_e_4t0a0 b LREF(e_4t0a0)
1686#define b_e_4t08a0 b LREF(e4t08a0)
1687#define b_e_5t0 b LREF(e_5t0)
1688#define b_e_8t0 b LREF(e_8t0)
1689#define b_e_8t0a0 b LREF(e_8t0a0)
1690#define r__r_a0 add r,a0,r
1691#define r__r_2a0 sh1add a0,r,r
1692#define r__r_4a0 sh2add a0,r,r
1693#define r__r_8a0 sh3add a0,r,r
1694#define r__r_t0 add r,t0,r
1695#define r__r_2t0 sh1add t0,r,r
1696#define r__r_4t0 sh2add t0,r,r
1697#define r__r_8t0 sh3add t0,r,r
1698#define t0__3a0 sh1add a0,a0,t0
1699#define t0__4a0 sh2add a0,0,t0
1700#define t0__5a0 sh2add a0,a0,t0
1701#define t0__8a0 sh3add a0,0,t0
1702#define t0__9a0 sh3add a0,a0,t0
1703#define t0__16a0 zdep a0,27,28,t0
1704#define t0__32a0 zdep a0,26,27,t0
1705#define t0__64a0 zdep a0,25,26,t0
1706#define t0__128a0 zdep a0,24,25,t0
1707#define t0__t0ma0 sub t0,a0,t0
1708#define t0__t0_a0 add t0,a0,t0
1709#define t0__t0_2a0 sh1add a0,t0,t0
1710#define t0__t0_4a0 sh2add a0,t0,t0
1711#define t0__t0_8a0 sh3add a0,t0,t0
1712#define t0__2t0_a0 sh1add t0,a0,t0
1713#define t0__3t0 sh1add t0,t0,t0
1714#define t0__4t0 sh2add t0,0,t0
1715#define t0__4t0_a0 sh2add t0,a0,t0
1716#define t0__5t0 sh2add t0,t0,t0
1717#define t0__8t0 sh3add t0,0,t0
1718#define t0__8t0_a0 sh3add t0,a0,t0
1719#define t0__9t0 sh3add t0,t0,t0
1720#define t0__16t0 zdep t0,27,28,t0
1721#define t0__32t0 zdep t0,26,27,t0
1722#define t0__256a0 zdep a0,23,24,t0
1723
1724
1725 SUBSPA_MILLI
1726 ATTR_MILLI
1727 .align 16
1728 .proc
1729 .callinfo millicode
1730 .export $$mulI,millicode
1731GSYM($$mulI)
1732 combt,<<= a1,a0,LREF(l4) /* swap args if unsigned a1>a0 */
1733 copy 0,r /* zero out the result */
1734 xor a0,a1,a0 /* swap a0 & a1 using the */
1735 xor a0,a1,a1 /* old xor trick */
1736 xor a0,a1,a0
1737LSYM(l4)
1738 combt,<= 0,a0,LREF(l3) /* if a0>=0 then proceed like unsigned */
1739 zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
1740 sub,> 0,a1,t0 /* otherwise negate both and */
1741 combt,<=,n a0,t0,LREF(l2) /* swap back if |a0|<|a1| */
1742 sub 0,a0,a1
1743 movb,tr,n t0,a0,LREF(l2) /* 10th inst. */
1744
1745LSYM(l0) r__r_t0 /* add in this partial product */
1746LSYM(l1) a0__256a0 /* a0 <<= 8 ****************** */
1747LSYM(l2) zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
1748LSYM(l3) blr t0,0 /* case on these 8 bits ****** */
1749 extru a1,23,24,a1 /* a1 >>= 8 ****************** */
1750
1751/*16 insts before this. */
1752/* a0 <<= 8 ************************** */
1753LSYM(x0) a1_ne_0_b_l2 ! a0__256a0 ! MILLIRETN ! nop
1754LSYM(x1) a1_ne_0_b_l1 ! r__r_a0 ! MILLIRETN ! nop
1755LSYM(x2) a1_ne_0_b_l1 ! r__r_2a0 ! MILLIRETN ! nop
1756LSYM(x3) a1_ne_0_b_l0 ! t0__3a0 ! MILLIRET ! r__r_t0
1757LSYM(x4) a1_ne_0_b_l1 ! r__r_4a0 ! MILLIRETN ! nop
1758LSYM(x5) a1_ne_0_b_l0 ! t0__5a0 ! MILLIRET ! r__r_t0
1759LSYM(x6) t0__3a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1760LSYM(x7) t0__3a0 ! a1_ne_0_b_l0 ! r__r_4a0 ! b_n_ret_t0
1761LSYM(x8) a1_ne_0_b_l1 ! r__r_8a0 ! MILLIRETN ! nop
1762LSYM(x9) a1_ne_0_b_l0 ! t0__9a0 ! MILLIRET ! r__r_t0
1763LSYM(x10) t0__5a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1764LSYM(x11) t0__3a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
1765LSYM(x12) t0__3a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1766LSYM(x13) t0__5a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
1767LSYM(x14) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1768LSYM(x15) t0__5a0 ! a1_ne_0_b_l0 ! t0__3t0 ! b_n_ret_t0
1769LSYM(x16) t0__16a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1770LSYM(x17) t0__9a0 ! a1_ne_0_b_l0 ! t0__t0_8a0 ! b_n_ret_t0
1771LSYM(x18) t0__9a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1772LSYM(x19) t0__9a0 ! a1_ne_0_b_l0 ! t0__2t0_a0 ! b_n_ret_t0
1773LSYM(x20) t0__5a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1774LSYM(x21) t0__5a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1775LSYM(x22) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1776LSYM(x23) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
1777LSYM(x24) t0__3a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1778LSYM(x25) t0__5a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
1779LSYM(x26) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1780LSYM(x27) t0__3a0 ! a1_ne_0_b_l0 ! t0__9t0 ! b_n_ret_t0
1781LSYM(x28) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1782LSYM(x29) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1783LSYM(x30) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
1784LSYM(x31) t0__32a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1785LSYM(x32) t0__32a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1786LSYM(x33) t0__8a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1787LSYM(x34) t0__16a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1788LSYM(x35) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__t0_8a0
1789LSYM(x36) t0__9a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1790LSYM(x37) t0__9a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1791LSYM(x38) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1792LSYM(x39) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
1793LSYM(x40) t0__5a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1794LSYM(x41) t0__5a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
1795LSYM(x42) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1796LSYM(x43) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1797LSYM(x44) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1798LSYM(x45) t0__9a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
1799LSYM(x46) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_a0
1800LSYM(x47) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_2a0
1801LSYM(x48) t0__3a0 ! a1_ne_0_b_l0 ! t0__16t0 ! b_n_ret_t0
1802LSYM(x49) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_4a0
1803LSYM(x50) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
1804LSYM(x51) t0__9a0 ! t0__t0_8a0 ! b_e_t0 ! t0__3t0
1805LSYM(x52) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1806LSYM(x53) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1807LSYM(x54) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
1808LSYM(x55) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__2t0_a0
1809LSYM(x56) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1810LSYM(x57) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__3t0
1811LSYM(x58) t0__3a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1812LSYM(x59) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__3t0
1813LSYM(x60) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1814LSYM(x61) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1815LSYM(x62) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
1816LSYM(x63) t0__64a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1817LSYM(x64) t0__64a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1818LSYM(x65) t0__8a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
1819LSYM(x66) t0__32a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1820LSYM(x67) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1821LSYM(x68) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1822LSYM(x69) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1823LSYM(x70) t0__64a0 ! t0__t0_4a0 ! b_e_t0 ! t0__t0_2a0
1824LSYM(x71) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__t0ma0
1825LSYM(x72) t0__9a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1826LSYM(x73) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_t0
1827LSYM(x74) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1828LSYM(x75) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1829LSYM(x76) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1830LSYM(x77) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1831LSYM(x78) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__2t0_a0
1832LSYM(x79) t0__16a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
1833LSYM(x80) t0__16a0 ! t0__5t0 ! b_e_shift ! r__r_t0
1834LSYM(x81) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_t0
1835LSYM(x82) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
1836LSYM(x83) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1837LSYM(x84) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1838LSYM(x85) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
1839LSYM(x86) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1840LSYM(x87) t0__9a0 ! t0__9t0 ! b_e_t02a0 ! t0__t0_4a0
1841LSYM(x88) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1842LSYM(x89) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1843LSYM(x90) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
1844LSYM(x91) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__2t0_a0
1845LSYM(x92) t0__5a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
1846LSYM(x93) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__3t0
1847LSYM(x94) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__t0_2a0
1848LSYM(x95) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
1849LSYM(x96) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1850LSYM(x97) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1851LSYM(x98) t0__32a0 ! t0__3t0 ! b_e_t0 ! t0__t0_2a0
1852LSYM(x99) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
1853LSYM(x100) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
1854LSYM(x101) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
1855LSYM(x102) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
1856LSYM(x103) t0__5a0 ! t0__5t0 ! b_e_t02a0 ! t0__4t0_a0
1857LSYM(x104) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
1858LSYM(x105) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
1859LSYM(x106) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__4t0_a0
1860LSYM(x107) t0__9a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__8t0_a0
1861LSYM(x108) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1862LSYM(x109) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1863LSYM(x110) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__2t0_a0
1864LSYM(x111) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
1865LSYM(x112) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__16t0
1866LSYM(x113) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__3t0
1867LSYM(x114) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__3t0
1868LSYM(x115) t0__9a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__3t0
1869LSYM(x116) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__4t0_a0
1870LSYM(x117) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
1871LSYM(x118) t0__3a0 ! t0__4t0_a0 ! b_e_t0a0 ! t0__9t0
1872LSYM(x119) t0__3a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__9t0
1873LSYM(x120) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
1874LSYM(x121) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
1875LSYM(x122) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
1876LSYM(x123) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
1877LSYM(x124) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
1878LSYM(x125) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
1879LSYM(x126) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
1880LSYM(x127) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1881LSYM(x128) t0__128a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1882LSYM(x129) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0_a0 ! b_n_ret_t0
1883LSYM(x130) t0__64a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1884LSYM(x131) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1885LSYM(x132) t0__8a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1886LSYM(x133) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1887LSYM(x134) t0__8a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1888LSYM(x135) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__3t0
1889LSYM(x136) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1890LSYM(x137) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1891LSYM(x138) t0__8a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1892LSYM(x139) t0__8a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__4t0_a0
1893LSYM(x140) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__5t0
1894LSYM(x141) t0__8a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__2t0_a0
1895LSYM(x142) t0__9a0 ! t0__8t0 ! b_e_2t0 ! t0__t0ma0
1896LSYM(x143) t0__16a0 ! t0__9t0 ! b_e_t0 ! t0__t0ma0
1897LSYM(x144) t0__9a0 ! t0__8t0 ! b_e_shift ! r__r_2t0
1898LSYM(x145) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__2t0_a0
1899LSYM(x146) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
1900LSYM(x147) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1901LSYM(x148) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1902LSYM(x149) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1903LSYM(x150) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1904LSYM(x151) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
1905LSYM(x152) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1906LSYM(x153) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1907LSYM(x154) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1908LSYM(x155) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__5t0
1909LSYM(x156) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
1910LSYM(x157) t0__32a0 ! t0__t0ma0 ! b_e_t02a0 ! t0__5t0
1911LSYM(x158) t0__16a0 ! t0__5t0 ! b_e_2t0 ! t0__t0ma0
1912LSYM(x159) t0__32a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
1913LSYM(x160) t0__5a0 ! t0__4t0 ! b_e_shift ! r__r_8t0
1914LSYM(x161) t0__8a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
1915LSYM(x162) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_2t0
1916LSYM(x163) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__2t0_a0
1917LSYM(x164) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_4t0
1918LSYM(x165) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
1919LSYM(x166) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__2t0_a0
1920LSYM(x167) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
1921LSYM(x168) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
1922LSYM(x169) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__8t0_a0
1923LSYM(x170) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__5t0
1924LSYM(x171) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__9t0
1925LSYM(x172) t0__5a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__2t0_a0
1926LSYM(x173) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__9t0
1927LSYM(x174) t0__32a0 ! t0__t0_2a0 ! b_e_t04a0 ! t0__5t0
1928LSYM(x175) t0__8a0 ! t0__2t0_a0 ! b_e_5t0 ! t0__2t0_a0
1929LSYM(x176) t0__5a0 ! t0__4t0_a0 ! b_e_8t0 ! t0__t0_a0
1930LSYM(x177) t0__5a0 ! t0__4t0_a0 ! b_e_8t0a0 ! t0__t0_a0
1931LSYM(x178) t0__5a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__8t0_a0
1932LSYM(x179) t0__5a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__8t0_a0
1933LSYM(x180) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
1934LSYM(x181) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
1935LSYM(x182) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__2t0_a0
1936LSYM(x183) t0__9a0 ! t0__5t0 ! b_e_2t0a0 ! t0__2t0_a0
1937LSYM(x184) t0__5a0 ! t0__9t0 ! b_e_4t0 ! t0__t0_a0
1938LSYM(x185) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
1939LSYM(x186) t0__32a0 ! t0__t0ma0 ! b_e_2t0 ! t0__3t0
1940LSYM(x187) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__5t0
1941LSYM(x188) t0__9a0 ! t0__5t0 ! b_e_4t0 ! t0__t0_2a0
1942LSYM(x189) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
1943LSYM(x190) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__5t0
1944LSYM(x191) t0__64a0 ! t0__3t0 ! b_e_t0 ! t0__t0ma0
1945LSYM(x192) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
1946LSYM(x193) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
1947LSYM(x194) t0__8a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
1948LSYM(x195) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
1949LSYM(x196) t0__8a0 ! t0__3t0 ! b_e_4t0 ! t0__2t0_a0
1950LSYM(x197) t0__8a0 ! t0__3t0 ! b_e_4t0a0 ! t0__2t0_a0
1951LSYM(x198) t0__64a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
1952LSYM(x199) t0__8a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
1953LSYM(x200) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_8t0
1954LSYM(x201) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__8t0_a0
1955LSYM(x202) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__4t0_a0
1956LSYM(x203) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__4t0_a0
1957LSYM(x204) t0__8a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
1958LSYM(x205) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__5t0
1959LSYM(x206) t0__64a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__3t0
1960LSYM(x207) t0__8a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
1961LSYM(x208) t0__5a0 ! t0__5t0 ! b_e_8t0 ! t0__t0_a0
1962LSYM(x209) t0__5a0 ! t0__5t0 ! b_e_8t0a0 ! t0__t0_a0
1963LSYM(x210) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__5t0
1964LSYM(x211) t0__5a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__5t0
1965LSYM(x212) t0__3a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__4t0_a0
1966LSYM(x213) t0__3a0 ! t0__4t0_a0 ! b_e_4t0a0 ! t0__4t0_a0
1967LSYM(x214) t0__9a0 ! t0__t0_4a0 ! b_e_2t04a0 ! t0__8t0_a0
1968LSYM(x215) t0__5a0 ! t0__4t0_a0 ! b_e_5t0 ! t0__2t0_a0
1969LSYM(x216) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
1970LSYM(x217) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
1971LSYM(x218) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
1972LSYM(x219) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
1973LSYM(x220) t0__3a0 ! t0__9t0 ! b_e_4t0 ! t0__2t0_a0
1974LSYM(x221) t0__3a0 ! t0__9t0 ! b_e_4t0a0 ! t0__2t0_a0
1975LSYM(x222) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__3t0
1976LSYM(x223) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
1977LSYM(x224) t0__9a0 ! t0__3t0 ! b_e_8t0 ! t0__t0_a0
1978LSYM(x225) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
1979LSYM(x226) t0__3a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__32t0
1980LSYM(x227) t0__9a0 ! t0__5t0 ! b_e_t02a0 ! t0__5t0
1981LSYM(x228) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
1982LSYM(x229) t0__9a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__3t0
1983LSYM(x230) t0__9a0 ! t0__5t0 ! b_e_5t0 ! t0__t0_a0
1984LSYM(x231) t0__9a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
1985LSYM(x232) t0__3a0 ! t0__2t0_a0 ! b_e_8t0 ! t0__4t0_a0
1986LSYM(x233) t0__3a0 ! t0__2t0_a0 ! b_e_8t0a0 ! t0__4t0_a0
1987LSYM(x234) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__9t0
1988LSYM(x235) t0__3a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__9t0
1989LSYM(x236) t0__9a0 ! t0__2t0_a0 ! b_e_4t08a0 ! t0__3t0
1990LSYM(x237) t0__16a0 ! t0__5t0 ! b_e_3t0 ! t0__t0ma0
1991LSYM(x238) t0__3a0 ! t0__4t0_a0 ! b_e_2t04a0 ! t0__9t0
1992LSYM(x239) t0__16a0 ! t0__5t0 ! b_e_t0ma0 ! t0__3t0
1993LSYM(x240) t0__9a0 ! t0__t0_a0 ! b_e_8t0 ! t0__3t0
1994LSYM(x241) t0__9a0 ! t0__t0_a0 ! b_e_8t0a0 ! t0__3t0
1995LSYM(x242) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__8t0_a0
1996LSYM(x243) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__3t0
1997LSYM(x244) t0__5a0 ! t0__3t0 ! b_e_4t0 ! t0__4t0_a0
1998LSYM(x245) t0__8a0 ! t0__3t0 ! b_e_5t0 ! t0__2t0_a0
1999LSYM(x246) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__3t0
2000LSYM(x247) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__3t0
2001LSYM(x248) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_8t0
2002LSYM(x249) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__8t0_a0
2003LSYM(x250) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__5t0
2004LSYM(x251) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__5t0
2005LSYM(x252) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
2006LSYM(x253) t0__64a0 ! t0__t0ma0 ! b_e_t0 ! t0__4t0_a0
2007LSYM(x254) t0__128a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
2008LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
2009/*1040 insts before this. */
2010LSYM(ret_t0) MILLIRET
2011LSYM(e_t0) r__r_t0
2012LSYM(e_shift) a1_ne_0_b_l2
2013 a0__256a0 /* a0 <<= 8 *********** */
2014 MILLIRETN
2015LSYM(e_t0ma0) a1_ne_0_b_l0
2016 t0__t0ma0
2017 MILLIRET
2018 r__r_t0
2019LSYM(e_t0a0) a1_ne_0_b_l0
2020 t0__t0_a0
2021 MILLIRET
2022 r__r_t0
2023LSYM(e_t02a0) a1_ne_0_b_l0
2024 t0__t0_2a0
2025 MILLIRET
2026 r__r_t0
2027LSYM(e_t04a0) a1_ne_0_b_l0
2028 t0__t0_4a0
2029 MILLIRET
2030 r__r_t0
2031LSYM(e_2t0) a1_ne_0_b_l1
2032 r__r_2t0
2033 MILLIRETN
2034LSYM(e_2t0a0) a1_ne_0_b_l0
2035 t0__2t0_a0
2036 MILLIRET
2037 r__r_t0
2038LSYM(e2t04a0) t0__t0_2a0
2039 a1_ne_0_b_l1
2040 r__r_2t0
2041 MILLIRETN
2042LSYM(e_3t0) a1_ne_0_b_l0
2043 t0__3t0
2044 MILLIRET
2045 r__r_t0
2046LSYM(e_4t0) a1_ne_0_b_l1
2047 r__r_4t0
2048 MILLIRETN
2049LSYM(e_4t0a0) a1_ne_0_b_l0
2050 t0__4t0_a0
2051 MILLIRET
2052 r__r_t0
2053LSYM(e4t08a0) t0__t0_2a0
2054 a1_ne_0_b_l1
2055 r__r_4t0
2056 MILLIRETN
2057LSYM(e_5t0) a1_ne_0_b_l0
2058 t0__5t0
2059 MILLIRET
2060 r__r_t0
2061LSYM(e_8t0) a1_ne_0_b_l1
2062 r__r_8t0
2063 MILLIRETN
2064LSYM(e_8t0a0) a1_ne_0_b_l0
2065 t0__8t0_a0
2066 MILLIRET
2067 r__r_t0
2068
2069 .procend
2070 .end
2071#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 20:35:08 -0500