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-rw-r--r--arch/parisc/include/asm/atomic.h1
-rw-r--r--arch/parisc/include/asm/barrier.h35
-rw-r--r--arch/parisc/include/asm/delay.h2
-rw-r--r--arch/parisc/include/asm/dma.h1
-rw-r--r--arch/parisc/include/asm/exec.h6
-rw-r--r--arch/parisc/include/asm/ldcw.h48
-rw-r--r--arch/parisc/include/asm/processor.h2
-rw-r--r--arch/parisc/include/asm/psw.h41
-rw-r--r--arch/parisc/include/asm/special_insns.h40
-rw-r--r--arch/parisc/include/asm/spinlock.h1
-rw-r--r--arch/parisc/include/asm/switch_to.h12
-rw-r--r--arch/parisc/include/asm/system.h171
-rw-r--r--arch/parisc/include/asm/thread_info.h1
-rw-r--r--arch/parisc/include/asm/timex.h1
-rw-r--r--arch/parisc/include/asm/uaccess.h1
15 files changed, 191 insertions, 172 deletions
diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h
index 4054b31e0fa9..3ae56073cc3d 100644
--- a/arch/parisc/include/asm/atomic.h
+++ b/arch/parisc/include/asm/atomic.h
@@ -6,7 +6,6 @@
6#define _ASM_PARISC_ATOMIC_H_ 6#define _ASM_PARISC_ATOMIC_H_
7 7
8#include <linux/types.h> 8#include <linux/types.h>
9#include <asm/system.h>
10 9
11/* 10/*
12 * Atomic operations that C can't guarantee us. Useful for 11 * Atomic operations that C can't guarantee us. Useful for
diff --git a/arch/parisc/include/asm/barrier.h b/arch/parisc/include/asm/barrier.h
new file mode 100644
index 000000000000..e77d834aa803
--- /dev/null
+++ b/arch/parisc/include/asm/barrier.h
@@ -0,0 +1,35 @@
1#ifndef __PARISC_BARRIER_H
2#define __PARISC_BARRIER_H
3
4/*
5** This is simply the barrier() macro from linux/kernel.h but when serial.c
6** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
7** hasn't yet been included yet so it fails, thus repeating the macro here.
8**
9** PA-RISC architecture allows for weakly ordered memory accesses although
10** none of the processors use it. There is a strong ordered bit that is
11** set in the O-bit of the page directory entry. Operating systems that
12** can not tolerate out of order accesses should set this bit when mapping
13** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
14** of the processor implemented the PSW O-bit). The PCX-W ERS states that
15** the TLB O-bit is not implemented so the page directory does not need to
16** have the O-bit set when mapping pages (section 3.1). This section also
17** states that the PSW Y, Z, G, and O bits are not implemented.
18** So it looks like nothing needs to be done for parisc-linux (yet).
19** (thanks to chada for the above comment -ggg)
20**
21** The __asm__ op below simple prevents gcc/ld from reordering
22** instructions across the mb() "call".
23*/
24#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
25#define rmb() mb()
26#define wmb() mb()
27#define smp_mb() mb()
28#define smp_rmb() mb()
29#define smp_wmb() mb()
30#define smp_read_barrier_depends() do { } while(0)
31#define read_barrier_depends() do { } while(0)
32
33#define set_mb(var, value) do { var = value; mb(); } while (0)
34
35#endif /* __PARISC_BARRIER_H */
diff --git a/arch/parisc/include/asm/delay.h b/arch/parisc/include/asm/delay.h
index 7a75e984674b..912ee7e6a579 100644
--- a/arch/parisc/include/asm/delay.h
+++ b/arch/parisc/include/asm/delay.h
@@ -1,7 +1,7 @@
1#ifndef _PARISC_DELAY_H 1#ifndef _PARISC_DELAY_H
2#define _PARISC_DELAY_H 2#define _PARISC_DELAY_H
3 3
4#include <asm/system.h> /* for mfctl() */ 4#include <asm/special_insns.h> /* for mfctl() */
5#include <asm/processor.h> /* for boot_cpu_data */ 5#include <asm/processor.h> /* for boot_cpu_data */
6 6
7 7
diff --git a/arch/parisc/include/asm/dma.h b/arch/parisc/include/asm/dma.h
index f7a18f968703..fd48ae2de950 100644
--- a/arch/parisc/include/asm/dma.h
+++ b/arch/parisc/include/asm/dma.h
@@ -9,7 +9,6 @@
9#define _ASM_DMA_H 9#define _ASM_DMA_H
10 10
11#include <asm/io.h> /* need byte IO */ 11#include <asm/io.h> /* need byte IO */
12#include <asm/system.h>
13 12
14#define dma_outb outb 13#define dma_outb outb
15#define dma_inb inb 14#define dma_inb inb
diff --git a/arch/parisc/include/asm/exec.h b/arch/parisc/include/asm/exec.h
new file mode 100644
index 000000000000..6bb5af75b17a
--- /dev/null
+++ b/arch/parisc/include/asm/exec.h
@@ -0,0 +1,6 @@
1#ifndef __PARISC_EXEC_H
2#define __PARISC_EXEC_H
3
4#define arch_align_stack(x) (x)
5
6#endif /* __PARISC_EXEC_H */
diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h
new file mode 100644
index 000000000000..d2d11b7055ba
--- /dev/null
+++ b/arch/parisc/include/asm/ldcw.h
@@ -0,0 +1,48 @@
1#ifndef __PARISC_LDCW_H
2#define __PARISC_LDCW_H
3
4#ifndef CONFIG_PA20
5/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
6 and GCC only guarantees 8-byte alignment for stack locals, we can't
7 be assured of 16-byte alignment for atomic lock data even if we
8 specify "__attribute ((aligned(16)))" in the type declaration. So,
9 we use a struct containing an array of four ints for the atomic lock
10 type and dynamically select the 16-byte aligned int from the array
11 for the semaphore. */
12
13#define __PA_LDCW_ALIGNMENT 16
14#define __ldcw_align(a) ({ \
15 unsigned long __ret = (unsigned long) &(a)->lock[0]; \
16 __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
17 & ~(__PA_LDCW_ALIGNMENT - 1); \
18 (volatile unsigned int *) __ret; \
19})
20#define __LDCW "ldcw"
21
22#else /*CONFIG_PA20*/
23/* From: "Jim Hull" <jim.hull of hp.com>
24 I've attached a summary of the change, but basically, for PA 2.0, as
25 long as the ",CO" (coherent operation) completer is specified, then the
26 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
27 they only require "natural" alignment (4-byte for ldcw, 8-byte for
28 ldcd). */
29
30#define __PA_LDCW_ALIGNMENT 4
31#define __ldcw_align(a) (&(a)->slock)
32#define __LDCW "ldcw,co"
33
34#endif /*!CONFIG_PA20*/
35
36/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
37#define __ldcw(a) ({ \
38 unsigned __ret; \
39 __asm__ __volatile__(__LDCW " 0(%2),%0" \
40 : "=r" (__ret), "+m" (*(a)) : "r" (a)); \
41 __ret; \
42})
43
44#ifdef CONFIG_SMP
45# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
46#endif
47
48#endif /* __PARISC_LDCW_H */
diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index 7213ec9e594c..acdf4cad6125 100644
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -16,7 +16,6 @@
16#include <asm/pdc.h> 16#include <asm/pdc.h>
17#include <asm/ptrace.h> 17#include <asm/ptrace.h>
18#include <asm/types.h> 18#include <asm/types.h>
19#include <asm/system.h>
20#include <asm/percpu.h> 19#include <asm/percpu.h>
21 20
22#endif /* __ASSEMBLY__ */ 21#endif /* __ASSEMBLY__ */
@@ -169,6 +168,7 @@ struct thread_struct {
169 * Return saved PC of a blocked thread. This is used by ps mostly. 168 * Return saved PC of a blocked thread. This is used by ps mostly.
170 */ 169 */
171 170
171struct task_struct;
172unsigned long thread_saved_pc(struct task_struct *t); 172unsigned long thread_saved_pc(struct task_struct *t);
173void show_trace(struct task_struct *task, unsigned long *stack); 173void show_trace(struct task_struct *task, unsigned long *stack);
174 174
diff --git a/arch/parisc/include/asm/psw.h b/arch/parisc/include/asm/psw.h
index 5a3e23c9ce63..ad69a35e9c0f 100644
--- a/arch/parisc/include/asm/psw.h
+++ b/arch/parisc/include/asm/psw.h
@@ -59,4 +59,45 @@
59#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB) 59#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
60#define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I) 60#define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
61 61
62#ifndef __ASSEMBLY__
63
64/* The program status word as bitfields. */
65struct pa_psw {
66 unsigned int y:1;
67 unsigned int z:1;
68 unsigned int rv:2;
69 unsigned int w:1;
70 unsigned int e:1;
71 unsigned int s:1;
72 unsigned int t:1;
73
74 unsigned int h:1;
75 unsigned int l:1;
76 unsigned int n:1;
77 unsigned int x:1;
78 unsigned int b:1;
79 unsigned int c:1;
80 unsigned int v:1;
81 unsigned int m:1;
82
83 unsigned int cb:8;
84
85 unsigned int o:1;
86 unsigned int g:1;
87 unsigned int f:1;
88 unsigned int r:1;
89 unsigned int q:1;
90 unsigned int p:1;
91 unsigned int d:1;
92 unsigned int i:1;
93};
94
95#ifdef CONFIG_64BIT
96#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
97#else
98#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
99#endif
100
101#endif /* !__ASSEMBLY__ */
102
62#endif 103#endif
diff --git a/arch/parisc/include/asm/special_insns.h b/arch/parisc/include/asm/special_insns.h
new file mode 100644
index 000000000000..d306b75bc77f
--- /dev/null
+++ b/arch/parisc/include/asm/special_insns.h
@@ -0,0 +1,40 @@
1#ifndef __PARISC_SPECIAL_INSNS_H
2#define __PARISC_SPECIAL_INSNS_H
3
4#define mfctl(reg) ({ \
5 unsigned long cr; \
6 __asm__ __volatile__( \
7 "mfctl " #reg ",%0" : \
8 "=r" (cr) \
9 ); \
10 cr; \
11})
12
13#define mtctl(gr, cr) \
14 __asm__ __volatile__("mtctl %0,%1" \
15 : /* no outputs */ \
16 : "r" (gr), "i" (cr) : "memory")
17
18/* these are here to de-mystefy the calling code, and to provide hooks */
19/* which I needed for debugging EIEM problems -PB */
20#define get_eiem() mfctl(15)
21static inline void set_eiem(unsigned long val)
22{
23 mtctl(val, 15);
24}
25
26#define mfsp(reg) ({ \
27 unsigned long cr; \
28 __asm__ __volatile__( \
29 "mfsp " #reg ",%0" : \
30 "=r" (cr) \
31 ); \
32 cr; \
33})
34
35#define mtsp(gr, cr) \
36 __asm__ __volatile__("mtsp %0,%1" \
37 : /* no outputs */ \
38 : "r" (gr), "i" (cr) : "memory")
39
40#endif /* __PARISC_SPECIAL_INSNS_H */
diff --git a/arch/parisc/include/asm/spinlock.h b/arch/parisc/include/asm/spinlock.h
index 74036f436a3b..804aa28ab1d6 100644
--- a/arch/parisc/include/asm/spinlock.h
+++ b/arch/parisc/include/asm/spinlock.h
@@ -1,7 +1,6 @@
1#ifndef __ASM_SPINLOCK_H 1#ifndef __ASM_SPINLOCK_H
2#define __ASM_SPINLOCK_H 2#define __ASM_SPINLOCK_H
3 3
4#include <asm/system.h>
5#include <asm/processor.h> 4#include <asm/processor.h>
6#include <asm/spinlock_types.h> 5#include <asm/spinlock_types.h>
7 6
diff --git a/arch/parisc/include/asm/switch_to.h b/arch/parisc/include/asm/switch_to.h
new file mode 100644
index 000000000000..8ed8fea1e784
--- /dev/null
+++ b/arch/parisc/include/asm/switch_to.h
@@ -0,0 +1,12 @@
1#ifndef __PARISC_SWITCH_TO_H
2#define __PARISC_SWITCH_TO_H
3
4struct task_struct;
5
6extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
7
8#define switch_to(prev, next, last) do { \
9 (last) = _switch_to(prev, next); \
10} while(0)
11
12#endif /* __PARISC_SWITCH_TO_H */
diff --git a/arch/parisc/include/asm/system.h b/arch/parisc/include/asm/system.h
index b19e63a8e848..fc2c1261ac1f 100644
--- a/arch/parisc/include/asm/system.h
+++ b/arch/parisc/include/asm/system.h
@@ -1,165 +1,6 @@
1#ifndef __PARISC_SYSTEM_H 1/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2#define __PARISC_SYSTEM_H 2#include <asm/barrier.h>
3 3#include <asm/exec.h>
4#include <linux/irqflags.h> 4#include <asm/ldcw.h>
5 5#include <asm/special_insns.h>
6/* The program status word as bitfields. */ 6#include <asm/switch_to.h>
7struct pa_psw {
8 unsigned int y:1;
9 unsigned int z:1;
10 unsigned int rv:2;
11 unsigned int w:1;
12 unsigned int e:1;
13 unsigned int s:1;
14 unsigned int t:1;
15
16 unsigned int h:1;
17 unsigned int l:1;
18 unsigned int n:1;
19 unsigned int x:1;
20 unsigned int b:1;
21 unsigned int c:1;
22 unsigned int v:1;
23 unsigned int m:1;
24
25 unsigned int cb:8;
26
27 unsigned int o:1;
28 unsigned int g:1;
29 unsigned int f:1;
30 unsigned int r:1;
31 unsigned int q:1;
32 unsigned int p:1;
33 unsigned int d:1;
34 unsigned int i:1;
35};
36
37#ifdef CONFIG_64BIT
38#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
39#else
40#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
41#endif
42
43struct task_struct;
44
45extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
46
47#define switch_to(prev, next, last) do { \
48 (last) = _switch_to(prev, next); \
49} while(0)
50
51#define mfctl(reg) ({ \
52 unsigned long cr; \
53 __asm__ __volatile__( \
54 "mfctl " #reg ",%0" : \
55 "=r" (cr) \
56 ); \
57 cr; \
58})
59
60#define mtctl(gr, cr) \
61 __asm__ __volatile__("mtctl %0,%1" \
62 : /* no outputs */ \
63 : "r" (gr), "i" (cr) : "memory")
64
65/* these are here to de-mystefy the calling code, and to provide hooks */
66/* which I needed for debugging EIEM problems -PB */
67#define get_eiem() mfctl(15)
68static inline void set_eiem(unsigned long val)
69{
70 mtctl(val, 15);
71}
72
73#define mfsp(reg) ({ \
74 unsigned long cr; \
75 __asm__ __volatile__( \
76 "mfsp " #reg ",%0" : \
77 "=r" (cr) \
78 ); \
79 cr; \
80})
81
82#define mtsp(gr, cr) \
83 __asm__ __volatile__("mtsp %0,%1" \
84 : /* no outputs */ \
85 : "r" (gr), "i" (cr) : "memory")
86
87
88/*
89** This is simply the barrier() macro from linux/kernel.h but when serial.c
90** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
91** hasn't yet been included yet so it fails, thus repeating the macro here.
92**
93** PA-RISC architecture allows for weakly ordered memory accesses although
94** none of the processors use it. There is a strong ordered bit that is
95** set in the O-bit of the page directory entry. Operating systems that
96** can not tolerate out of order accesses should set this bit when mapping
97** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
98** of the processor implemented the PSW O-bit). The PCX-W ERS states that
99** the TLB O-bit is not implemented so the page directory does not need to
100** have the O-bit set when mapping pages (section 3.1). This section also
101** states that the PSW Y, Z, G, and O bits are not implemented.
102** So it looks like nothing needs to be done for parisc-linux (yet).
103** (thanks to chada for the above comment -ggg)
104**
105** The __asm__ op below simple prevents gcc/ld from reordering
106** instructions across the mb() "call".
107*/
108#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
109#define rmb() mb()
110#define wmb() mb()
111#define smp_mb() mb()
112#define smp_rmb() mb()
113#define smp_wmb() mb()
114#define smp_read_barrier_depends() do { } while(0)
115#define read_barrier_depends() do { } while(0)
116
117#define set_mb(var, value) do { var = value; mb(); } while (0)
118
119#ifndef CONFIG_PA20
120/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
121 and GCC only guarantees 8-byte alignment for stack locals, we can't
122 be assured of 16-byte alignment for atomic lock data even if we
123 specify "__attribute ((aligned(16)))" in the type declaration. So,
124 we use a struct containing an array of four ints for the atomic lock
125 type and dynamically select the 16-byte aligned int from the array
126 for the semaphore. */
127
128#define __PA_LDCW_ALIGNMENT 16
129#define __ldcw_align(a) ({ \
130 unsigned long __ret = (unsigned long) &(a)->lock[0]; \
131 __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
132 & ~(__PA_LDCW_ALIGNMENT - 1); \
133 (volatile unsigned int *) __ret; \
134})
135#define __LDCW "ldcw"
136
137#else /*CONFIG_PA20*/
138/* From: "Jim Hull" <jim.hull of hp.com>
139 I've attached a summary of the change, but basically, for PA 2.0, as
140 long as the ",CO" (coherent operation) completer is specified, then the
141 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
142 they only require "natural" alignment (4-byte for ldcw, 8-byte for
143 ldcd). */
144
145#define __PA_LDCW_ALIGNMENT 4
146#define __ldcw_align(a) (&(a)->slock)
147#define __LDCW "ldcw,co"
148
149#endif /*!CONFIG_PA20*/
150
151/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
152#define __ldcw(a) ({ \
153 unsigned __ret; \
154 __asm__ __volatile__(__LDCW " 0(%2),%0" \
155 : "=r" (__ret), "+m" (*(a)) : "r" (a)); \
156 __ret; \
157})
158
159#ifdef CONFIG_SMP
160# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
161#endif
162
163#define arch_align_stack(x) (x)
164
165#endif
diff --git a/arch/parisc/include/asm/thread_info.h b/arch/parisc/include/asm/thread_info.h
index 6d9c7c7973d0..83ae7dd4d99e 100644
--- a/arch/parisc/include/asm/thread_info.h
+++ b/arch/parisc/include/asm/thread_info.h
@@ -5,6 +5,7 @@
5 5
6#ifndef __ASSEMBLY__ 6#ifndef __ASSEMBLY__
7#include <asm/processor.h> 7#include <asm/processor.h>
8#include <asm/special_insns.h>
8 9
9struct thread_info { 10struct thread_info {
10 struct task_struct *task; /* main task structure */ 11 struct task_struct *task; /* main task structure */
diff --git a/arch/parisc/include/asm/timex.h b/arch/parisc/include/asm/timex.h
index 3b68d77273d9..2bd51f6d832b 100644
--- a/arch/parisc/include/asm/timex.h
+++ b/arch/parisc/include/asm/timex.h
@@ -6,7 +6,6 @@
6#ifndef _ASMPARISC_TIMEX_H 6#ifndef _ASMPARISC_TIMEX_H
7#define _ASMPARISC_TIMEX_H 7#define _ASMPARISC_TIMEX_H
8 8
9#include <asm/system.h>
10 9
11#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ 10#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
12 11
diff --git a/arch/parisc/include/asm/uaccess.h b/arch/parisc/include/asm/uaccess.h
index ff4cf9dab8d2..9ac066086f03 100644
--- a/arch/parisc/include/asm/uaccess.h
+++ b/arch/parisc/include/asm/uaccess.h
@@ -5,7 +5,6 @@
5 * User space memory access functions 5 * User space memory access functions
6 */ 6 */
7#include <asm/page.h> 7#include <asm/page.h>
8#include <asm/system.h>
9#include <asm/cache.h> 8#include <asm/cache.h>
10#include <asm/errno.h> 9#include <asm/errno.h>
11#include <asm-generic/uaccess-unaligned.h> 10#include <asm-generic/uaccess-unaligned.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 18:34:17 -0400