diff options
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index e84e602eafa7..c3eeb90b480a 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | |||
| @@ -53,13 +53,18 @@ | |||
| 53 | CKCTL_6338_SAR_EN | \ | 53 | CKCTL_6338_SAR_EN | \ |
| 54 | CKCTL_6338_SPI_EN) | 54 | CKCTL_6338_SPI_EN) |
| 55 | 55 | ||
| 56 | #define CKCTL_6345_CPU_EN (1 << 0) | 56 | /* BCM6345 clock bits are shifted by 16 on the left, because of the test |
| 57 | #define CKCTL_6345_BUS_EN (1 << 1) | 57 | * control register which is 16-bits wide. That way we do not have any |
| 58 | #define CKCTL_6345_EBI_EN (1 << 2) | 58 | * specific BCM6345 code for handling clocks, and writing 0 to the test |
| 59 | #define CKCTL_6345_UART_EN (1 << 3) | 59 | * control register is fine. |
| 60 | #define CKCTL_6345_ADSLPHY_EN (1 << 4) | 60 | */ |
| 61 | #define CKCTL_6345_ENET_EN (1 << 7) | 61 | #define CKCTL_6345_CPU_EN (1 << 16) |
| 62 | #define CKCTL_6345_USBH_EN (1 << 8) | 62 | #define CKCTL_6345_BUS_EN (1 << 17) |
| 63 | #define CKCTL_6345_EBI_EN (1 << 18) | ||
| 64 | #define CKCTL_6345_UART_EN (1 << 19) | ||
| 65 | #define CKCTL_6345_ADSLPHY_EN (1 << 20) | ||
| 66 | #define CKCTL_6345_ENET_EN (1 << 23) | ||
| 67 | #define CKCTL_6345_USBH_EN (1 << 24) | ||
| 63 | 68 | ||
| 64 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ | 69 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ |
| 65 | CKCTL_6345_USBH_EN | \ | 70 | CKCTL_6345_USBH_EN | \ |