diff options
| author | Florian Fainelli <florian@openwrt.org> | 2012-11-12 03:48:45 -0500 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-11-20 02:30:50 -0500 |
| commit | e59b008e14c63572d4c643592e84bbd1b4088f39 (patch) | |
| tree | b69661b59829de3b4e69ad43858000cab5ef9fab /arch/mips | |
| parent | 0224cde212df4abf251f89c3724a800b1949a774 (diff) | |
MIPS: BCM63XX: fix BCM6345 clocks bits
BCM6345 has an intermediate 16-bits wide test control register between the
peripheral identifier register, and its clock control register is only 16-bits
wide contrary to other platforms where it is 32-bits wide. By shifting all
clocks bits by 16-bits to the left we ensure they get written to the proper
clock control register, without adding specific BCM6345 handling in the clock
code.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4555/
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index e84e602eafa7..c3eeb90b480a 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | |||
| @@ -53,13 +53,18 @@ | |||
| 53 | CKCTL_6338_SAR_EN | \ | 53 | CKCTL_6338_SAR_EN | \ |
| 54 | CKCTL_6338_SPI_EN) | 54 | CKCTL_6338_SPI_EN) |
| 55 | 55 | ||
| 56 | #define CKCTL_6345_CPU_EN (1 << 0) | 56 | /* BCM6345 clock bits are shifted by 16 on the left, because of the test |
| 57 | #define CKCTL_6345_BUS_EN (1 << 1) | 57 | * control register which is 16-bits wide. That way we do not have any |
| 58 | #define CKCTL_6345_EBI_EN (1 << 2) | 58 | * specific BCM6345 code for handling clocks, and writing 0 to the test |
| 59 | #define CKCTL_6345_UART_EN (1 << 3) | 59 | * control register is fine. |
| 60 | #define CKCTL_6345_ADSLPHY_EN (1 << 4) | 60 | */ |
| 61 | #define CKCTL_6345_ENET_EN (1 << 7) | 61 | #define CKCTL_6345_CPU_EN (1 << 16) |
| 62 | #define CKCTL_6345_USBH_EN (1 << 8) | 62 | #define CKCTL_6345_BUS_EN (1 << 17) |
| 63 | #define CKCTL_6345_EBI_EN (1 << 18) | ||
| 64 | #define CKCTL_6345_UART_EN (1 << 19) | ||
| 65 | #define CKCTL_6345_ADSLPHY_EN (1 << 20) | ||
| 66 | #define CKCTL_6345_ENET_EN (1 << 23) | ||
| 67 | #define CKCTL_6345_USBH_EN (1 << 24) | ||
| 63 | 68 | ||
| 64 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ | 69 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ |
| 65 | CKCTL_6345_USBH_EN | \ | 70 | CKCTL_6345_USBH_EN | \ |