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-rw-r--r--arch/mips/Kconfig5
-rw-r--r--arch/mips/configs/ip22_defconfig1
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/ip28_defconfig2
-rw-r--r--arch/mips/include/asm/bitops.h114
-rw-r--r--arch/mips/include/asm/break.h1
-rw-r--r--arch/mips/include/asm/byteorder.h40
-rw-r--r--arch/mips/include/asm/cpu-features.h2
-rw-r--r--arch/mips/include/asm/ds1286.h15
-rw-r--r--arch/mips/include/asm/fpu_emulator.h17
-rw-r--r--arch/mips/include/asm/m48t35.h27
-rw-r--r--arch/mips/kernel/cpu-probe.c247
-rw-r--r--arch/mips/kernel/smp.c6
-rw-r--r--arch/mips/kernel/traps.c29
-rw-r--r--arch/mips/kernel/unaligned.c12
-rw-r--r--arch/mips/math-emu/cp1emu.c4
-rw-r--r--arch/mips/math-emu/dsemul.c7
-rw-r--r--arch/mips/math-emu/dsemul.h17
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c25
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c14
20 files changed, 281 insertions, 305 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 653574bc19cf..f4af967a6b30 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -327,7 +327,6 @@ config SGI_IP22
327 select IP22_CPU_SCACHE 327 select IP22_CPU_SCACHE
328 select IRQ_CPU 328 select IRQ_CPU
329 select GENERIC_ISA_DMA_SUPPORT_BROKEN 329 select GENERIC_ISA_DMA_SUPPORT_BROKEN
330 select SGI_HAS_DS1286
331 select SGI_HAS_I8042 330 select SGI_HAS_I8042
332 select SGI_HAS_INDYDOG 331 select SGI_HAS_INDYDOG
333 select SGI_HAS_HAL2 332 select SGI_HAS_HAL2
@@ -382,7 +381,6 @@ config SGI_IP28
382 select HW_HAS_EISA 381 select HW_HAS_EISA
383 select I8253 382 select I8253
384 select I8259 383 select I8259
385 select SGI_HAS_DS1286
386 select SGI_HAS_I8042 384 select SGI_HAS_I8042
387 select SGI_HAS_INDYDOG 385 select SGI_HAS_INDYDOG
388 select SGI_HAS_HAL2 386 select SGI_HAS_HAL2
@@ -893,9 +891,6 @@ config EMMA2RH
893config SERIAL_RM9000 891config SERIAL_RM9000
894 bool 892 bool
895 893
896config SGI_HAS_DS1286
897 bool
898
899config SGI_HAS_INDYDOG 894config SGI_HAS_INDYDOG
900 bool 895 bool
901 896
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index cc8e6bf2b245..f719bf5e01aa 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -771,7 +771,6 @@ CONFIG_WATCHDOG=y
771CONFIG_INDYDOG=m 771CONFIG_INDYDOG=m
772# CONFIG_HW_RANDOM is not set 772# CONFIG_HW_RANDOM is not set
773# CONFIG_RTC is not set 773# CONFIG_RTC is not set
774CONFIG_SGI_DS1286=m
775# CONFIG_R3964 is not set 774# CONFIG_R3964 is not set
776CONFIG_RAW_DRIVER=m 775CONFIG_RAW_DRIVER=m
777CONFIG_MAX_RAW_DEVS=256 776CONFIG_MAX_RAW_DEVS=256
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 831d3e5a1ea6..34ea319be94c 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -701,7 +701,6 @@ CONFIG_LEGACY_PTY_COUNT=256
701# CONFIG_WATCHDOG is not set 701# CONFIG_WATCHDOG is not set
702CONFIG_HW_RANDOM=m 702CONFIG_HW_RANDOM=m
703# CONFIG_RTC is not set 703# CONFIG_RTC is not set
704CONFIG_SGI_IP27_RTC=y
705# CONFIG_R3964 is not set 704# CONFIG_R3964 is not set
706# CONFIG_APPLICOM is not set 705# CONFIG_APPLICOM is not set
707# CONFIG_DRM is not set 706# CONFIG_DRM is not set
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 822b01f643e3..70a744e9a8c5 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -70,7 +70,6 @@ CONFIG_CPU_BIG_ENDIAN=y
70CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 70CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
71CONFIG_IRQ_CPU=y 71CONFIG_IRQ_CPU=y
72CONFIG_SWAP_IO_SPACE=y 72CONFIG_SWAP_IO_SPACE=y
73CONFIG_SGI_HAS_DS1286=y
74CONFIG_SGI_HAS_INDYDOG=y 73CONFIG_SGI_HAS_INDYDOG=y
75CONFIG_SGI_HAS_SEEQ=y 74CONFIG_SGI_HAS_SEEQ=y
76CONFIG_SGI_HAS_WD93=y 75CONFIG_SGI_HAS_WD93=y
@@ -585,7 +584,6 @@ CONFIG_LEGACY_PTY_COUNT=256
585# CONFIG_IPMI_HANDLER is not set 584# CONFIG_IPMI_HANDLER is not set
586# CONFIG_HW_RANDOM is not set 585# CONFIG_HW_RANDOM is not set
587# CONFIG_RTC is not set 586# CONFIG_RTC is not set
588CONFIG_SGI_DS1286=y
589# CONFIG_DTLK is not set 587# CONFIG_DTLK is not set
590# CONFIG_R3964 is not set 588# CONFIG_R3964 is not set
591# CONFIG_RAW_DRIVER is not set 589# CONFIG_RAW_DRIVER is not set
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 49df8c4c9d25..bac4a960b24c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
558 __clear_bit(nr, addr); 558 __clear_bit(nr, addr);
559} 559}
560 560
561#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
562
563/* 561/*
564 * Return the bit position (0..63) of the most significant 1 bit in a word 562 * Return the bit position (0..63) of the most significant 1 bit in a word
565 * Returns -1 if no 1 bit exists 563 * Returns -1 if no 1 bit exists
566 */ 564 */
567static inline unsigned long __fls(unsigned long x) 565static inline unsigned long __fls(unsigned long word)
568{ 566{
569 int lz; 567 int num;
570 568
571 if (sizeof(x) == 4) { 569 if (BITS_PER_LONG == 32 &&
570 __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
572 __asm__( 571 __asm__(
573 " .set push \n" 572 " .set push \n"
574 " .set mips32 \n" 573 " .set mips32 \n"
575 " clz %0, %1 \n" 574 " clz %0, %1 \n"
576 " .set pop \n" 575 " .set pop \n"
577 : "=r" (lz) 576 : "=r" (num)
578 : "r" (x)); 577 : "r" (word));
579 578
580 return 31 - lz; 579 return 31 - num;
581 } 580 }
582 581
583 BUG_ON(sizeof(x) != 8); 582 if (BITS_PER_LONG == 64 &&
583 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
584 __asm__(
585 " .set push \n"
586 " .set mips64 \n"
587 " dclz %0, %1 \n"
588 " .set pop \n"
589 : "=r" (num)
590 : "r" (word));
584 591
585 __asm__( 592 return 63 - num;
586 " .set push \n" 593 }
587 " .set mips64 \n" 594
588 " dclz %0, %1 \n" 595 num = BITS_PER_LONG - 1;
589 " .set pop \n"
590 : "=r" (lz)
591 : "r" (x));
592 596
593 return 63 - lz; 597#if BITS_PER_LONG == 64
598 if (!(word & (~0ul << 32))) {
599 num -= 32;
600 word <<= 32;
601 }
602#endif
603 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
604 num -= 16;
605 word <<= 16;
606 }
607 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
608 num -= 8;
609 word <<= 8;
610 }
611 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
612 num -= 4;
613 word <<= 4;
614 }
615 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
616 num -= 2;
617 word <<= 2;
618 }
619 if (!(word & (~0ul << (BITS_PER_LONG-1))))
620 num -= 1;
621 return num;
594} 622}
595 623
596/* 624/*
@@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word)
612 * This is defined the same way as ffs. 640 * This is defined the same way as ffs.
613 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. 641 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
614 */ 642 */
615static inline int fls(int word) 643static inline int fls(int x)
616{ 644{
617 __asm__("clz %0, %1" : "=r" (word) : "r" (word)); 645 int r;
618 646
619 return 32 - word; 647 if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
620} 648 __asm__("clz %0, %1" : "=r" (x) : "r" (x));
621 649
622#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) 650 return 32 - x;
623static inline int fls64(__u64 word) 651 }
624{
625 __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
626 652
627 return 64 - word; 653 r = 32;
654 if (!x)
655 return 0;
656 if (!(x & 0xffff0000u)) {
657 x <<= 16;
658 r -= 16;
659 }
660 if (!(x & 0xff000000u)) {
661 x <<= 8;
662 r -= 8;
663 }
664 if (!(x & 0xf0000000u)) {
665 x <<= 4;
666 r -= 4;
667 }
668 if (!(x & 0xc0000000u)) {
669 x <<= 2;
670 r -= 2;
671 }
672 if (!(x & 0x80000000u)) {
673 x <<= 1;
674 r -= 1;
675 }
676 return r;
628} 677}
629#else 678
630#include <asm-generic/bitops/fls64.h> 679#include <asm-generic/bitops/fls64.h>
631#endif
632 680
633/* 681/*
634 * ffs - find first bit set. 682 * ffs - find first bit set.
@@ -646,16 +694,6 @@ static inline int ffs(int word)
646 return fls(word & -word); 694 return fls(word & -word);
647} 695}
648 696
649#else
650
651#include <asm-generic/bitops/__ffs.h>
652#include <asm-generic/bitops/__fls.h>
653#include <asm-generic/bitops/ffs.h>
654#include <asm-generic/bitops/fls.h>
655#include <asm-generic/bitops/fls64.h>
656
657#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
658
659#include <asm-generic/bitops/ffz.h> 697#include <asm-generic/bitops/ffz.h>
660#include <asm-generic/bitops/find.h> 698#include <asm-generic/bitops/find.h>
661 699
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 25b980c91e7e..44437ed765e8 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -29,6 +29,7 @@
29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ 29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
30#define BRK_BUG 512 /* Used by BUG() */ 30#define BRK_BUG 512 /* Used by BUG() */
31#define BRK_KDB 513 /* Used in KDB_ENTER() */ 31#define BRK_KDB 513 /* Used in KDB_ENTER() */
32#define BRK_MEMU 514 /* Used by FPU emulator */
32#define BRK_MULOVF 1023 /* Multiply overflow */ 33#define BRK_MULOVF 1023 /* Multiply overflow */
33 34
34#endif /* __ASM_BREAK_H */ 35#endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index fe7dc2d59b69..2988d29a0867 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -11,11 +11,19 @@
11#include <linux/compiler.h> 11#include <linux/compiler.h>
12#include <asm/types.h> 12#include <asm/types.h>
13 13
14#ifdef __GNUC__ 14#if defined(__MIPSEB__)
15# define __BIG_ENDIAN
16#elif defined(__MIPSEL__)
17# define __LITTLE_ENDIAN
18#else
19# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
20#endif
21
22#define __SWAB_64_THRU_32__
15 23
16#ifdef CONFIG_CPU_MIPSR2 24#ifdef CONFIG_CPU_MIPSR2
17 25
18static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) 26static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
19{ 27{
20 __asm__( 28 __asm__(
21 " wsbh %0, %1 \n" 29 " wsbh %0, %1 \n"
@@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
24 32
25 return x; 33 return x;
26} 34}
27#define __arch__swab16(x) ___arch__swab16(x) 35#define __arch_swab16 __arch_swab16
28 36
29static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) 37static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
30{ 38{
31 __asm__( 39 __asm__(
32 " wsbh %0, %1 \n" 40 " wsbh %0, %1 \n"
@@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
36 44
37 return x; 45 return x;
38} 46}
39#define __arch__swab32(x) ___arch__swab32(x) 47#define __arch_swab32 __arch_swab32
40 48
41#ifdef CONFIG_CPU_MIPS64_R2 49#ifdef CONFIG_CPU_MIPS64_R2
42 50static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
43static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
44{ 51{
45 __asm__( 52 __asm__(
46 " dsbh %0, %1 \n" 53 " dsbh %0, %1 \n"
@@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
51 58
52 return x; 59 return x;
53} 60}
54 61#define __arch_swab64 __arch_swab64
55#define __arch__swab64(x) ___arch__swab64(x)
56
57#endif /* CONFIG_CPU_MIPS64_R2 */ 62#endif /* CONFIG_CPU_MIPS64_R2 */
58 63
59#endif /* CONFIG_CPU_MIPSR2 */ 64#endif /* CONFIG_CPU_MIPSR2 */
60 65
61#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 66#include <linux/byteorder.h>
62# define __BYTEORDER_HAS_U64__
63# define __SWAB_64_THRU_32__
64#endif
65
66#endif /* __GNUC__ */
67
68#if defined(__MIPSEB__)
69# include <linux/byteorder/big_endian.h>
70#elif defined(__MIPSEL__)
71# include <linux/byteorder/little_endian.h>
72#else
73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
74#endif
75 67
76#endif /* _ASM_BYTEORDER_H */ 68#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5ea701fc3425..12d12dfe73c0 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -141,6 +141,8 @@
141#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 141#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
142#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 142#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
143#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 143#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
144#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
145 cpu_has_mips64r1 | cpu_has_mips64r2)
144 146
145#ifndef cpu_has_dsp 147#ifndef cpu_has_dsp
146#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 148#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h
deleted file mode 100644
index 6983b6ff0af3..000000000000
--- a/arch/mips/include/asm/ds1286.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Machine dependent access functions for RTC registers.
7 *
8 * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
9 */
10#ifndef _ASM_DS1286_H
11#define _ASM_DS1286_H
12
13#include <ds1286.h>
14
15#endif /* _ASM_DS1286_H */
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 2731c38bd7ae..e5189572956c 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -23,6 +23,9 @@
23#ifndef _ASM_FPU_EMULATOR_H 23#ifndef _ASM_FPU_EMULATOR_H
24#define _ASM_FPU_EMULATOR_H 24#define _ASM_FPU_EMULATOR_H
25 25
26#include <asm/break.h>
27#include <asm/inst.h>
28
26struct mips_fpu_emulator_stats { 29struct mips_fpu_emulator_stats {
27 unsigned int emulated; 30 unsigned int emulated;
28 unsigned int loads; 31 unsigned int loads;
@@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats {
34 37
35extern struct mips_fpu_emulator_stats fpuemustats; 38extern struct mips_fpu_emulator_stats fpuemustats;
36 39
40extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
41 unsigned long cpc);
42extern int do_dsemulret(struct pt_regs *xcp);
43
44/*
45 * Instruction inserted following the badinst to further tag the sequence
46 */
47#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */
48
49/*
50 * Break instruction with special math emu break code set
51 */
52#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16))
53
37#endif /* _ASM_FPU_EMULATOR_H */ 54#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h
deleted file mode 100644
index f44852e9a96d..000000000000
--- a/arch/mips/include/asm/m48t35.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
3 */
4#ifndef _ASM_M48T35_H
5#define _ASM_M48T35_H
6
7#include <linux/spinlock.h>
8
9extern spinlock_t rtc_lock;
10
11struct m48t35_rtc {
12 volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */
13 volatile u8 control;
14 volatile u8 sec;
15 volatile u8 min;
16 volatile u8 hour;
17 volatile u8 day;
18 volatile u8 date;
19 volatile u8 month;
20 volatile u8 year;
21};
22
23#define M48T35_RTC_SET 0x80
24#define M48T35_RTC_STOPPED 0x80
25#define M48T35_RTC_READ 0x40
26
27#endif /* _ASM_M48T35_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0cf15457ecac..c9207b5fd923 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -286,11 +286,12 @@ static inline int __cpu_has_fpu(void)
286#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 286#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
287 | MIPS_CPU_COUNTER) 287 | MIPS_CPU_COUNTER)
288 288
289static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 289static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
290{ 290{
291 switch (c->processor_id & 0xff00) { 291 switch (c->processor_id & 0xff00) {
292 case PRID_IMP_R2000: 292 case PRID_IMP_R2000:
293 c->cputype = CPU_R2000; 293 c->cputype = CPU_R2000;
294 __cpu_name[cpu] = "R2000";
294 c->isa_level = MIPS_CPU_ISA_I; 295 c->isa_level = MIPS_CPU_ISA_I;
295 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 296 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
296 MIPS_CPU_NOFPUEX; 297 MIPS_CPU_NOFPUEX;
@@ -299,13 +300,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
299 c->tlbsize = 64; 300 c->tlbsize = 64;
300 break; 301 break;
301 case PRID_IMP_R3000: 302 case PRID_IMP_R3000:
302 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 303 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
303 if (cpu_has_confreg()) 304 if (cpu_has_confreg()) {
304 c->cputype = CPU_R3081E; 305 c->cputype = CPU_R3081E;
305 else 306 __cpu_name[cpu] = "R3081";
307 } else {
306 c->cputype = CPU_R3000A; 308 c->cputype = CPU_R3000A;
307 else 309 __cpu_name[cpu] = "R3000A";
310 }
311 break;
312 } else {
308 c->cputype = CPU_R3000; 313 c->cputype = CPU_R3000;
314 __cpu_name[cpu] = "R3000";
315 }
309 c->isa_level = MIPS_CPU_ISA_I; 316 c->isa_level = MIPS_CPU_ISA_I;
310 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 317 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
311 MIPS_CPU_NOFPUEX; 318 MIPS_CPU_NOFPUEX;
@@ -315,15 +322,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
315 break; 322 break;
316 case PRID_IMP_R4000: 323 case PRID_IMP_R4000:
317 if (read_c0_config() & CONF_SC) { 324 if (read_c0_config() & CONF_SC) {
318 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 325 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
319 c->cputype = CPU_R4400PC; 326 c->cputype = CPU_R4400PC;
320 else 327 __cpu_name[cpu] = "R4400PC";
328 } else {
321 c->cputype = CPU_R4000PC; 329 c->cputype = CPU_R4000PC;
330 __cpu_name[cpu] = "R4000PC";
331 }
322 } else { 332 } else {
323 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 333 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
324 c->cputype = CPU_R4400SC; 334 c->cputype = CPU_R4400SC;
325 else 335 __cpu_name[cpu] = "R4400SC";
336 } else {
326 c->cputype = CPU_R4000SC; 337 c->cputype = CPU_R4000SC;
338 __cpu_name[cpu] = "R4000SC";
339 }
327 } 340 }
328 341
329 c->isa_level = MIPS_CPU_ISA_III; 342 c->isa_level = MIPS_CPU_ISA_III;
@@ -336,25 +349,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
336 switch (c->processor_id & 0xf0) { 349 switch (c->processor_id & 0xf0) {
337 case PRID_REV_VR4111: 350 case PRID_REV_VR4111:
338 c->cputype = CPU_VR4111; 351 c->cputype = CPU_VR4111;
352 __cpu_name[cpu] = "NEC VR4111";
339 break; 353 break;
340 case PRID_REV_VR4121: 354 case PRID_REV_VR4121:
341 c->cputype = CPU_VR4121; 355 c->cputype = CPU_VR4121;
356 __cpu_name[cpu] = "NEC VR4121";
342 break; 357 break;
343 case PRID_REV_VR4122: 358 case PRID_REV_VR4122:
344 if ((c->processor_id & 0xf) < 0x3) 359 if ((c->processor_id & 0xf) < 0x3) {
345 c->cputype = CPU_VR4122; 360 c->cputype = CPU_VR4122;
346 else 361 __cpu_name[cpu] = "NEC VR4122";
362 } else {
347 c->cputype = CPU_VR4181A; 363 c->cputype = CPU_VR4181A;
364 __cpu_name[cpu] = "NEC VR4181A";
365 }
348 break; 366 break;
349 case PRID_REV_VR4130: 367 case PRID_REV_VR4130:
350 if ((c->processor_id & 0xf) < 0x4) 368 if ((c->processor_id & 0xf) < 0x4) {
351 c->cputype = CPU_VR4131; 369 c->cputype = CPU_VR4131;
352 else 370 __cpu_name[cpu] = "NEC VR4131";
371 } else {
353 c->cputype = CPU_VR4133; 372 c->cputype = CPU_VR4133;
373 __cpu_name[cpu] = "NEC VR4133";
374 }
354 break; 375 break;
355 default: 376 default:
356 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 377 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
357 c->cputype = CPU_VR41XX; 378 c->cputype = CPU_VR41XX;
379 __cpu_name[cpu] = "NEC Vr41xx";
358 break; 380 break;
359 } 381 }
360 c->isa_level = MIPS_CPU_ISA_III; 382 c->isa_level = MIPS_CPU_ISA_III;
@@ -363,6 +385,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
363 break; 385 break;
364 case PRID_IMP_R4300: 386 case PRID_IMP_R4300:
365 c->cputype = CPU_R4300; 387 c->cputype = CPU_R4300;
388 __cpu_name[cpu] = "R4300";
366 c->isa_level = MIPS_CPU_ISA_III; 389 c->isa_level = MIPS_CPU_ISA_III;
367 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
368 MIPS_CPU_LLSC; 391 MIPS_CPU_LLSC;
@@ -370,6 +393,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
370 break; 393 break;
371 case PRID_IMP_R4600: 394 case PRID_IMP_R4600:
372 c->cputype = CPU_R4600; 395 c->cputype = CPU_R4600;
396 __cpu_name[cpu] = "R4600";
373 c->isa_level = MIPS_CPU_ISA_III; 397 c->isa_level = MIPS_CPU_ISA_III;
374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 398 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
375 MIPS_CPU_LLSC; 399 MIPS_CPU_LLSC;
@@ -384,6 +408,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
384 * it's c0_prid id number with the TX3900. 408 * it's c0_prid id number with the TX3900.
385 */ 409 */
386 c->cputype = CPU_R4650; 410 c->cputype = CPU_R4650;
411 __cpu_name[cpu] = "R4650";
387 c->isa_level = MIPS_CPU_ISA_III; 412 c->isa_level = MIPS_CPU_ISA_III;
388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 413 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
389 c->tlbsize = 48; 414 c->tlbsize = 48;
@@ -395,25 +420,26 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
395 420
396 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 421 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
397 c->cputype = CPU_TX3927; 422 c->cputype = CPU_TX3927;
423 __cpu_name[cpu] = "TX3927";
398 c->tlbsize = 64; 424 c->tlbsize = 64;
399 } else { 425 } else {
400 switch (c->processor_id & 0xff) { 426 switch (c->processor_id & 0xff) {
401 case PRID_REV_TX3912: 427 case PRID_REV_TX3912:
402 c->cputype = CPU_TX3912; 428 c->cputype = CPU_TX3912;
429 __cpu_name[cpu] = "TX3912";
403 c->tlbsize = 32; 430 c->tlbsize = 32;
404 break; 431 break;
405 case PRID_REV_TX3922: 432 case PRID_REV_TX3922:
406 c->cputype = CPU_TX3922; 433 c->cputype = CPU_TX3922;
434 __cpu_name[cpu] = "TX3922";
407 c->tlbsize = 64; 435 c->tlbsize = 64;
408 break; 436 break;
409 default:
410 c->cputype = CPU_UNKNOWN;
411 break;
412 } 437 }
413 } 438 }
414 break; 439 break;
415 case PRID_IMP_R4700: 440 case PRID_IMP_R4700:
416 c->cputype = CPU_R4700; 441 c->cputype = CPU_R4700;
442 __cpu_name[cpu] = "R4700";
417 c->isa_level = MIPS_CPU_ISA_III; 443 c->isa_level = MIPS_CPU_ISA_III;
418 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 444 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
419 MIPS_CPU_LLSC; 445 MIPS_CPU_LLSC;
@@ -421,6 +447,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
421 break; 447 break;
422 case PRID_IMP_TX49: 448 case PRID_IMP_TX49:
423 c->cputype = CPU_TX49XX; 449 c->cputype = CPU_TX49XX;
450 __cpu_name[cpu] = "R49XX";
424 c->isa_level = MIPS_CPU_ISA_III; 451 c->isa_level = MIPS_CPU_ISA_III;
425 c->options = R4K_OPTS | MIPS_CPU_LLSC; 452 c->options = R4K_OPTS | MIPS_CPU_LLSC;
426 if (!(c->processor_id & 0x08)) 453 if (!(c->processor_id & 0x08))
@@ -429,6 +456,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
429 break; 456 break;
430 case PRID_IMP_R5000: 457 case PRID_IMP_R5000:
431 c->cputype = CPU_R5000; 458 c->cputype = CPU_R5000;
459 __cpu_name[cpu] = "R5000";
432 c->isa_level = MIPS_CPU_ISA_IV; 460 c->isa_level = MIPS_CPU_ISA_IV;
433 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 461 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
434 MIPS_CPU_LLSC; 462 MIPS_CPU_LLSC;
@@ -436,6 +464,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
436 break; 464 break;
437 case PRID_IMP_R5432: 465 case PRID_IMP_R5432:
438 c->cputype = CPU_R5432; 466 c->cputype = CPU_R5432;
467 __cpu_name[cpu] = "R5432";
439 c->isa_level = MIPS_CPU_ISA_IV; 468 c->isa_level = MIPS_CPU_ISA_IV;
440 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 469 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
441 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 470 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -443,6 +472,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
443 break; 472 break;
444 case PRID_IMP_R5500: 473 case PRID_IMP_R5500:
445 c->cputype = CPU_R5500; 474 c->cputype = CPU_R5500;
475 __cpu_name[cpu] = "R5500";
446 c->isa_level = MIPS_CPU_ISA_IV; 476 c->isa_level = MIPS_CPU_ISA_IV;
447 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 477 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
448 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 478 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -450,6 +480,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
450 break; 480 break;
451 case PRID_IMP_NEVADA: 481 case PRID_IMP_NEVADA:
452 c->cputype = CPU_NEVADA; 482 c->cputype = CPU_NEVADA;
483 __cpu_name[cpu] = "Nevada";
453 c->isa_level = MIPS_CPU_ISA_IV; 484 c->isa_level = MIPS_CPU_ISA_IV;
454 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 485 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
455 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 486 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
@@ -457,6 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
457 break; 488 break;
458 case PRID_IMP_R6000: 489 case PRID_IMP_R6000:
459 c->cputype = CPU_R6000; 490 c->cputype = CPU_R6000;
491 __cpu_name[cpu] = "R6000";
460 c->isa_level = MIPS_CPU_ISA_II; 492 c->isa_level = MIPS_CPU_ISA_II;
461 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 493 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
462 MIPS_CPU_LLSC; 494 MIPS_CPU_LLSC;
@@ -464,6 +496,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
464 break; 496 break;
465 case PRID_IMP_R6000A: 497 case PRID_IMP_R6000A:
466 c->cputype = CPU_R6000A; 498 c->cputype = CPU_R6000A;
499 __cpu_name[cpu] = "R6000A";
467 c->isa_level = MIPS_CPU_ISA_II; 500 c->isa_level = MIPS_CPU_ISA_II;
468 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 501 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
469 MIPS_CPU_LLSC; 502 MIPS_CPU_LLSC;
@@ -471,6 +504,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
471 break; 504 break;
472 case PRID_IMP_RM7000: 505 case PRID_IMP_RM7000:
473 c->cputype = CPU_RM7000; 506 c->cputype = CPU_RM7000;
507 __cpu_name[cpu] = "RM7000";
474 c->isa_level = MIPS_CPU_ISA_IV; 508 c->isa_level = MIPS_CPU_ISA_IV;
475 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 509 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
476 MIPS_CPU_LLSC; 510 MIPS_CPU_LLSC;
@@ -486,6 +520,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
486 break; 520 break;
487 case PRID_IMP_RM9000: 521 case PRID_IMP_RM9000:
488 c->cputype = CPU_RM9000; 522 c->cputype = CPU_RM9000;
523 __cpu_name[cpu] = "RM9000";
489 c->isa_level = MIPS_CPU_ISA_IV; 524 c->isa_level = MIPS_CPU_ISA_IV;
490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 525 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
491 MIPS_CPU_LLSC; 526 MIPS_CPU_LLSC;
@@ -500,6 +535,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
500 break; 535 break;
501 case PRID_IMP_R8000: 536 case PRID_IMP_R8000:
502 c->cputype = CPU_R8000; 537 c->cputype = CPU_R8000;
538 __cpu_name[cpu] = "RM8000";
503 c->isa_level = MIPS_CPU_ISA_IV; 539 c->isa_level = MIPS_CPU_ISA_IV;
504 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 540 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
505 MIPS_CPU_FPU | MIPS_CPU_32FPR | 541 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -508,6 +544,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
508 break; 544 break;
509 case PRID_IMP_R10000: 545 case PRID_IMP_R10000:
510 c->cputype = CPU_R10000; 546 c->cputype = CPU_R10000;
547 __cpu_name[cpu] = "R10000";
511 c->isa_level = MIPS_CPU_ISA_IV; 548 c->isa_level = MIPS_CPU_ISA_IV;
512 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 549 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
513 MIPS_CPU_FPU | MIPS_CPU_32FPR | 550 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -517,6 +554,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
517 break; 554 break;
518 case PRID_IMP_R12000: 555 case PRID_IMP_R12000:
519 c->cputype = CPU_R12000; 556 c->cputype = CPU_R12000;
557 __cpu_name[cpu] = "R12000";
520 c->isa_level = MIPS_CPU_ISA_IV; 558 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 559 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
522 MIPS_CPU_FPU | MIPS_CPU_32FPR | 560 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -526,6 +564,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
526 break; 564 break;
527 case PRID_IMP_R14000: 565 case PRID_IMP_R14000:
528 c->cputype = CPU_R14000; 566 c->cputype = CPU_R14000;
567 __cpu_name[cpu] = "R14000";
529 c->isa_level = MIPS_CPU_ISA_IV; 568 c->isa_level = MIPS_CPU_ISA_IV;
530 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 569 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
531 MIPS_CPU_FPU | MIPS_CPU_32FPR | 570 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -535,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
535 break; 574 break;
536 case PRID_IMP_LOONGSON2: 575 case PRID_IMP_LOONGSON2:
537 c->cputype = CPU_LOONGSON2; 576 c->cputype = CPU_LOONGSON2;
577 __cpu_name[cpu] = "ICT Loongson-2";
538 c->isa_level = MIPS_CPU_ISA_III; 578 c->isa_level = MIPS_CPU_ISA_III;
539 c->options = R4K_OPTS | 579 c->options = R4K_OPTS |
540 MIPS_CPU_FPU | MIPS_CPU_LLSC | 580 MIPS_CPU_FPU | MIPS_CPU_LLSC |
@@ -652,21 +692,24 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
652 692
653static void __cpuinit decode_configs(struct cpuinfo_mips *c) 693static void __cpuinit decode_configs(struct cpuinfo_mips *c)
654{ 694{
695 int ok;
696
655 /* MIPS32 or MIPS64 compliant CPU. */ 697 /* MIPS32 or MIPS64 compliant CPU. */
656 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 698 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
657 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 699 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
658 700
659 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 701 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
660 702
661 /* Read Config registers. */ 703 ok = decode_config0(c); /* Read Config registers. */
662 if (!decode_config0(c)) 704 BUG_ON(!ok); /* Arch spec violation! */
663 return; /* actually worth a panic() */ 705 if (ok)
664 if (!decode_config1(c)) 706 ok = decode_config1(c);
665 return; 707 if (ok)
666 if (!decode_config2(c)) 708 ok = decode_config2(c);
667 return; 709 if (ok)
668 if (!decode_config3(c)) 710 ok = decode_config3(c);
669 return; 711
712 mips_probe_watch_registers(c);
670} 713}
671 714
672#ifdef CONFIG_CPU_MIPSR2 715#ifdef CONFIG_CPU_MIPSR2
@@ -675,52 +718,62 @@ extern void spram_config(void);
675static inline void spram_config(void) {} 718static inline void spram_config(void) {}
676#endif 719#endif
677 720
678static inline void cpu_probe_mips(struct cpuinfo_mips *c) 721static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
679{ 722{
680 decode_configs(c); 723 decode_configs(c);
681 mips_probe_watch_registers(c);
682 switch (c->processor_id & 0xff00) { 724 switch (c->processor_id & 0xff00) {
683 case PRID_IMP_4KC: 725 case PRID_IMP_4KC:
684 c->cputype = CPU_4KC; 726 c->cputype = CPU_4KC;
727 __cpu_name[cpu] = "MIPS 4Kc";
685 break; 728 break;
686 case PRID_IMP_4KEC: 729 case PRID_IMP_4KEC:
687 c->cputype = CPU_4KEC; 730 c->cputype = CPU_4KEC;
731 __cpu_name[cpu] = "MIPS 4KEc";
688 break; 732 break;
689 case PRID_IMP_4KECR2: 733 case PRID_IMP_4KECR2:
690 c->cputype = CPU_4KEC; 734 c->cputype = CPU_4KEC;
735 __cpu_name[cpu] = "MIPS 4KEc";
691 break; 736 break;
692 case PRID_IMP_4KSC: 737 case PRID_IMP_4KSC:
693 case PRID_IMP_4KSD: 738 case PRID_IMP_4KSD:
694 c->cputype = CPU_4KSC; 739 c->cputype = CPU_4KSC;
740 __cpu_name[cpu] = "MIPS 4KSc";
695 break; 741 break;
696 case PRID_IMP_5KC: 742 case PRID_IMP_5KC:
697 c->cputype = CPU_5KC; 743 c->cputype = CPU_5KC;
744 __cpu_name[cpu] = "MIPS 5Kc";
698 break; 745 break;
699 case PRID_IMP_20KC: 746 case PRID_IMP_20KC:
700 c->cputype = CPU_20KC; 747 c->cputype = CPU_20KC;
748 __cpu_name[cpu] = "MIPS 20Kc";
701 break; 749 break;
702 case PRID_IMP_24K: 750 case PRID_IMP_24K:
703 case PRID_IMP_24KE: 751 case PRID_IMP_24KE:
704 c->cputype = CPU_24K; 752 c->cputype = CPU_24K;
753 __cpu_name[cpu] = "MIPS 24Kc";
705 break; 754 break;
706 case PRID_IMP_25KF: 755 case PRID_IMP_25KF:
707 c->cputype = CPU_25KF; 756 c->cputype = CPU_25KF;
757 __cpu_name[cpu] = "MIPS 25Kc";
708 break; 758 break;
709 case PRID_IMP_34K: 759 case PRID_IMP_34K:
710 c->cputype = CPU_34K; 760 c->cputype = CPU_34K;
761 __cpu_name[cpu] = "MIPS 34Kc";
711 break; 762 break;
712 case PRID_IMP_74K: 763 case PRID_IMP_74K:
713 c->cputype = CPU_74K; 764 c->cputype = CPU_74K;
765 __cpu_name[cpu] = "MIPS 74Kc";
714 break; 766 break;
715 case PRID_IMP_1004K: 767 case PRID_IMP_1004K:
716 c->cputype = CPU_1004K; 768 c->cputype = CPU_1004K;
769 __cpu_name[cpu] = "MIPS 1004Kc";
717 break; 770 break;
718 } 771 }
719 772
720 spram_config(); 773 spram_config();
721} 774}
722 775
723static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 776static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
724{ 777{
725 decode_configs(c); 778 decode_configs(c);
726 switch (c->processor_id & 0xff00) { 779 switch (c->processor_id & 0xff00) {
@@ -729,23 +782,31 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
729 switch ((c->processor_id >> 24) & 0xff) { 782 switch ((c->processor_id >> 24) & 0xff) {
730 case 0: 783 case 0:
731 c->cputype = CPU_AU1000; 784 c->cputype = CPU_AU1000;
785 __cpu_name[cpu] = "Au1000";
732 break; 786 break;
733 case 1: 787 case 1:
734 c->cputype = CPU_AU1500; 788 c->cputype = CPU_AU1500;
789 __cpu_name[cpu] = "Au1500";
735 break; 790 break;
736 case 2: 791 case 2:
737 c->cputype = CPU_AU1100; 792 c->cputype = CPU_AU1100;
793 __cpu_name[cpu] = "Au1100";
738 break; 794 break;
739 case 3: 795 case 3:
740 c->cputype = CPU_AU1550; 796 c->cputype = CPU_AU1550;
797 __cpu_name[cpu] = "Au1550";
741 break; 798 break;
742 case 4: 799 case 4:
743 c->cputype = CPU_AU1200; 800 c->cputype = CPU_AU1200;
744 if (2 == (c->processor_id & 0xff)) 801 __cpu_name[cpu] = "Au1200";
802 if ((c->processor_id & 0xff) == 2) {
745 c->cputype = CPU_AU1250; 803 c->cputype = CPU_AU1250;
804 __cpu_name[cpu] = "Au1250";
805 }
746 break; 806 break;
747 case 5: 807 case 5:
748 c->cputype = CPU_AU1210; 808 c->cputype = CPU_AU1210;
809 __cpu_name[cpu] = "Au1210";
749 break; 810 break;
750 default: 811 default:
751 panic("Unknown Au Core!"); 812 panic("Unknown Au Core!");
@@ -755,154 +816,67 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
755 } 816 }
756} 817}
757 818
758static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 819static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
759{ 820{
760 decode_configs(c); 821 decode_configs(c);
761 822
762 switch (c->processor_id & 0xff00) { 823 switch (c->processor_id & 0xff00) {
763 case PRID_IMP_SB1: 824 case PRID_IMP_SB1:
764 c->cputype = CPU_SB1; 825 c->cputype = CPU_SB1;
826 __cpu_name[cpu] = "SiByte SB1";
765 /* FPU in pass1 is known to have issues. */ 827 /* FPU in pass1 is known to have issues. */
766 if ((c->processor_id & 0xff) < 0x02) 828 if ((c->processor_id & 0xff) < 0x02)
767 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 829 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
768 break; 830 break;
769 case PRID_IMP_SB1A: 831 case PRID_IMP_SB1A:
770 c->cputype = CPU_SB1A; 832 c->cputype = CPU_SB1A;
833 __cpu_name[cpu] = "SiByte SB1A";
771 break; 834 break;
772 } 835 }
773} 836}
774 837
775static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 838static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
776{ 839{
777 decode_configs(c); 840 decode_configs(c);
778 switch (c->processor_id & 0xff00) { 841 switch (c->processor_id & 0xff00) {
779 case PRID_IMP_SR71000: 842 case PRID_IMP_SR71000:
780 c->cputype = CPU_SR71000; 843 c->cputype = CPU_SR71000;
844 __cpu_name[cpu] = "Sandcraft SR71000";
781 c->scache.ways = 8; 845 c->scache.ways = 8;
782 c->tlbsize = 64; 846 c->tlbsize = 64;
783 break; 847 break;
784 } 848 }
785} 849}
786 850
787static inline void cpu_probe_nxp(struct cpuinfo_mips *c) 851static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
788{ 852{
789 decode_configs(c); 853 decode_configs(c);
790 switch (c->processor_id & 0xff00) { 854 switch (c->processor_id & 0xff00) {
791 case PRID_IMP_PR4450: 855 case PRID_IMP_PR4450:
792 c->cputype = CPU_PR4450; 856 c->cputype = CPU_PR4450;
857 __cpu_name[cpu] = "Philips PR4450";
793 c->isa_level = MIPS_CPU_ISA_M32R1; 858 c->isa_level = MIPS_CPU_ISA_M32R1;
794 break; 859 break;
795 default:
796 panic("Unknown NXP Core!"); /* REVISIT: die? */
797 break;
798 } 860 }
799} 861}
800 862
801 863static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
802static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
803{ 864{
804 decode_configs(c); 865 decode_configs(c);
805 switch (c->processor_id & 0xff00) { 866 switch (c->processor_id & 0xff00) {
806 case PRID_IMP_BCM3302: 867 case PRID_IMP_BCM3302:
807 c->cputype = CPU_BCM3302; 868 c->cputype = CPU_BCM3302;
869 __cpu_name[cpu] = "Broadcom BCM3302";
808 break; 870 break;
809 case PRID_IMP_BCM4710: 871 case PRID_IMP_BCM4710:
810 c->cputype = CPU_BCM4710; 872 c->cputype = CPU_BCM4710;
811 break; 873 __cpu_name[cpu] = "Broadcom BCM4710";
812 default:
813 c->cputype = CPU_UNKNOWN;
814 break; 874 break;
815 } 875 }
816} 876}
817 877
818const char *__cpu_name[NR_CPUS]; 878const char *__cpu_name[NR_CPUS];
819 879
820/*
821 * Name a CPU
822 */
823static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
824{
825 const char *name = NULL;
826
827 switch (c->cputype) {
828 case CPU_UNKNOWN: name = "unknown"; break;
829 case CPU_R2000: name = "R2000"; break;
830 case CPU_R3000: name = "R3000"; break;
831 case CPU_R3000A: name = "R3000A"; break;
832 case CPU_R3041: name = "R3041"; break;
833 case CPU_R3051: name = "R3051"; break;
834 case CPU_R3052: name = "R3052"; break;
835 case CPU_R3081: name = "R3081"; break;
836 case CPU_R3081E: name = "R3081E"; break;
837 case CPU_R4000PC: name = "R4000PC"; break;
838 case CPU_R4000SC: name = "R4000SC"; break;
839 case CPU_R4000MC: name = "R4000MC"; break;
840 case CPU_R4200: name = "R4200"; break;
841 case CPU_R4400PC: name = "R4400PC"; break;
842 case CPU_R4400SC: name = "R4400SC"; break;
843 case CPU_R4400MC: name = "R4400MC"; break;
844 case CPU_R4600: name = "R4600"; break;
845 case CPU_R6000: name = "R6000"; break;
846 case CPU_R6000A: name = "R6000A"; break;
847 case CPU_R8000: name = "R8000"; break;
848 case CPU_R10000: name = "R10000"; break;
849 case CPU_R12000: name = "R12000"; break;
850 case CPU_R14000: name = "R14000"; break;
851 case CPU_R4300: name = "R4300"; break;
852 case CPU_R4650: name = "R4650"; break;
853 case CPU_R4700: name = "R4700"; break;
854 case CPU_R5000: name = "R5000"; break;
855 case CPU_R5000A: name = "R5000A"; break;
856 case CPU_R4640: name = "R4640"; break;
857 case CPU_NEVADA: name = "Nevada"; break;
858 case CPU_RM7000: name = "RM7000"; break;
859 case CPU_RM9000: name = "RM9000"; break;
860 case CPU_R5432: name = "R5432"; break;
861 case CPU_4KC: name = "MIPS 4Kc"; break;
862 case CPU_5KC: name = "MIPS 5Kc"; break;
863 case CPU_R4310: name = "R4310"; break;
864 case CPU_SB1: name = "SiByte SB1"; break;
865 case CPU_SB1A: name = "SiByte SB1A"; break;
866 case CPU_TX3912: name = "TX3912"; break;
867 case CPU_TX3922: name = "TX3922"; break;
868 case CPU_TX3927: name = "TX3927"; break;
869 case CPU_AU1000: name = "Au1000"; break;
870 case CPU_AU1500: name = "Au1500"; break;
871 case CPU_AU1100: name = "Au1100"; break;
872 case CPU_AU1550: name = "Au1550"; break;
873 case CPU_AU1200: name = "Au1200"; break;
874 case CPU_AU1210: name = "Au1210"; break;
875 case CPU_AU1250: name = "Au1250"; break;
876 case CPU_4KEC: name = "MIPS 4KEc"; break;
877 case CPU_4KSC: name = "MIPS 4KSc"; break;
878 case CPU_VR41XX: name = "NEC Vr41xx"; break;
879 case CPU_R5500: name = "R5500"; break;
880 case CPU_TX49XX: name = "TX49xx"; break;
881 case CPU_20KC: name = "MIPS 20Kc"; break;
882 case CPU_24K: name = "MIPS 24K"; break;
883 case CPU_25KF: name = "MIPS 25Kf"; break;
884 case CPU_34K: name = "MIPS 34K"; break;
885 case CPU_1004K: name = "MIPS 1004K"; break;
886 case CPU_74K: name = "MIPS 74K"; break;
887 case CPU_VR4111: name = "NEC VR4111"; break;
888 case CPU_VR4121: name = "NEC VR4121"; break;
889 case CPU_VR4122: name = "NEC VR4122"; break;
890 case CPU_VR4131: name = "NEC VR4131"; break;
891 case CPU_VR4133: name = "NEC VR4133"; break;
892 case CPU_VR4181: name = "NEC VR4181"; break;
893 case CPU_VR4181A: name = "NEC VR4181A"; break;
894 case CPU_SR71000: name = "Sandcraft SR71000"; break;
895 case CPU_BCM3302: name = "Broadcom BCM3302"; break;
896 case CPU_BCM4710: name = "Broadcom BCM4710"; break;
897 case CPU_PR4450: name = "Philips PR4450"; break;
898 case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
899 default:
900 BUG();
901 }
902
903 return name;
904}
905
906__cpuinit void cpu_probe(void) 880__cpuinit void cpu_probe(void)
907{ 881{
908 struct cpuinfo_mips *c = &current_cpu_data; 882 struct cpuinfo_mips *c = &current_cpu_data;
@@ -915,30 +889,31 @@ __cpuinit void cpu_probe(void)
915 c->processor_id = read_c0_prid(); 889 c->processor_id = read_c0_prid();
916 switch (c->processor_id & 0xff0000) { 890 switch (c->processor_id & 0xff0000) {
917 case PRID_COMP_LEGACY: 891 case PRID_COMP_LEGACY:
918 cpu_probe_legacy(c); 892 cpu_probe_legacy(c, cpu);
919 break; 893 break;
920 case PRID_COMP_MIPS: 894 case PRID_COMP_MIPS:
921 cpu_probe_mips(c); 895 cpu_probe_mips(c, cpu);
922 break; 896 break;
923 case PRID_COMP_ALCHEMY: 897 case PRID_COMP_ALCHEMY:
924 cpu_probe_alchemy(c); 898 cpu_probe_alchemy(c, cpu);
925 break; 899 break;
926 case PRID_COMP_SIBYTE: 900 case PRID_COMP_SIBYTE:
927 cpu_probe_sibyte(c); 901 cpu_probe_sibyte(c, cpu);
928 break; 902 break;
929 case PRID_COMP_BROADCOM: 903 case PRID_COMP_BROADCOM:
930 cpu_probe_broadcom(c); 904 cpu_probe_broadcom(c, cpu);
931 break; 905 break;
932 case PRID_COMP_SANDCRAFT: 906 case PRID_COMP_SANDCRAFT:
933 cpu_probe_sandcraft(c); 907 cpu_probe_sandcraft(c, cpu);
934 break; 908 break;
935 case PRID_COMP_NXP: 909 case PRID_COMP_NXP:
936 cpu_probe_nxp(c); 910 cpu_probe_nxp(c, cpu);
937 break; 911 break;
938 default:
939 c->cputype = CPU_UNKNOWN;
940 } 912 }
941 913
914 BUG_ON(!__cpu_name[cpu]);
915 BUG_ON(c->cputype == CPU_UNKNOWN);
916
942 /* 917 /*
943 * Platform code can force the cpu type to optimize code 918 * Platform code can force the cpu type to optimize code
944 * generation. In that case be sure the cpu type is correctly 919 * generation. In that case be sure the cpu type is correctly
@@ -958,8 +933,6 @@ __cpuinit void cpu_probe(void)
958 } 933 }
959 } 934 }
960 935
961 __cpu_name[cpu] = cpu_to_name(c);
962
963 if (cpu_has_mips_r2) 936 if (cpu_has_mips_r2)
964 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 937 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
965 else 938 else
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index b79ea7055ec3..8bf88faf5afd 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -195,12 +195,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
195/* preload SMP state for boot cpu */ 195/* preload SMP state for boot cpu */
196void __devinit smp_prepare_boot_cpu(void) 196void __devinit smp_prepare_boot_cpu(void)
197{ 197{
198 /*
199 * This assumes that bootup is always handled by the processor
200 * with the logic and physical number 0.
201 */
202 __cpu_number_map[0] = 0;
203 __cpu_logical_map[0] = 0;
204 cpu_set(0, phys_cpu_present_map); 198 cpu_set(0, phys_cpu_present_map);
205 cpu_set(0, cpu_online_map); 199 cpu_set(0, cpu_online_map);
206 cpu_set(0, cpu_callin_map); 200 cpu_set(0, cpu_callin_map);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 80b9e070c207..353056110f2b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -32,6 +32,7 @@
32#include <asm/cpu.h> 32#include <asm/cpu.h>
33#include <asm/dsp.h> 33#include <asm/dsp.h>
34#include <asm/fpu.h> 34#include <asm/fpu.h>
35#include <asm/fpu_emulator.h>
35#include <asm/mipsregs.h> 36#include <asm/mipsregs.h>
36#include <asm/mipsmtregs.h> 37#include <asm/mipsmtregs.h>
37#include <asm/module.h> 38#include <asm/module.h>
@@ -722,6 +723,21 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
722 die_if_kernel("Kernel bug detected", regs); 723 die_if_kernel("Kernel bug detected", regs);
723 force_sig(SIGTRAP, current); 724 force_sig(SIGTRAP, current);
724 break; 725 break;
726 case BRK_MEMU:
727 /*
728 * Address errors may be deliberately induced by the FPU
729 * emulator to retake control of the CPU after executing the
730 * instruction in the delay slot of an emulated branch.
731 *
732 * Terminate if exception was recognized as a delay slot return
733 * otherwise handle as normal.
734 */
735 if (do_dsemulret(regs))
736 return;
737
738 die_if_kernel("Math emu break/trap", regs);
739 force_sig(SIGTRAP, current);
740 break;
725 default: 741 default:
726 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 742 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
727 die_if_kernel(b, regs); 743 die_if_kernel(b, regs);
@@ -1555,6 +1571,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1555#ifdef CONFIG_64BIT 1571#ifdef CONFIG_64BIT
1556 unsigned long uncached_ebase = TO_UNCAC(ebase); 1572 unsigned long uncached_ebase = TO_UNCAC(ebase);
1557#endif 1573#endif
1574 if (cpu_has_mips_r2)
1575 ebase += (read_c0_ebase() & 0x3ffff000);
1558 1576
1559 if (!addr) 1577 if (!addr)
1560 panic(panic_null_cerr); 1578 panic(panic_null_cerr);
@@ -1588,8 +1606,11 @@ void __init trap_init(void)
1588 1606
1589 if (cpu_has_veic || cpu_has_vint) 1607 if (cpu_has_veic || cpu_has_vint)
1590 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1608 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1591 else 1609 else {
1592 ebase = CAC_BASE; 1610 ebase = CAC_BASE;
1611 if (cpu_has_mips_r2)
1612 ebase += (read_c0_ebase() & 0x3ffff000);
1613 }
1593 1614
1594 per_cpu_trap_init(); 1615 per_cpu_trap_init();
1595 1616
@@ -1697,11 +1718,11 @@ void __init trap_init(void)
1697 1718
1698 if (cpu_has_vce) 1719 if (cpu_has_vce)
1699 /* Special exception: R4[04]00 uses also the divec space. */ 1720 /* Special exception: R4[04]00 uses also the divec space. */
1700 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1721 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1701 else if (cpu_has_4kex) 1722 else if (cpu_has_4kex)
1702 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1723 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1703 else 1724 else
1704 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1725 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1705 1726
1706 signal_init(); 1727 signal_init();
1707#ifdef CONFIG_MIPS32_COMPAT 1728#ifdef CONFIG_MIPS32_COMPAT
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 20709669e592..bf4c4a979abb 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -499,22 +499,10 @@ sigill:
499 499
500asmlinkage void do_ade(struct pt_regs *regs) 500asmlinkage void do_ade(struct pt_regs *regs)
501{ 501{
502 extern int do_dsemulret(struct pt_regs *);
503 unsigned int __user *pc; 502 unsigned int __user *pc;
504 mm_segment_t seg; 503 mm_segment_t seg;
505 504
506 /* 505 /*
507 * Address errors may be deliberately induced by the FPU emulator to
508 * retake control of the CPU after executing the instruction in the
509 * delay slot of an emulated branch.
510 */
511 /* Terminate if exception was recognized as a delay slot return */
512 if (do_dsemulret(regs))
513 return;
514
515 /* Otherwise handle as normal */
516
517 /*
518 * Did we catch a fault trying to load an instruction? 506 * Did we catch a fault trying to load an instruction?
519 * Or are we running in MIPS16 mode? 507 * Or are we running in MIPS16 mode?
520 */ 508 */
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 7ec0b217dfd3..890f77927d62 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -48,7 +48,6 @@
48#include <asm/branch.h> 48#include <asm/branch.h>
49 49
50#include "ieee754.h" 50#include "ieee754.h"
51#include "dsemul.h"
52 51
53/* Strap kernel emulator for full MIPS IV emulation */ 52/* Strap kernel emulator for full MIPS IV emulation */
54 53
@@ -346,9 +345,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
346 /* cop control register rd -> gpr[rt] */ 345 /* cop control register rd -> gpr[rt] */
347 u32 value; 346 u32 value;
348 347
349 if (ir == CP1UNDEF) {
350 return do_dsemulret(xcp);
351 }
352 if (MIPSInst_RD(ir) == FPCREG_CSR) { 348 if (MIPSInst_RD(ir) == FPCREG_CSR) {
353 value = ctx->fcr31; 349 value = ctx->fcr31;
354 value = (value & ~0x3) | mips_rm[value & 0x3]; 350 value = (value & ~0x3) | mips_rm[value & 0x3];
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index 653e325849e4..df7b9d928efc 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -18,7 +18,6 @@
18#include <asm/fpu_emulator.h> 18#include <asm/fpu_emulator.h>
19 19
20#include "ieee754.h" 20#include "ieee754.h"
21#include "dsemul.h"
22 21
23/* Strap kernel emulator for full MIPS IV emulation */ 22/* Strap kernel emulator for full MIPS IV emulation */
24 23
@@ -94,7 +93,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
94 return SIGBUS; 93 return SIGBUS;
95 94
96 err = __put_user(ir, &fr->emul); 95 err = __put_user(ir, &fr->emul);
97 err |= __put_user((mips_instruction)BADINST, &fr->badinst); 96 err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst);
98 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); 97 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
99 err |= __put_user(cpc, &fr->epc); 98 err |= __put_user(cpc, &fr->epc);
100 99
@@ -130,13 +129,13 @@ int do_dsemulret(struct pt_regs *xcp)
130 /* 129 /*
131 * Do some sanity checking on the stackframe: 130 * Do some sanity checking on the stackframe:
132 * 131 *
133 * - Is the instruction pointed to by the EPC an BADINST? 132 * - Is the instruction pointed to by the EPC an BREAK_MATH?
134 * - Is the following memory word the BD_COOKIE? 133 * - Is the following memory word the BD_COOKIE?
135 */ 134 */
136 err = __get_user(insn, &fr->badinst); 135 err = __get_user(insn, &fr->badinst);
137 err |= __get_user(cookie, &fr->cookie); 136 err |= __get_user(cookie, &fr->cookie);
138 137
139 if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { 138 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
140 fpuemustats.errors++; 139 fpuemustats.errors++;
141 return 0; 140 return 0;
142 } 141 }
diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h
deleted file mode 100644
index 091f0e76730f..000000000000
--- a/arch/mips/math-emu/dsemul.h
+++ /dev/null
@@ -1,17 +0,0 @@
1extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc);
2extern int do_dsemulret(struct pt_regs *xcp);
3
4/* Instruction which will always cause an address error */
5#define AdELOAD 0x8c000001 /* lw $0,1($0) */
6/* Instruction which will plainly cause a CP1 exception when FPU is disabled */
7#define CP1UNDEF 0x44400001 /* cfc1 $0,$0 undef */
8
9/* Instruction inserted following the badinst to further tag the sequence */
10#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */
11
12/* Setup which instruction to use for trampoline */
13#ifdef STANDALONE_EMULATOR
14#define BADINST CP1UNDEF
15#else
16#define BADINST AdELOAD
17#endif
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 4a74423b2ba8..01129a9d50fa 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -49,6 +49,7 @@
49#include <linux/platform_device.h> 49#include <linux/platform_device.h>
50#include <linux/delay.h> 50#include <linux/delay.h>
51#include <linux/gpio.h> 51#include <linux/gpio.h>
52#include <linux/leds.h>
52#include <asm/io.h> 53#include <asm/io.h>
53#include <asm/reboot.h> 54#include <asm/reboot.h>
54#include <asm/txx9/generic.h> 55#include <asm/txx9/generic.h>
@@ -210,10 +211,6 @@ static void __init rbtx4927_mem_setup(void)
210 /* TX4927-SIO DTR on (PIO[15]) */ 211 /* TX4927-SIO DTR on (PIO[15]) */
211 gpio_request(15, "sio-dtr"); 212 gpio_request(15, "sio-dtr");
212 gpio_direction_output(15, 1); 213 gpio_direction_output(15, 1);
213 gpio_request(0, "led");
214 gpio_direction_output(0, 1);
215 gpio_request(1, "led");
216 gpio_direction_output(1, 1);
217 214
218 tx4927_sio_init(0, 0); 215 tx4927_sio_init(0, 0);
219#ifdef CONFIG_SERIAL_TXX9_CONSOLE 216#ifdef CONFIG_SERIAL_TXX9_CONSOLE
@@ -315,6 +312,25 @@ static void __init rbtx4927_mtd_init(void)
315 tx4927_mtd_init(i); 312 tx4927_mtd_init(i);
316} 313}
317 314
315static void __init rbtx4927_gpioled_init(void)
316{
317 static struct gpio_led leds[] = {
318 { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
319 { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
320 };
321 static struct gpio_led_platform_data pdata = {
322 .num_leds = ARRAY_SIZE(leds),
323 .leds = leds,
324 };
325 struct platform_device *pdev = platform_device_alloc("leds-gpio", 0);
326
327 if (!pdev)
328 return;
329 pdev->dev.platform_data = &pdata;
330 if (platform_device_add(pdev))
331 platform_device_put(pdev);
332}
333
318static void __init rbtx4927_device_init(void) 334static void __init rbtx4927_device_init(void)
319{ 335{
320 toshiba_rbtx4927_rtc_init(); 336 toshiba_rbtx4927_rtc_init();
@@ -322,6 +338,7 @@ static void __init rbtx4927_device_init(void)
322 tx4927_wdt_init(); 338 tx4927_wdt_init();
323 rbtx4927_mtd_init(); 339 rbtx4927_mtd_init();
324 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); 340 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
341 rbtx4927_gpioled_init();
325} 342}
326 343
327struct txx9_board_vec rbtx4927_vec __initdata = { 344struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 6daee9b1cd5e..98fbd9391bf8 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -308,16 +308,22 @@ static void __init rbtx4939_device_init(void)
308#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) 308#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
309 int i, j; 309 int i, j;
310 unsigned char ethaddr[2][6]; 310 unsigned char ethaddr[2][6];
311 u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
312
311 for (i = 0; i < 2; i++) { 313 for (i = 0; i < 2; i++) {
312 unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10); 314 unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
313 if (readb(rbtx4939_bdipsw_addr) & 8) { 315 if (bdipsw == 0)
316 memcpy(ethaddr[i], (void *)area, 6);
317 else {
314 u16 buf[3]; 318 u16 buf[3];
315 area -= 0x03000000; 319 if (bdipsw & 8)
320 area -= 0x03000000;
321 else
322 area -= 0x01000000;
316 for (j = 0; j < 3; j++) 323 for (j = 0; j < 3; j++)
317 buf[j] = le16_to_cpup((u16 *)(area + j * 2)); 324 buf[j] = le16_to_cpup((u16 *)(area + j * 2));
318 memcpy(ethaddr[i], buf, 6); 325 memcpy(ethaddr[i], buf, 6);
319 } else 326 }
320 memcpy(ethaddr[i], (void *)area, 6);
321 } 327 }
322 tx4939_ethaddr_init(ethaddr[0], ethaddr[1]); 328 tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
323#endif 329#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 19:02:31 -0500