aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/mips/Makefile9
-rw-r--r--arch/mips/ath79/mach-db120.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c2
-rw-r--r--arch/mips/cavium-octeon/setup.c9
-rw-r--r--arch/mips/include/asm/asmmacro-32.h6
-rw-r--r--arch/mips/include/asm/asmmacro.h18
-rw-r--r--arch/mips/include/asm/cop2.h8
-rw-r--r--arch/mips/include/asm/fpregdef.h14
-rw-r--r--arch/mips/include/asm/fpu.h4
-rw-r--r--arch/mips/include/asm/ftrace.h4
-rw-r--r--arch/mips/include/asm/idle.h7
-rw-r--r--arch/mips/include/asm/mipsregs.h11
-rw-r--r--arch/mips/include/uapi/asm/ptrace.h2
-rw-r--r--arch/mips/include/uapi/asm/unistd.h15
-rw-r--r--arch/mips/kernel/branch.c8
-rw-r--r--arch/mips/kernel/genex.S1
-rw-r--r--arch/mips/kernel/idle.c3
-rw-r--r--arch/mips/kernel/r2300_fpu.S6
-rw-r--r--arch/mips/kernel/r2300_switch.S5
-rw-r--r--arch/mips/kernel/r4k_fpu.S27
-rw-r--r--arch/mips/kernel/r4k_switch.S15
-rw-r--r--arch/mips/kernel/r6000_fpu.S5
-rw-r--r--arch/mips/kernel/scall32-o32.S1
-rw-r--r--arch/mips/kernel/scall64-64.S1
-rw-r--r--arch/mips/kernel/scall64-n32.S1
-rw-r--r--arch/mips/kernel/scall64-o32.S1
-rw-r--r--arch/mips/kernel/setup.c3
-rw-r--r--arch/mips/lasat/Kconfig2
-rw-r--r--arch/mips/lib/r3k_dump_tlb.c4
-rw-r--r--arch/mips/lib/strnlen_user.S6
-rw-r--r--arch/mips/loongson/lemote-2f/clock.c5
-rw-r--r--arch/mips/math-emu/cp1emu.c10
-rw-r--r--arch/mips/mm/tlbex.c6
-rw-r--r--arch/mips/mti-malta/Makefile3
-rw-r--r--arch/mips/mti-sead3/Makefile1
-rw-r--r--arch/mips/mti-sead3/sead3-i2c.c8
-rw-r--r--arch/mips/mti-sead3/sead3-pic32-bus.c102
-rw-r--r--arch/mips/mti-sead3/sead3-pic32-i2c-drv.c423
-rw-r--r--arch/mips/pci/msi-xlp.c4
-rw-r--r--arch/mips/pci/pci-lantiq.c7
-rw-r--r--arch/mips/pmcs-msp71xx/msp_irq.c1
-rw-r--r--arch/mips/pmcs-msp71xx/msp_irq_cic.c4
-rw-r--r--arch/mips/sibyte/Makefile1
44 files changed, 171 insertions, 605 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ad6badb6be71..f43aa536c517 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2066,6 +2066,7 @@ config MIPS_CPS
2066 support is unavailable. 2066 support is unavailable.
2067 2067
2068config MIPS_CPS_PM 2068config MIPS_CPS_PM
2069 depends on MIPS_CPS
2069 select MIPS_CPC 2070 select MIPS_CPC
2070 bool 2071 bool
2071 2072
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 23cb94806fbc..58076472bdd8 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -93,6 +93,15 @@ LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
93KBUILD_AFLAGS_MODULE += -mlong-calls 93KBUILD_AFLAGS_MODULE += -mlong-calls
94KBUILD_CFLAGS_MODULE += -mlong-calls 94KBUILD_CFLAGS_MODULE += -mlong-calls
95 95
96#
97# pass -msoft-float to GAS if it supports it. However on newer binutils
98# (specifically newer than 2.24.51.20140728) we then also need to explicitly
99# set ".set hardfloat" in all files which manipulate floating point registers.
100#
101ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
102 cflags-y += -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
103endif
104
96cflags-y += -ffreestanding 105cflags-y += -ffreestanding
97 106
98# 107#
diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c
index 4d661a1d2dae..9423f5aed287 100644
--- a/arch/mips/ath79/mach-db120.c
+++ b/arch/mips/ath79/mach-db120.c
@@ -113,7 +113,7 @@ static void __init db120_pci_init(u8 *eeprom)
113 ath79_register_pci(); 113 ath79_register_pci();
114} 114}
115#else 115#else
116static inline void db120_pci_init(void) {} 116static inline void db120_pci_init(u8 *eeprom) {}
117#endif /* CONFIG_PCI */ 117#endif /* CONFIG_PCI */
118 118
119static void __init db120_setup(void) 119static void __init db120_setup(void)
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 741734049675..2bc4aa95944e 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -809,6 +809,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
809 .irq_set_type = octeon_irq_ciu_gpio_set_type, 809 .irq_set_type = octeon_irq_ciu_gpio_set_type,
810#ifdef CONFIG_SMP 810#ifdef CONFIG_SMP
811 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, 811 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
812 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
812#endif 813#endif
813 .flags = IRQCHIP_SET_TYPE_MASKED, 814 .flags = IRQCHIP_SET_TYPE_MASKED,
814}; 815};
@@ -823,6 +824,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
823 .irq_set_type = octeon_irq_ciu_gpio_set_type, 824 .irq_set_type = octeon_irq_ciu_gpio_set_type,
824#ifdef CONFIG_SMP 825#ifdef CONFIG_SMP
825 .irq_set_affinity = octeon_irq_ciu_set_affinity, 826 .irq_set_affinity = octeon_irq_ciu_set_affinity,
827 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
826#endif 828#endif
827 .flags = IRQCHIP_SET_TYPE_MASKED, 829 .flags = IRQCHIP_SET_TYPE_MASKED,
828}; 830};
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 38f4c32e2816..5ebdb32d9a2b 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -806,15 +806,6 @@ void __init prom_init(void)
806#endif 806#endif
807 } 807 }
808 808
809 if (octeon_is_simulation()) {
810 /*
811 * The simulator uses a mtdram device pre filled with
812 * the filesystem. Also specify the calibration delay
813 * to avoid calculating it every time.
814 */
815 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
816 }
817
818 mips_hpt_frequency = octeon_get_clock_rate(); 809 mips_hpt_frequency = octeon_get_clock_rate();
819 810
820 octeon_init_cvmcount(); 811 octeon_init_cvmcount();
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index e38c2811d4e2..cdac7b3eeaf7 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -13,6 +13,8 @@
13#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
14 14
15 .macro fpu_save_single thread tmp=t0 15 .macro fpu_save_single thread tmp=t0
16 .set push
17 SET_HARDFLOAT
16 cfc1 \tmp, fcr31 18 cfc1 \tmp, fcr31
17 swc1 $f0, THREAD_FPR0_LS64(\thread) 19 swc1 $f0, THREAD_FPR0_LS64(\thread)
18 swc1 $f1, THREAD_FPR1_LS64(\thread) 20 swc1 $f1, THREAD_FPR1_LS64(\thread)
@@ -47,9 +49,12 @@
47 swc1 $f30, THREAD_FPR30_LS64(\thread) 49 swc1 $f30, THREAD_FPR30_LS64(\thread)
48 swc1 $f31, THREAD_FPR31_LS64(\thread) 50 swc1 $f31, THREAD_FPR31_LS64(\thread)
49 sw \tmp, THREAD_FCR31(\thread) 51 sw \tmp, THREAD_FCR31(\thread)
52 .set pop
50 .endm 53 .endm
51 54
52 .macro fpu_restore_single thread tmp=t0 55 .macro fpu_restore_single thread tmp=t0
56 .set push
57 SET_HARDFLOAT
53 lw \tmp, THREAD_FCR31(\thread) 58 lw \tmp, THREAD_FCR31(\thread)
54 lwc1 $f0, THREAD_FPR0_LS64(\thread) 59 lwc1 $f0, THREAD_FPR0_LS64(\thread)
55 lwc1 $f1, THREAD_FPR1_LS64(\thread) 60 lwc1 $f1, THREAD_FPR1_LS64(\thread)
@@ -84,6 +89,7 @@
84 lwc1 $f30, THREAD_FPR30_LS64(\thread) 89 lwc1 $f30, THREAD_FPR30_LS64(\thread)
85 lwc1 $f31, THREAD_FPR31_LS64(\thread) 90 lwc1 $f31, THREAD_FPR31_LS64(\thread)
86 ctc1 \tmp, fcr31 91 ctc1 \tmp, fcr31
92 .set pop
87 .endm 93 .endm
88 94
89 .macro cpu_save_nonscratch thread 95 .macro cpu_save_nonscratch thread
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index cd9a98bc8f60..6caf8766b80f 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -57,6 +57,8 @@
57#endif /* CONFIG_CPU_MIPSR2 */ 57#endif /* CONFIG_CPU_MIPSR2 */
58 58
59 .macro fpu_save_16even thread tmp=t0 59 .macro fpu_save_16even thread tmp=t0
60 .set push
61 SET_HARDFLOAT
60 cfc1 \tmp, fcr31 62 cfc1 \tmp, fcr31
61 sdc1 $f0, THREAD_FPR0_LS64(\thread) 63 sdc1 $f0, THREAD_FPR0_LS64(\thread)
62 sdc1 $f2, THREAD_FPR2_LS64(\thread) 64 sdc1 $f2, THREAD_FPR2_LS64(\thread)
@@ -75,11 +77,13 @@
75 sdc1 $f28, THREAD_FPR28_LS64(\thread) 77 sdc1 $f28, THREAD_FPR28_LS64(\thread)
76 sdc1 $f30, THREAD_FPR30_LS64(\thread) 78 sdc1 $f30, THREAD_FPR30_LS64(\thread)
77 sw \tmp, THREAD_FCR31(\thread) 79 sw \tmp, THREAD_FCR31(\thread)
80 .set pop
78 .endm 81 .endm
79 82
80 .macro fpu_save_16odd thread 83 .macro fpu_save_16odd thread
81 .set push 84 .set push
82 .set mips64r2 85 .set mips64r2
86 SET_HARDFLOAT
83 sdc1 $f1, THREAD_FPR1_LS64(\thread) 87 sdc1 $f1, THREAD_FPR1_LS64(\thread)
84 sdc1 $f3, THREAD_FPR3_LS64(\thread) 88 sdc1 $f3, THREAD_FPR3_LS64(\thread)
85 sdc1 $f5, THREAD_FPR5_LS64(\thread) 89 sdc1 $f5, THREAD_FPR5_LS64(\thread)
@@ -110,6 +114,8 @@
110 .endm 114 .endm
111 115
112 .macro fpu_restore_16even thread tmp=t0 116 .macro fpu_restore_16even thread tmp=t0
117 .set push
118 SET_HARDFLOAT
113 lw \tmp, THREAD_FCR31(\thread) 119 lw \tmp, THREAD_FCR31(\thread)
114 ldc1 $f0, THREAD_FPR0_LS64(\thread) 120 ldc1 $f0, THREAD_FPR0_LS64(\thread)
115 ldc1 $f2, THREAD_FPR2_LS64(\thread) 121 ldc1 $f2, THREAD_FPR2_LS64(\thread)
@@ -133,6 +139,7 @@
133 .macro fpu_restore_16odd thread 139 .macro fpu_restore_16odd thread
134 .set push 140 .set push
135 .set mips64r2 141 .set mips64r2
142 SET_HARDFLOAT
136 ldc1 $f1, THREAD_FPR1_LS64(\thread) 143 ldc1 $f1, THREAD_FPR1_LS64(\thread)
137 ldc1 $f3, THREAD_FPR3_LS64(\thread) 144 ldc1 $f3, THREAD_FPR3_LS64(\thread)
138 ldc1 $f5, THREAD_FPR5_LS64(\thread) 145 ldc1 $f5, THREAD_FPR5_LS64(\thread)
@@ -277,6 +284,7 @@
277 .macro cfcmsa rd, cs 284 .macro cfcmsa rd, cs
278 .set push 285 .set push
279 .set noat 286 .set noat
287 SET_HARDFLOAT
280 .insn 288 .insn
281 .word CFC_MSA_INSN | (\cs << 11) 289 .word CFC_MSA_INSN | (\cs << 11)
282 move \rd, $1 290 move \rd, $1
@@ -286,6 +294,7 @@
286 .macro ctcmsa cd, rs 294 .macro ctcmsa cd, rs
287 .set push 295 .set push
288 .set noat 296 .set noat
297 SET_HARDFLOAT
289 move $1, \rs 298 move $1, \rs
290 .word CTC_MSA_INSN | (\cd << 6) 299 .word CTC_MSA_INSN | (\cd << 6)
291 .set pop 300 .set pop
@@ -294,6 +303,7 @@
294 .macro ld_d wd, off, base 303 .macro ld_d wd, off, base
295 .set push 304 .set push
296 .set noat 305 .set noat
306 SET_HARDFLOAT
297 add $1, \base, \off 307 add $1, \base, \off
298 .word LDD_MSA_INSN | (\wd << 6) 308 .word LDD_MSA_INSN | (\wd << 6)
299 .set pop 309 .set pop
@@ -302,6 +312,7 @@
302 .macro st_d wd, off, base 312 .macro st_d wd, off, base
303 .set push 313 .set push
304 .set noat 314 .set noat
315 SET_HARDFLOAT
305 add $1, \base, \off 316 add $1, \base, \off
306 .word STD_MSA_INSN | (\wd << 6) 317 .word STD_MSA_INSN | (\wd << 6)
307 .set pop 318 .set pop
@@ -310,6 +321,7 @@
310 .macro copy_u_w rd, ws, n 321 .macro copy_u_w rd, ws, n
311 .set push 322 .set push
312 .set noat 323 .set noat
324 SET_HARDFLOAT
313 .insn 325 .insn
314 .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11) 326 .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
315 /* move triggers an assembler bug... */ 327 /* move triggers an assembler bug... */
@@ -320,6 +332,7 @@
320 .macro copy_u_d rd, ws, n 332 .macro copy_u_d rd, ws, n
321 .set push 333 .set push
322 .set noat 334 .set noat
335 SET_HARDFLOAT
323 .insn 336 .insn
324 .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11) 337 .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
325 /* move triggers an assembler bug... */ 338 /* move triggers an assembler bug... */
@@ -330,6 +343,7 @@
330 .macro insert_w wd, n, rs 343 .macro insert_w wd, n, rs
331 .set push 344 .set push
332 .set noat 345 .set noat
346 SET_HARDFLOAT
333 /* move triggers an assembler bug... */ 347 /* move triggers an assembler bug... */
334 or $1, \rs, zero 348 or $1, \rs, zero
335 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) 349 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -339,6 +353,7 @@
339 .macro insert_d wd, n, rs 353 .macro insert_d wd, n, rs
340 .set push 354 .set push
341 .set noat 355 .set noat
356 SET_HARDFLOAT
342 /* move triggers an assembler bug... */ 357 /* move triggers an assembler bug... */
343 or $1, \rs, zero 358 or $1, \rs, zero
344 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) 359 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -381,6 +396,7 @@
381 st_d 31, THREAD_FPR31, \thread 396 st_d 31, THREAD_FPR31, \thread
382 .set push 397 .set push
383 .set noat 398 .set noat
399 SET_HARDFLOAT
384 cfcmsa $1, MSA_CSR 400 cfcmsa $1, MSA_CSR
385 sw $1, THREAD_MSA_CSR(\thread) 401 sw $1, THREAD_MSA_CSR(\thread)
386 .set pop 402 .set pop
@@ -389,6 +405,7 @@
389 .macro msa_restore_all thread 405 .macro msa_restore_all thread
390 .set push 406 .set push
391 .set noat 407 .set noat
408 SET_HARDFLOAT
392 lw $1, THREAD_MSA_CSR(\thread) 409 lw $1, THREAD_MSA_CSR(\thread)
393 ctcmsa MSA_CSR, $1 410 ctcmsa MSA_CSR, $1
394 .set pop 411 .set pop
@@ -441,6 +458,7 @@
441 .macro msa_init_all_upper 458 .macro msa_init_all_upper
442 .set push 459 .set push
443 .set noat 460 .set noat
461 SET_HARDFLOAT
444 not $1, zero 462 not $1, zero
445 msa_init_upper 0 463 msa_init_upper 0
446 .set pop 464 .set pop
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 51f80bd36fcc..63b3468ede4c 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -37,15 +37,15 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
37 37
38#define cop2_present 1 38#define cop2_present 1
39#define cop2_lazy_restore 1 39#define cop2_lazy_restore 1
40#define cop2_save(r) do { (r); } while (0) 40#define cop2_save(r) do { (void)(r); } while (0)
41#define cop2_restore(r) do { (r); } while (0) 41#define cop2_restore(r) do { (void)(r); } while (0)
42 42
43#else 43#else
44 44
45#define cop2_present 0 45#define cop2_present 0
46#define cop2_lazy_restore 0 46#define cop2_lazy_restore 0
47#define cop2_save(r) do { (r); } while (0) 47#define cop2_save(r) do { (void)(r); } while (0)
48#define cop2_restore(r) do { (r); } while (0) 48#define cop2_restore(r) do { (void)(r); } while (0)
49#endif 49#endif
50 50
51enum cu2_ops { 51enum cu2_ops {
diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
index 429481f9028d..f184ba088532 100644
--- a/arch/mips/include/asm/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
@@ -14,6 +14,20 @@
14 14
15#include <asm/sgidefs.h> 15#include <asm/sgidefs.h>
16 16
17/*
18 * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
19 * hardfloat and softfloat object files. The kernel build uses soft-float by
20 * default, so we also need to pass -msoft-float along to GAS if it supports it.
21 * But this in turn causes assembler errors in files which access hardfloat
22 * registers. We detect if GAS supports "-msoft-float" in the Makefile and
23 * explicitly put ".set hardfloat" where floating point registers are touched.
24 */
25#ifdef GAS_HAS_SET_HARDFLOAT
26#define SET_HARDFLOAT .set hardfloat
27#else
28#define SET_HARDFLOAT
29#endif
30
17#if _MIPS_SIM == _MIPS_SIM_ABI32 31#if _MIPS_SIM == _MIPS_SIM_ABI32
18 32
19/* 33/*
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 4d0aeda68397..dd562414cd5e 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -145,8 +145,8 @@ static inline void lose_fpu(int save)
145 if (is_msa_enabled()) { 145 if (is_msa_enabled()) {
146 if (save) { 146 if (save) {
147 save_msa(current); 147 save_msa(current);
148 asm volatile("cfc1 %0, $31" 148 current->thread.fpu.fcr31 =
149 : "=r"(current->thread.fpu.fcr31)); 149 read_32bit_cp1_register(CP1_STATUS);
150 } 150 }
151 disable_msa(); 151 disable_msa();
152 clear_thread_flag(TIF_USEDMSA); 152 clear_thread_flag(TIF_USEDMSA);
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 992aaba603b5..b463f2aa5a61 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -24,7 +24,7 @@ do { \
24 asm volatile ( \ 24 asm volatile ( \
25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \ 25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
26 " li %[tmp_err], 0\n" \ 26 " li %[tmp_err], 0\n" \
27 "2:\n" \ 27 "2: .insn\n" \
28 \ 28 \
29 ".section .fixup, \"ax\"\n" \ 29 ".section .fixup, \"ax\"\n" \
30 "3: li %[tmp_err], 1\n" \ 30 "3: li %[tmp_err], 1\n" \
@@ -46,7 +46,7 @@ do { \
46 asm volatile ( \ 46 asm volatile ( \
47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\ 47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
48 " li %[tmp_err], 0\n" \ 48 " li %[tmp_err], 0\n" \
49 "2:\n" \ 49 "2: .insn\n" \
50 \ 50 \
51 ".section .fixup, \"ax\"\n" \ 51 ".section .fixup, \"ax\"\n" \
52 "3: li %[tmp_err], 1\n" \ 52 "3: li %[tmp_err], 1\n" \
diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h
index d9f932de80e9..1c967abd545c 100644
--- a/arch/mips/include/asm/idle.h
+++ b/arch/mips/include/asm/idle.h
@@ -8,19 +8,12 @@ extern void (*cpu_wait)(void);
8extern void r4k_wait(void); 8extern void r4k_wait(void);
9extern asmlinkage void __r4k_wait(void); 9extern asmlinkage void __r4k_wait(void);
10extern void r4k_wait_irqoff(void); 10extern void r4k_wait_irqoff(void);
11extern void __pastwait(void);
12 11
13static inline int using_rollback_handler(void) 12static inline int using_rollback_handler(void)
14{ 13{
15 return cpu_wait == r4k_wait; 14 return cpu_wait == r4k_wait;
16} 15}
17 16
18static inline int address_is_in_r4k_wait_irqoff(unsigned long addr)
19{
20 return addr >= (unsigned long)r4k_wait_irqoff &&
21 addr < (unsigned long)__pastwait;
22}
23
24extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev, 17extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
25 struct cpuidle_driver *drv, int index); 18 struct cpuidle_driver *drv, int index);
26 19
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index cf3b580c3df6..b46cd220a018 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1324,7 +1324,7 @@ do { \
1324/* 1324/*
1325 * Macros to access the floating point coprocessor control registers 1325 * Macros to access the floating point coprocessor control registers
1326 */ 1326 */
1327#define read_32bit_cp1_register(source) \ 1327#define _read_32bit_cp1_register(source, gas_hardfloat) \
1328({ \ 1328({ \
1329 int __res; \ 1329 int __res; \
1330 \ 1330 \
@@ -1334,12 +1334,21 @@ do { \
1334 " # gas fails to assemble cfc1 for some archs, \n" \ 1334 " # gas fails to assemble cfc1 for some archs, \n" \
1335 " # like Octeon. \n" \ 1335 " # like Octeon. \n" \
1336 " .set mips1 \n" \ 1336 " .set mips1 \n" \
1337 " "STR(gas_hardfloat)" \n" \
1337 " cfc1 %0,"STR(source)" \n" \ 1338 " cfc1 %0,"STR(source)" \n" \
1338 " .set pop \n" \ 1339 " .set pop \n" \
1339 : "=r" (__res)); \ 1340 : "=r" (__res)); \
1340 __res; \ 1341 __res; \
1341}) 1342})
1342 1343
1344#ifdef GAS_HAS_SET_HARDFLOAT
1345#define read_32bit_cp1_register(source) \
1346 _read_32bit_cp1_register(source, .set hardfloat)
1347#else
1348#define read_32bit_cp1_register(source) \
1349 _read_32bit_cp1_register(source, )
1350#endif
1351
1343#ifdef HAVE_AS_DSP 1352#ifdef HAVE_AS_DSP
1344#define rddsp(mask) \ 1353#define rddsp(mask) \
1345({ \ 1354({ \
diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h
index bbcfb8ba8106..91a3d197ede3 100644
--- a/arch/mips/include/uapi/asm/ptrace.h
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -9,6 +9,8 @@
9#ifndef _UAPI_ASM_PTRACE_H 9#ifndef _UAPI_ASM_PTRACE_H
10#define _UAPI_ASM_PTRACE_H 10#define _UAPI_ASM_PTRACE_H
11 11
12#include <linux/types.h>
13
12/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ 14/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
13#define FPR_BASE 32 15#define FPR_BASE 32
14#define PC 64 16#define PC 64
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index fdb4923777d1..9dc58568f230 100644
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -375,16 +375,17 @@
375#define __NR_seccomp (__NR_Linux + 352) 375#define __NR_seccomp (__NR_Linux + 352)
376#define __NR_getrandom (__NR_Linux + 353) 376#define __NR_getrandom (__NR_Linux + 353)
377#define __NR_memfd_create (__NR_Linux + 354) 377#define __NR_memfd_create (__NR_Linux + 354)
378#define __NR_bpf (__NR_Linux + 355)
378 379
379/* 380/*
380 * Offset of the last Linux o32 flavoured syscall 381 * Offset of the last Linux o32 flavoured syscall
381 */ 382 */
382#define __NR_Linux_syscalls 354 383#define __NR_Linux_syscalls 355
383 384
384#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 385#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
385 386
386#define __NR_O32_Linux 4000 387#define __NR_O32_Linux 4000
387#define __NR_O32_Linux_syscalls 354 388#define __NR_O32_Linux_syscalls 355
388 389
389#if _MIPS_SIM == _MIPS_SIM_ABI64 390#if _MIPS_SIM == _MIPS_SIM_ABI64
390 391
@@ -707,16 +708,17 @@
707#define __NR_seccomp (__NR_Linux + 312) 708#define __NR_seccomp (__NR_Linux + 312)
708#define __NR_getrandom (__NR_Linux + 313) 709#define __NR_getrandom (__NR_Linux + 313)
709#define __NR_memfd_create (__NR_Linux + 314) 710#define __NR_memfd_create (__NR_Linux + 314)
711#define __NR_bpf (__NR_Linux + 315)
710 712
711/* 713/*
712 * Offset of the last Linux 64-bit flavoured syscall 714 * Offset of the last Linux 64-bit flavoured syscall
713 */ 715 */
714#define __NR_Linux_syscalls 314 716#define __NR_Linux_syscalls 315
715 717
716#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 718#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
717 719
718#define __NR_64_Linux 5000 720#define __NR_64_Linux 5000
719#define __NR_64_Linux_syscalls 314 721#define __NR_64_Linux_syscalls 315
720 722
721#if _MIPS_SIM == _MIPS_SIM_NABI32 723#if _MIPS_SIM == _MIPS_SIM_NABI32
722 724
@@ -1043,15 +1045,16 @@
1043#define __NR_seccomp (__NR_Linux + 316) 1045#define __NR_seccomp (__NR_Linux + 316)
1044#define __NR_getrandom (__NR_Linux + 317) 1046#define __NR_getrandom (__NR_Linux + 317)
1045#define __NR_memfd_create (__NR_Linux + 318) 1047#define __NR_memfd_create (__NR_Linux + 318)
1048#define __NR_memfd_create (__NR_Linux + 319)
1046 1049
1047/* 1050/*
1048 * Offset of the last N32 flavoured syscall 1051 * Offset of the last N32 flavoured syscall
1049 */ 1052 */
1050#define __NR_Linux_syscalls 318 1053#define __NR_Linux_syscalls 319
1051 1054
1052#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 1055#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1053 1056
1054#define __NR_N32_Linux 6000 1057#define __NR_N32_Linux 6000
1055#define __NR_N32_Linux_syscalls 318 1058#define __NR_N32_Linux_syscalls 319
1056 1059
1057#endif /* _UAPI_ASM_UNISTD_H */ 1060#endif /* _UAPI_ASM_UNISTD_H */
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 7b2df224f041..4d7d99d601cc 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -144,7 +144,7 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
144 case mm_bc1t_op: 144 case mm_bc1t_op:
145 preempt_disable(); 145 preempt_disable();
146 if (is_fpu_owner()) 146 if (is_fpu_owner())
147 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 147 fcr31 = read_32bit_cp1_register(CP1_STATUS);
148 else 148 else
149 fcr31 = current->thread.fpu.fcr31; 149 fcr31 = current->thread.fpu.fcr31;
150 preempt_enable(); 150 preempt_enable();
@@ -562,11 +562,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
562 case cop1_op: 562 case cop1_op:
563 preempt_disable(); 563 preempt_disable();
564 if (is_fpu_owner()) 564 if (is_fpu_owner())
565 asm volatile( 565 fcr31 = read_32bit_cp1_register(CP1_STATUS);
566 ".set push\n"
567 "\t.set mips1\n"
568 "\tcfc1\t%0,$31\n"
569 "\t.set pop" : "=r" (fcr31));
570 else 566 else
571 fcr31 = current->thread.fpu.fcr31; 567 fcr31 = current->thread.fpu.fcr31;
572 preempt_enable(); 568 preempt_enable();
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ac35e12cb1f3..a5e26dd90592 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -358,6 +358,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
358 .set push 358 .set push
359 /* gas fails to assemble cfc1 for some archs (octeon).*/ \ 359 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
360 .set mips1 360 .set mips1
361 SET_HARDFLOAT
361 cfc1 a1, fcr31 362 cfc1 a1, fcr31
362 li a2, ~(0x3f << 12) 363 li a2, ~(0x3f << 12)
363 and a2, a1 364 and a2, a1
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 09ce45980758..0b9082b6b683 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -68,9 +68,6 @@ void r4k_wait_irqoff(void)
68 " wait \n" 68 " wait \n"
69 " .set pop \n"); 69 " .set pop \n");
70 local_irq_enable(); 70 local_irq_enable();
71 __asm__(
72 " .globl __pastwait \n"
73 "__pastwait: \n");
74} 71}
75 72
76/* 73/*
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index f31063dbdaeb..5ce3b746cedc 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -28,6 +28,8 @@
28 .set mips1 28 .set mips1
29 /* Save floating point context */ 29 /* Save floating point context */
30LEAF(_save_fp_context) 30LEAF(_save_fp_context)
31 .set push
32 SET_HARDFLOAT
31 li v0, 0 # assume success 33 li v0, 0 # assume success
32 cfc1 t1,fcr31 34 cfc1 t1,fcr31
33 EX(swc1 $f0,(SC_FPREGS+0)(a0)) 35 EX(swc1 $f0,(SC_FPREGS+0)(a0))
@@ -65,6 +67,7 @@ LEAF(_save_fp_context)
65 EX(sw t1,(SC_FPC_CSR)(a0)) 67 EX(sw t1,(SC_FPC_CSR)(a0))
66 cfc1 t0,$0 # implementation/version 68 cfc1 t0,$0 # implementation/version
67 jr ra 69 jr ra
70 .set pop
68 .set nomacro 71 .set nomacro
69 EX(sw t0,(SC_FPC_EIR)(a0)) 72 EX(sw t0,(SC_FPC_EIR)(a0))
70 .set macro 73 .set macro
@@ -80,6 +83,8 @@ LEAF(_save_fp_context)
80 * stack frame which might have been changed by the user. 83 * stack frame which might have been changed by the user.
81 */ 84 */
82LEAF(_restore_fp_context) 85LEAF(_restore_fp_context)
86 .set push
87 SET_HARDFLOAT
83 li v0, 0 # assume success 88 li v0, 0 # assume success
84 EX(lw t0,(SC_FPC_CSR)(a0)) 89 EX(lw t0,(SC_FPC_CSR)(a0))
85 EX(lwc1 $f0,(SC_FPREGS+0)(a0)) 90 EX(lwc1 $f0,(SC_FPREGS+0)(a0))
@@ -116,6 +121,7 @@ LEAF(_restore_fp_context)
116 EX(lwc1 $f31,(SC_FPREGS+248)(a0)) 121 EX(lwc1 $f31,(SC_FPREGS+248)(a0))
117 jr ra 122 jr ra
118 ctc1 t0,fcr31 123 ctc1 t0,fcr31
124 .set pop
119 END(_restore_fp_context) 125 END(_restore_fp_context)
120 .set reorder 126 .set reorder
121 127
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 20b7b040e76f..435ea652f5fa 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -120,6 +120,9 @@ LEAF(_restore_fp)
120 120
121#define FPU_DEFAULT 0x00000000 121#define FPU_DEFAULT 0x00000000
122 122
123 .set push
124 SET_HARDFLOAT
125
123LEAF(_init_fpu) 126LEAF(_init_fpu)
124 mfc0 t0, CP0_STATUS 127 mfc0 t0, CP0_STATUS
125 li t1, ST0_CU1 128 li t1, ST0_CU1
@@ -165,3 +168,5 @@ LEAF(_init_fpu)
165 mtc1 t0, $f31 168 mtc1 t0, $f31
166 jr ra 169 jr ra
167 END(_init_fpu) 170 END(_init_fpu)
171
172 .set pop
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 8352523568e6..6c160c67984c 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -19,8 +19,12 @@
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/regdef.h> 20#include <asm/regdef.h>
21 21
22/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
23#undef fp
24
22 .macro EX insn, reg, src 25 .macro EX insn, reg, src
23 .set push 26 .set push
27 SET_HARDFLOAT
24 .set nomacro 28 .set nomacro
25.ex\@: \insn \reg, \src 29.ex\@: \insn \reg, \src
26 .set pop 30 .set pop
@@ -33,12 +37,17 @@
33 .set arch=r4000 37 .set arch=r4000
34 38
35LEAF(_save_fp_context) 39LEAF(_save_fp_context)
40 .set push
41 SET_HARDFLOAT
36 cfc1 t1, fcr31 42 cfc1 t1, fcr31
43 .set pop
37 44
38#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 45#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
39 .set push 46 .set push
47 SET_HARDFLOAT
40#ifdef CONFIG_CPU_MIPS32_R2 48#ifdef CONFIG_CPU_MIPS32_R2
41 .set mips64r2 49 .set mips32r2
50 .set fp=64
42 mfc0 t0, CP0_STATUS 51 mfc0 t0, CP0_STATUS
43 sll t0, t0, 5 52 sll t0, t0, 5
44 bgez t0, 1f # skip storing odd if FR=0 53 bgez t0, 1f # skip storing odd if FR=0
@@ -64,6 +73,8 @@ LEAF(_save_fp_context)
641: .set pop 731: .set pop
65#endif 74#endif
66 75
76 .set push
77 SET_HARDFLOAT
67 /* Store the 16 even double precision registers */ 78 /* Store the 16 even double precision registers */
68 EX sdc1 $f0, SC_FPREGS+0(a0) 79 EX sdc1 $f0, SC_FPREGS+0(a0)
69 EX sdc1 $f2, SC_FPREGS+16(a0) 80 EX sdc1 $f2, SC_FPREGS+16(a0)
@@ -84,11 +95,14 @@ LEAF(_save_fp_context)
84 EX sw t1, SC_FPC_CSR(a0) 95 EX sw t1, SC_FPC_CSR(a0)
85 jr ra 96 jr ra
86 li v0, 0 # success 97 li v0, 0 # success
98 .set pop
87 END(_save_fp_context) 99 END(_save_fp_context)
88 100
89#ifdef CONFIG_MIPS32_COMPAT 101#ifdef CONFIG_MIPS32_COMPAT
90 /* Save 32-bit process floating point context */ 102 /* Save 32-bit process floating point context */
91LEAF(_save_fp_context32) 103LEAF(_save_fp_context32)
104 .set push
105 SET_HARDFLOAT
92 cfc1 t1, fcr31 106 cfc1 t1, fcr31
93 107
94 mfc0 t0, CP0_STATUS 108 mfc0 t0, CP0_STATUS
@@ -134,6 +148,7 @@ LEAF(_save_fp_context32)
134 EX sw t1, SC32_FPC_CSR(a0) 148 EX sw t1, SC32_FPC_CSR(a0)
135 cfc1 t0, $0 # implementation/version 149 cfc1 t0, $0 # implementation/version
136 EX sw t0, SC32_FPC_EIR(a0) 150 EX sw t0, SC32_FPC_EIR(a0)
151 .set pop
137 152
138 jr ra 153 jr ra
139 li v0, 0 # success 154 li v0, 0 # success
@@ -150,8 +165,10 @@ LEAF(_restore_fp_context)
150 165
151#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 166#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
152 .set push 167 .set push
168 SET_HARDFLOAT
153#ifdef CONFIG_CPU_MIPS32_R2 169#ifdef CONFIG_CPU_MIPS32_R2
154 .set mips64r2 170 .set mips32r2
171 .set fp=64
155 mfc0 t0, CP0_STATUS 172 mfc0 t0, CP0_STATUS
156 sll t0, t0, 5 173 sll t0, t0, 5
157 bgez t0, 1f # skip loading odd if FR=0 174 bgez t0, 1f # skip loading odd if FR=0
@@ -175,6 +192,8 @@ LEAF(_restore_fp_context)
175 EX ldc1 $f31, SC_FPREGS+248(a0) 192 EX ldc1 $f31, SC_FPREGS+248(a0)
1761: .set pop 1931: .set pop
177#endif 194#endif
195 .set push
196 SET_HARDFLOAT
178 EX ldc1 $f0, SC_FPREGS+0(a0) 197 EX ldc1 $f0, SC_FPREGS+0(a0)
179 EX ldc1 $f2, SC_FPREGS+16(a0) 198 EX ldc1 $f2, SC_FPREGS+16(a0)
180 EX ldc1 $f4, SC_FPREGS+32(a0) 199 EX ldc1 $f4, SC_FPREGS+32(a0)
@@ -192,6 +211,7 @@ LEAF(_restore_fp_context)
192 EX ldc1 $f28, SC_FPREGS+224(a0) 211 EX ldc1 $f28, SC_FPREGS+224(a0)
193 EX ldc1 $f30, SC_FPREGS+240(a0) 212 EX ldc1 $f30, SC_FPREGS+240(a0)
194 ctc1 t1, fcr31 213 ctc1 t1, fcr31
214 .set pop
195 jr ra 215 jr ra
196 li v0, 0 # success 216 li v0, 0 # success
197 END(_restore_fp_context) 217 END(_restore_fp_context)
@@ -199,6 +219,8 @@ LEAF(_restore_fp_context)
199#ifdef CONFIG_MIPS32_COMPAT 219#ifdef CONFIG_MIPS32_COMPAT
200LEAF(_restore_fp_context32) 220LEAF(_restore_fp_context32)
201 /* Restore an o32 sigcontext. */ 221 /* Restore an o32 sigcontext. */
222 .set push
223 SET_HARDFLOAT
202 EX lw t1, SC32_FPC_CSR(a0) 224 EX lw t1, SC32_FPC_CSR(a0)
203 225
204 mfc0 t0, CP0_STATUS 226 mfc0 t0, CP0_STATUS
@@ -242,6 +264,7 @@ LEAF(_restore_fp_context32)
242 ctc1 t1, fcr31 264 ctc1 t1, fcr31
243 jr ra 265 jr ra
244 li v0, 0 # success 266 li v0, 0 # success
267 .set pop
245 END(_restore_fp_context32) 268 END(_restore_fp_context32)
246#endif 269#endif
247 270
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 4c4ec1812420..64591e671878 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -22,6 +22,9 @@
22 22
23#include <asm/asmmacro.h> 23#include <asm/asmmacro.h>
24 24
25/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
26#undef fp
27
25/* 28/*
26 * Offset to the current process status flags, the first 32 bytes of the 29 * Offset to the current process status flags, the first 32 bytes of the
27 * stack are not used. 30 * stack are not used.
@@ -65,8 +68,12 @@
65 bgtz a3, 1f 68 bgtz a3, 1f
66 69
67 /* Save 128b MSA vector context + scalar FP control & status. */ 70 /* Save 128b MSA vector context + scalar FP control & status. */
71 .set push
72 SET_HARDFLOAT
68 cfc1 t1, fcr31 73 cfc1 t1, fcr31
69 msa_save_all a0 74 msa_save_all a0
75 .set pop /* SET_HARDFLOAT */
76
70 sw t1, THREAD_FCR31(a0) 77 sw t1, THREAD_FCR31(a0)
71 b 2f 78 b 2f
72 79
@@ -161,6 +168,9 @@ LEAF(_init_msa_upper)
161 168
162#define FPU_DEFAULT 0x00000000 169#define FPU_DEFAULT 0x00000000
163 170
171 .set push
172 SET_HARDFLOAT
173
164LEAF(_init_fpu) 174LEAF(_init_fpu)
165 mfc0 t0, CP0_STATUS 175 mfc0 t0, CP0_STATUS
166 li t1, ST0_CU1 176 li t1, ST0_CU1
@@ -232,7 +242,8 @@ LEAF(_init_fpu)
232 242
233#ifdef CONFIG_CPU_MIPS32_R2 243#ifdef CONFIG_CPU_MIPS32_R2
234 .set push 244 .set push
235 .set mips64r2 245 .set mips32r2
246 .set fp=64
236 sll t0, t0, 5 # is Status.FR set? 247 sll t0, t0, 5 # is Status.FR set?
237 bgez t0, 1f # no: skip setting upper 32b 248 bgez t0, 1f # no: skip setting upper 32b
238 249
@@ -291,3 +302,5 @@ LEAF(_init_fpu)
291#endif 302#endif
292 jr ra 303 jr ra
293 END(_init_fpu) 304 END(_init_fpu)
305
306 .set pop /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
index da0fbe46d83b..47077380c15c 100644
--- a/arch/mips/kernel/r6000_fpu.S
+++ b/arch/mips/kernel/r6000_fpu.S
@@ -18,6 +18,9 @@
18 18
19 .set noreorder 19 .set noreorder
20 .set mips2 20 .set mips2
21 .set push
22 SET_HARDFLOAT
23
21 /* Save floating point context */ 24 /* Save floating point context */
22 LEAF(_save_fp_context) 25 LEAF(_save_fp_context)
23 mfc0 t0,CP0_STATUS 26 mfc0 t0,CP0_STATUS
@@ -85,3 +88,5 @@
851: jr ra 881: jr ra
86 nop 89 nop
87 END(_restore_fp_context) 90 END(_restore_fp_context)
91
92 .set pop /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 744cd10ba599..00cad1005a16 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -579,3 +579,4 @@ EXPORT(sys_call_table)
579 PTR sys_seccomp 579 PTR sys_seccomp
580 PTR sys_getrandom 580 PTR sys_getrandom
581 PTR sys_memfd_create 581 PTR sys_memfd_create
582 PTR sys_bpf /* 4355 */
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 002b1bc09c38..5251565e344b 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -434,4 +434,5 @@ EXPORT(sys_call_table)
434 PTR sys_seccomp 434 PTR sys_seccomp
435 PTR sys_getrandom 435 PTR sys_getrandom
436 PTR sys_memfd_create 436 PTR sys_memfd_create
437 PTR sys_bpf /* 5315 */
437 .size sys_call_table,.-sys_call_table 438 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index ca6cbbe9805b..77e74398b828 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -427,4 +427,5 @@ EXPORT(sysn32_call_table)
427 PTR sys_seccomp 427 PTR sys_seccomp
428 PTR sys_getrandom 428 PTR sys_getrandom
429 PTR sys_memfd_create 429 PTR sys_memfd_create
430 PTR sys_bpf
430 .size sysn32_call_table,.-sysn32_call_table 431 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9e10d11fbb84..6f8db9f728e8 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -564,4 +564,5 @@ EXPORT(sys32_call_table)
564 PTR sys_seccomp 564 PTR sys_seccomp
565 PTR sys_getrandom 565 PTR sys_getrandom
566 PTR sys_memfd_create 566 PTR sys_memfd_create
567 PTR sys_bpf /* 4355 */
567 .size sys32_call_table,.-sys32_call_table 568 .size sys32_call_table,.-sys32_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index b3b8f0d9d4a7..d21ec57b6e95 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -683,7 +683,8 @@ static void __init arch_mem_init(char **cmdline_p)
683 dma_contiguous_reserve(PFN_PHYS(max_low_pfn)); 683 dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
684 /* Tell bootmem about cma reserved memblock section */ 684 /* Tell bootmem about cma reserved memblock section */
685 for_each_memblock(reserved, reg) 685 for_each_memblock(reserved, reg)
686 reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT); 686 if (reg->size != 0)
687 reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
687} 688}
688 689
689static void __init resource_init(void) 690static void __init resource_init(void)
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
index 1d2ee8a9be13..8776d0a34274 100644
--- a/arch/mips/lasat/Kconfig
+++ b/arch/mips/lasat/Kconfig
@@ -4,7 +4,7 @@ config PICVUE
4 4
5config PICVUE_PROC 5config PICVUE_PROC
6 tristate "PICVUE LCD display driver /proc interface" 6 tristate "PICVUE LCD display driver /proc interface"
7 depends on PICVUE 7 depends on PICVUE && PROC_FS
8 8
9config DS1603 9config DS1603
10 bool "DS1603 RTC driver" 10 bool "DS1603 RTC driver"
diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c
index 91615c2ef0cf..1ef365ab3cd3 100644
--- a/arch/mips/lib/r3k_dump_tlb.c
+++ b/arch/mips/lib/r3k_dump_tlb.c
@@ -34,7 +34,7 @@ static void dump_tlb(int first, int last)
34 entrylo0 = read_c0_entrylo0(); 34 entrylo0 = read_c0_entrylo0();
35 35
36 /* Unused entries have a virtual address of KSEG0. */ 36 /* Unused entries have a virtual address of KSEG0. */
37 if ((entryhi & 0xffffe000) != 0x80000000 37 if ((entryhi & 0xfffff000) != 0x80000000
38 && (entryhi & 0xfc0) == asid) { 38 && (entryhi & 0xfc0) == asid) {
39 /* 39 /*
40 * Only print entries in use 40 * Only print entries in use
@@ -43,7 +43,7 @@ static void dump_tlb(int first, int last)
43 43
44 printk("va=%08lx asid=%08lx" 44 printk("va=%08lx asid=%08lx"
45 " [pa=%06lx n=%d d=%d v=%d g=%d]", 45 " [pa=%06lx n=%d d=%d v=%d g=%d]",
46 (entryhi & 0xffffe000), 46 (entryhi & 0xfffff000),
47 entryhi & 0xfc0, 47 entryhi & 0xfc0,
48 entrylo0 & PAGE_MASK, 48 entrylo0 & PAGE_MASK,
49 (entrylo0 & (1 << 11)) ? 1 : 0, 49 (entrylo0 & (1 << 11)) ? 1 : 0,
diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S
index f3af6995e2a6..7d12c0dded3d 100644
--- a/arch/mips/lib/strnlen_user.S
+++ b/arch/mips/lib/strnlen_user.S
@@ -40,9 +40,11 @@ FEXPORT(__strnlen_\func\()_nocheck_asm)
40.else 40.else
41 EX(lbe, t0, (v0), .Lfault\@) 41 EX(lbe, t0, (v0), .Lfault\@)
42.endif 42.endif
43 PTR_ADDIU v0, 1 43 .set noreorder
44 bnez t0, 1b 44 bnez t0, 1b
451: PTR_SUBU v0, a0 451: PTR_ADDIU v0, 1
46 .set reorder
47 PTR_SUBU v0, a0
46 jr ra 48 jr ra
47 END(__strnlen_\func\()_asm) 49 END(__strnlen_\func\()_asm)
48 50
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index a217061beee3..462e34d46b4a 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);
91 91
92int clk_set_rate(struct clk *clk, unsigned long rate) 92int clk_set_rate(struct clk *clk, unsigned long rate)
93{ 93{
94 unsigned int rate_khz = rate / 1000;
94 struct cpufreq_frequency_table *pos; 95 struct cpufreq_frequency_table *pos;
95 int ret = 0; 96 int ret = 0;
96 int regval; 97 int regval;
@@ -107,9 +108,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
107 propagate_rate(clk); 108 propagate_rate(clk);
108 109
109 cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table) 110 cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
110 if (rate == pos->frequency) 111 if (rate_khz == pos->frequency)
111 break; 112 break;
112 if (rate != pos->frequency) 113 if (rate_khz != pos->frequency)
113 return -ENOTSUPP; 114 return -ENOTSUPP;
114 115
115 clk->rate = rate; 116 clk->rate = rate;
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 7a4727795a70..cac529a405b8 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -584,11 +584,7 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
584 if (insn.i_format.rs == bc_op) { 584 if (insn.i_format.rs == bc_op) {
585 preempt_disable(); 585 preempt_disable();
586 if (is_fpu_owner()) 586 if (is_fpu_owner())
587 asm volatile( 587 fcr31 = read_32bit_cp1_register(CP1_STATUS);
588 ".set push\n"
589 "\t.set mips1\n"
590 "\tcfc1\t%0,$31\n"
591 "\t.set pop" : "=r" (fcr31));
592 else 588 else
593 fcr31 = current->thread.fpu.fcr31; 589 fcr31 = current->thread.fpu.fcr31;
594 preempt_enable(); 590 preempt_enable();
@@ -1023,7 +1019,7 @@ emul:
1023 goto emul; 1019 goto emul;
1024 1020
1025 case cop1x_op: 1021 case cop1x_op:
1026 if (cpu_has_mips_4_5 || cpu_has_mips64) 1022 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1027 /* its one of ours */ 1023 /* its one of ours */
1028 goto emul; 1024 goto emul;
1029 1025
@@ -1068,7 +1064,7 @@ emul:
1068 break; 1064 break;
1069 1065
1070 case cop1x_op: 1066 case cop1x_op:
1071 if (!cpu_has_mips_4_5 && !cpu_has_mips64) 1067 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1072 return SIGILL; 1068 return SIGILL;
1073 1069
1074 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1070 sig = fpux_emu(xcp, ctx, ir, fault_addr);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a08dd53a1cc5..b5f228e7eae6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1062,6 +1062,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1062struct mips_huge_tlb_info { 1062struct mips_huge_tlb_info {
1063 int huge_pte; 1063 int huge_pte;
1064 int restore_scratch; 1064 int restore_scratch;
1065 bool need_reload_pte;
1065}; 1066};
1066 1067
1067static struct mips_huge_tlb_info 1068static struct mips_huge_tlb_info
@@ -1076,6 +1077,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1076 1077
1077 rv.huge_pte = scratch; 1078 rv.huge_pte = scratch;
1078 rv.restore_scratch = 0; 1079 rv.restore_scratch = 0;
1080 rv.need_reload_pte = false;
1079 1081
1080 if (check_for_high_segbits) { 1082 if (check_for_high_segbits) {
1081 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1083 UASM_i_MFC0(p, tmp, C0_BADVADDR);
@@ -1264,6 +1266,7 @@ static void build_r4000_tlb_refill_handler(void)
1264 } else { 1266 } else {
1265 htlb_info.huge_pte = K0; 1267 htlb_info.huge_pte = K0;
1266 htlb_info.restore_scratch = 0; 1268 htlb_info.restore_scratch = 0;
1269 htlb_info.need_reload_pte = true;
1267 vmalloc_mode = refill_noscratch; 1270 vmalloc_mode = refill_noscratch;
1268 /* 1271 /*
1269 * create the plain linear handler 1272 * create the plain linear handler
@@ -1300,7 +1303,8 @@ static void build_r4000_tlb_refill_handler(void)
1300 } 1303 }
1301#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1304#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1302 uasm_l_tlb_huge_update(&l, p); 1305 uasm_l_tlb_huge_update(&l, p);
1303 UASM_i_LW(&p, K0, 0, K1); 1306 if (htlb_info.need_reload_pte)
1307 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1304 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1308 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1305 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1309 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1306 htlb_info.restore_scratch); 1310 htlb_info.restore_scratch);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index b9510ea8db56..6510ace272d4 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -5,8 +5,9 @@
5# Copyright (C) 2008 Wind River Systems, Inc. 5# Copyright (C) 2008 Wind River Systems, Inc.
6# written by Ralf Baechle <ralf@linux-mips.org> 6# written by Ralf Baechle <ralf@linux-mips.org>
7# 7#
8obj-y := malta-amon.o malta-display.o malta-init.o \ 8obj-y := malta-display.o malta-init.o \
9 malta-int.o malta-memory.o malta-platform.o \ 9 malta-int.o malta-memory.o malta-platform.o \
10 malta-reset.o malta-setup.o malta-time.o 10 malta-reset.o malta-setup.o malta-time.o
11 11
12obj-$(CONFIG_MIPS_CMP) += malta-amon.o
12obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o 13obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
index febf4334545e..2ae49e99eb67 100644
--- a/arch/mips/mti-sead3/Makefile
+++ b/arch/mips/mti-sead3/Makefile
@@ -14,7 +14,6 @@ obj-y := sead3-lcd.o sead3-display.o sead3-init.o \
14 sead3-setup.o sead3-time.o 14 sead3-setup.o sead3-time.o
15 15
16obj-y += sead3-i2c-dev.o sead3-i2c.o \ 16obj-y += sead3-i2c-dev.o sead3-i2c.o \
17 sead3-pic32-i2c-drv.o sead3-pic32-bus.o \
18 leds-sead3.o sead3-leds.o 17 leds-sead3.o sead3-leds.o
19 18
20obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o 19obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o
diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c
index f70d5fc58ef5..795ae83894e0 100644
--- a/arch/mips/mti-sead3/sead3-i2c.c
+++ b/arch/mips/mti-sead3/sead3-i2c.c
@@ -5,10 +5,8 @@
5 * 5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */ 7 */
8#include <linux/module.h>
9#include <linux/init.h> 8#include <linux/init.h>
10#include <linux/platform_device.h> 9#include <linux/platform_device.h>
11#include <irq.h>
12 10
13struct resource sead3_i2c_resources[] = { 11struct resource sead3_i2c_resources[] = {
14 { 12 {
@@ -30,8 +28,4 @@ static int __init sead3_i2c_init(void)
30 return platform_device_register(&sead3_i2c_device); 28 return platform_device_register(&sead3_i2c_device);
31} 29}
32 30
33module_init(sead3_i2c_init); 31device_initcall(sead3_i2c_init);
34
35MODULE_AUTHOR("Chris Dearman <chris@mips.com>");
36MODULE_LICENSE("GPL");
37MODULE_DESCRIPTION("I2C probe driver for SEAD3");
diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c
deleted file mode 100644
index 3b12aa5a7c88..000000000000
--- a/arch/mips/mti-sead3/sead3-pic32-bus.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/spinlock.h>
11#include <linux/io.h>
12#include <linux/errno.h>
13
14#define PIC32_NULL 0x00
15#define PIC32_RD 0x01
16#define PIC32_SYSRD 0x02
17#define PIC32_WR 0x10
18#define PIC32_SYSWR 0x20
19#define PIC32_IRQ_CLR 0x40
20#define PIC32_STATUS 0x80
21
22#define DELAY() udelay(100) /* FIXME: needed? */
23
24/* spinlock to ensure atomic access to PIC32 */
25static DEFINE_SPINLOCK(pic32_bus_lock);
26
27/* FIXME: io_remap these */
28static void __iomem *bus_xfer = (void __iomem *)0xbf000600;
29static void __iomem *bus_status = (void __iomem *)0xbf000060;
30
31static inline unsigned int ioready(void)
32{
33 return readl(bus_status) & 1;
34}
35
36static inline void wait_ioready(void)
37{
38 do { } while (!ioready());
39}
40
41static inline void wait_ioclear(void)
42{
43 do { } while (ioready());
44}
45
46static inline void check_ioclear(void)
47{
48 if (ioready()) {
49 pr_debug("ioclear: initially busy\n");
50 do {
51 (void) readl(bus_xfer);
52 DELAY();
53 } while (ioready());
54 pr_debug("ioclear: cleared busy\n");
55 }
56}
57
58u32 pic32_bus_readl(u32 reg)
59{
60 unsigned long flags;
61 u32 status, val;
62
63 spin_lock_irqsave(&pic32_bus_lock, flags);
64
65 check_ioclear();
66
67 writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer);
68 DELAY();
69 wait_ioready();
70 status = readl(bus_xfer);
71 DELAY();
72 val = readl(bus_xfer);
73 wait_ioclear();
74
75 pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status);
76
77 spin_unlock_irqrestore(&pic32_bus_lock, flags);
78
79 return val;
80}
81
82void pic32_bus_writel(u32 val, u32 reg)
83{
84 unsigned long flags;
85 u32 status;
86
87 spin_lock_irqsave(&pic32_bus_lock, flags);
88
89 check_ioclear();
90
91 writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer);
92 DELAY();
93 writel(val, bus_xfer);
94 DELAY();
95 wait_ioready();
96 status = readl(bus_xfer);
97 wait_ioclear();
98
99 pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status);
100
101 spin_unlock_irqrestore(&pic32_bus_lock, flags);
102}
diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
deleted file mode 100644
index 80fe194cfa53..000000000000
--- a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
+++ /dev/null
@@ -1,423 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/spinlock.h>
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/errno.h>
15#include <linux/i2c.h>
16#include <linux/slab.h>
17
18#define PIC32_I2CxCON 0x0000
19#define PIC32_I2CxCONCLR 0x0004
20#define PIC32_I2CxCONSET 0x0008
21#define PIC32_I2CxCONINV 0x000C
22#define I2CCON_ON (1<<15)
23#define I2CCON_FRZ (1<<14)
24#define I2CCON_SIDL (1<<13)
25#define I2CCON_SCLREL (1<<12)
26#define I2CCON_STRICT (1<<11)
27#define I2CCON_A10M (1<<10)
28#define I2CCON_DISSLW (1<<9)
29#define I2CCON_SMEN (1<<8)
30#define I2CCON_GCEN (1<<7)
31#define I2CCON_STREN (1<<6)
32#define I2CCON_ACKDT (1<<5)
33#define I2CCON_ACKEN (1<<4)
34#define I2CCON_RCEN (1<<3)
35#define I2CCON_PEN (1<<2)
36#define I2CCON_RSEN (1<<1)
37#define I2CCON_SEN (1<<0)
38
39#define PIC32_I2CxSTAT 0x0010
40#define PIC32_I2CxSTATCLR 0x0014
41#define PIC32_I2CxSTATSET 0x0018
42#define PIC32_I2CxSTATINV 0x001C
43#define I2CSTAT_ACKSTAT (1<<15)
44#define I2CSTAT_TRSTAT (1<<14)
45#define I2CSTAT_BCL (1<<10)
46#define I2CSTAT_GCSTAT (1<<9)
47#define I2CSTAT_ADD10 (1<<8)
48#define I2CSTAT_IWCOL (1<<7)
49#define I2CSTAT_I2COV (1<<6)
50#define I2CSTAT_DA (1<<5)
51#define I2CSTAT_P (1<<4)
52#define I2CSTAT_S (1<<3)
53#define I2CSTAT_RW (1<<2)
54#define I2CSTAT_RBF (1<<1)
55#define I2CSTAT_TBF (1<<0)
56
57#define PIC32_I2CxADD 0x0020
58#define PIC32_I2CxADDCLR 0x0024
59#define PIC32_I2CxADDSET 0x0028
60#define PIC32_I2CxADDINV 0x002C
61#define PIC32_I2CxMSK 0x0030
62#define PIC32_I2CxMSKCLR 0x0034
63#define PIC32_I2CxMSKSET 0x0038
64#define PIC32_I2CxMSKINV 0x003C
65#define PIC32_I2CxBRG 0x0040
66#define PIC32_I2CxBRGCLR 0x0044
67#define PIC32_I2CxBRGSET 0x0048
68#define PIC32_I2CxBRGINV 0x004C
69#define PIC32_I2CxTRN 0x0050
70#define PIC32_I2CxTRNCLR 0x0054
71#define PIC32_I2CxTRNSET 0x0058
72#define PIC32_I2CxTRNINV 0x005C
73#define PIC32_I2CxRCV 0x0060
74
75struct i2c_platform_data {
76 u32 base;
77 struct i2c_adapter adap;
78 u32 xfer_timeout;
79 u32 ack_timeout;
80 u32 ctl_timeout;
81};
82
83extern u32 pic32_bus_readl(u32 reg);
84extern void pic32_bus_writel(u32 val, u32 reg);
85
86static inline void
87StartI2C(struct i2c_platform_data *adap)
88{
89 pr_debug("StartI2C\n");
90 pic32_bus_writel(I2CCON_SEN, adap->base + PIC32_I2CxCONSET);
91}
92
93static inline void
94StopI2C(struct i2c_platform_data *adap)
95{
96 pr_debug("StopI2C\n");
97 pic32_bus_writel(I2CCON_PEN, adap->base + PIC32_I2CxCONSET);
98}
99
100static inline void
101AckI2C(struct i2c_platform_data *adap)
102{
103 pr_debug("AckI2C\n");
104 pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR);
105 pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
106}
107
108static inline void
109NotAckI2C(struct i2c_platform_data *adap)
110{
111 pr_debug("NakI2C\n");
112 pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET);
113 pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
114}
115
116static inline int
117IdleI2C(struct i2c_platform_data *adap)
118{
119 int i;
120
121 pr_debug("IdleI2C\n");
122 for (i = 0; i < adap->ctl_timeout; i++) {
123 if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) &
124 (I2CCON_ACKEN | I2CCON_RCEN | I2CCON_PEN | I2CCON_RSEN |
125 I2CCON_SEN)) == 0) &&
126 ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
127 (I2CSTAT_TRSTAT)) == 0))
128 return 0;
129 udelay(1);
130 }
131 return -ETIMEDOUT;
132}
133
134static inline u32
135MasterWriteI2C(struct i2c_platform_data *adap, u32 byte)
136{
137 pr_debug("MasterWriteI2C\n");
138
139 pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN);
140
141 return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_IWCOL;
142}
143
144static inline u32
145MasterReadI2C(struct i2c_platform_data *adap)
146{
147 pr_debug("MasterReadI2C\n");
148
149 pic32_bus_writel(I2CCON_RCEN, adap->base + PIC32_I2CxCONSET);
150
151 while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & I2CCON_RCEN)
152 ;
153
154 pic32_bus_writel(I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR);
155
156 return pic32_bus_readl(adap->base + PIC32_I2CxRCV);
157}
158
159static int
160do_address(struct i2c_platform_data *adap, unsigned int addr, int rd)
161{
162 pr_debug("doaddress\n");
163
164 IdleI2C(adap);
165 StartI2C(adap);
166 IdleI2C(adap);
167
168 addr <<= 1;
169 if (rd)
170 addr |= 1;
171
172 if (MasterWriteI2C(adap, addr))
173 return -EIO;
174 IdleI2C(adap);
175 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT)
176 return -EIO;
177 return 0;
178}
179
180static int
181i2c_read(struct i2c_platform_data *adap, unsigned char *buf,
182 unsigned int len)
183{
184 int i;
185 u32 data;
186
187 pr_debug("i2c_read\n");
188
189 i = 0;
190 while (i < len) {
191 data = MasterReadI2C(adap);
192 buf[i++] = data;
193 if (i < len)
194 AckI2C(adap);
195 else
196 NotAckI2C(adap);
197 }
198
199 StopI2C(adap);
200 IdleI2C(adap);
201 return 0;
202}
203
204static int
205i2c_write(struct i2c_platform_data *adap, unsigned char *buf,
206 unsigned int len)
207{
208 int i;
209 u32 data;
210
211 pr_debug("i2c_write\n");
212
213 i = 0;
214 while (i < len) {
215 data = buf[i];
216 if (MasterWriteI2C(adap, data))
217 return -EIO;
218 IdleI2C(adap);
219 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
220 I2CSTAT_ACKSTAT)
221 return -EIO;
222 i++;
223 }
224
225 StopI2C(adap);
226 IdleI2C(adap);
227 return 0;
228}
229
230static int
231platform_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
232{
233 struct i2c_platform_data *adap = i2c_adap->algo_data;
234 struct i2c_msg *p;
235 int i, err = 0;
236
237 pr_debug("platform_xfer\n");
238 for (i = 0; i < num; i++) {
239#define __BUFSIZE 80
240 int ii;
241 static char buf[__BUFSIZE];
242 char *b = buf;
243
244 p = &msgs[i];
245 b += sprintf(buf, " [%d bytes]", p->len);
246 if ((p->flags & I2C_M_RD) == 0) {
247 for (ii = 0; ii < p->len; ii++) {
248 if (b < &buf[__BUFSIZE-4]) {
249 b += sprintf(b, " %02x", p->buf[ii]);
250 } else {
251 strcat(b, "...");
252 break;
253 }
254 }
255 }
256 pr_debug("xfer%d: DevAddr: %04x Op:%s Data:%s\n", i, p->addr,
257 (p->flags & I2C_M_RD) ? "Rd" : "Wr", buf);
258 }
259
260
261 for (i = 0; !err && i < num; i++) {
262 p = &msgs[i];
263 err = do_address(adap, p->addr, p->flags & I2C_M_RD);
264 if (err || !p->len)
265 continue;
266 if (p->flags & I2C_M_RD)
267 err = i2c_read(adap, p->buf, p->len);
268 else
269 err = i2c_write(adap, p->buf, p->len);
270 }
271
272 /* Return the number of messages processed, or the error code. */
273 if (err == 0)
274 err = num;
275
276 return err;
277}
278
279static u32
280platform_func(struct i2c_adapter *adap)
281{
282 pr_debug("platform_algo\n");
283 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
284}
285
286static const struct i2c_algorithm platform_algo = {
287 .master_xfer = platform_xfer,
288 .functionality = platform_func,
289};
290
291static void i2c_platform_setup(struct i2c_platform_data *priv)
292{
293 pr_debug("i2c_platform_setup\n");
294
295 pic32_bus_writel(500, priv->base + PIC32_I2CxBRG);
296 pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONCLR);
297 pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONSET);
298 pic32_bus_writel((I2CSTAT_BCL | I2CSTAT_IWCOL),
299 (priv->base + PIC32_I2CxSTATCLR));
300}
301
302static void i2c_platform_disable(struct i2c_platform_data *priv)
303{
304 pr_debug("i2c_platform_disable\n");
305}
306
307static int i2c_platform_probe(struct platform_device *pdev)
308{
309 struct i2c_platform_data *priv;
310 struct resource *r;
311 int ret;
312
313 pr_debug("i2c_platform_probe\n");
314 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
315 if (!r)
316 return -ENODEV;
317
318 priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_platform_data),
319 GFP_KERNEL);
320 if (!priv)
321 return -ENOMEM;
322
323 /* FIXME: need to allocate resource in PIC32 space */
324#if 0
325 priv->base = bus_request_region(r->start, resource_size(r),
326 pdev->name);
327#else
328 priv->base = r->start;
329#endif
330 if (!priv->base)
331 return -EBUSY;
332
333 priv->xfer_timeout = 200;
334 priv->ack_timeout = 200;
335 priv->ctl_timeout = 200;
336
337 priv->adap.nr = pdev->id;
338 priv->adap.algo = &platform_algo;
339 priv->adap.algo_data = priv;
340 priv->adap.dev.parent = &pdev->dev;
341 strlcpy(priv->adap.name, "PIC32 I2C", sizeof(priv->adap.name));
342
343 i2c_platform_setup(priv);
344
345 ret = i2c_add_numbered_adapter(&priv->adap);
346 if (ret) {
347 i2c_platform_disable(priv);
348 return ret;
349 }
350
351 platform_set_drvdata(pdev, priv);
352 return 0;
353}
354
355static int i2c_platform_remove(struct platform_device *pdev)
356{
357 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
358
359 pr_debug("i2c_platform_remove\n");
360 platform_set_drvdata(pdev, NULL);
361 i2c_del_adapter(&priv->adap);
362 i2c_platform_disable(priv);
363 return 0;
364}
365
366#ifdef CONFIG_PM
367static int
368i2c_platform_suspend(struct platform_device *pdev, pm_message_t state)
369{
370 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
371
372 dev_dbg(&pdev->dev, "i2c_platform_disable\n");
373 i2c_platform_disable(priv);
374
375 return 0;
376}
377
378static int
379i2c_platform_resume(struct platform_device *pdev)
380{
381 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
382
383 dev_dbg(&pdev->dev, "i2c_platform_setup\n");
384 i2c_platform_setup(priv);
385
386 return 0;
387}
388#else
389#define i2c_platform_suspend NULL
390#define i2c_platform_resume NULL
391#endif
392
393static struct platform_driver i2c_platform_driver = {
394 .driver = {
395 .name = "i2c_pic32",
396 .owner = THIS_MODULE,
397 },
398 .probe = i2c_platform_probe,
399 .remove = i2c_platform_remove,
400 .suspend = i2c_platform_suspend,
401 .resume = i2c_platform_resume,
402};
403
404static int __init
405i2c_platform_init(void)
406{
407 pr_debug("i2c_platform_init\n");
408 return platform_driver_register(&i2c_platform_driver);
409}
410
411static void __exit
412i2c_platform_exit(void)
413{
414 pr_debug("i2c_platform_exit\n");
415 platform_driver_unregister(&i2c_platform_driver);
416}
417
418MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC.");
419MODULE_DESCRIPTION("PIC32 I2C driver");
420MODULE_LICENSE("GPL");
421
422module_init(i2c_platform_init);
423module_exit(i2c_platform_exit);
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index fa374fe3746b..f7ac3edda1b2 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -443,10 +443,8 @@ static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
443 msg.data = 0xc00 | msixvec; 443 msg.data = 0xc00 | msixvec;
444 444
445 ret = irq_set_msi_desc(xirq, desc); 445 ret = irq_set_msi_desc(xirq, desc);
446 if (ret < 0) { 446 if (ret < 0)
447 destroy_irq(xirq);
448 return ret; 447 return ret;
449 }
450 448
451 write_msi_msg(xirq, &msg); 449 write_msi_msg(xirq, &msg);
452 return 0; 450 return 0;
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 37fe8e7887e2..d3ed15b2b2d1 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -215,17 +215,12 @@ static int ltq_pci_probe(struct platform_device *pdev)
215 215
216 pci_clear_flags(PCI_PROBE_ONLY); 216 pci_clear_flags(PCI_PROBE_ONLY);
217 217
218 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
219 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1); 218 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
220 if (!res_cfg || !res_bridge) {
221 dev_err(&pdev->dev, "missing memory resources\n");
222 return -EINVAL;
223 }
224
225 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge); 219 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
226 if (IS_ERR(ltq_pci_membase)) 220 if (IS_ERR(ltq_pci_membase))
227 return PTR_ERR(ltq_pci_membase); 221 return PTR_ERR(ltq_pci_membase);
228 222
223 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
229 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg); 224 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
230 if (IS_ERR(ltq_pci_mapped_cfg)) 225 if (IS_ERR(ltq_pci_mapped_cfg))
231 return PTR_ERR(ltq_pci_mapped_cfg); 226 return PTR_ERR(ltq_pci_mapped_cfg);
diff --git a/arch/mips/pmcs-msp71xx/msp_irq.c b/arch/mips/pmcs-msp71xx/msp_irq.c
index f914c753de21..8d53d7a2ed45 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq.c
@@ -16,6 +16,7 @@
16#include <linux/time.h> 16#include <linux/time.h>
17 17
18#include <asm/irq_cpu.h> 18#include <asm/irq_cpu.h>
19#include <asm/setup.h>
19 20
20#include <msp_int.h> 21#include <msp_int.h>
21 22
diff --git a/arch/mips/pmcs-msp71xx/msp_irq_cic.c b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
index b8df2f7b3328..1207ec4dfb77 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
@@ -131,11 +131,11 @@ static int msp_cic_irq_set_affinity(struct irq_data *d,
131 int cpu; 131 int cpu;
132 unsigned long flags; 132 unsigned long flags;
133 unsigned int mtflags; 133 unsigned int mtflags;
134 unsigned long imask = (1 << (irq - MSP_CIC_INTBASE)); 134 unsigned long imask = (1 << (d->irq - MSP_CIC_INTBASE));
135 volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG; 135 volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
136 136
137 /* timer balancing should be disabled in kernel code */ 137 /* timer balancing should be disabled in kernel code */
138 BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER); 138 BUG_ON(d->irq == MSP_INT_VPE0_TIMER || d->irq == MSP_INT_VPE1_TIMER);
139 139
140 LOCK_CORE(flags, mtflags); 140 LOCK_CORE(flags, mtflags);
141 /* enable if any of each VPE's TCs require this IRQ */ 141 /* enable if any of each VPE's TCs require this IRQ */
diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile
index c8ed2c807e69..455c40d6d625 100644
--- a/arch/mips/sibyte/Makefile
+++ b/arch/mips/sibyte/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_SIBYTE_RHONE) += swarm/
25obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/ 25obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/
26obj-$(CONFIG_SIBYTE_SWARM) += swarm/ 26obj-$(CONFIG_SIBYTE_SWARM) += swarm/
27obj-$(CONFIG_SIBYTE_BIGSUR) += swarm/ 27obj-$(CONFIG_SIBYTE_BIGSUR) += swarm/
28obj-$(CONFIG_SIBYTE_LITTLESUR) += swarm/
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 00:44:46 -0500