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-rw-r--r--arch/mips/Kconfig67
-rw-r--r--arch/mips/Makefile23
-rw-r--r--arch/mips/alchemy/common/platform.c98
-rw-r--r--arch/mips/alchemy/pb1200/platform.c81
-rw-r--r--arch/mips/configs/ip22_defconfig1
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/ip28_defconfig2
-rw-r--r--arch/mips/configs/pnx8335-stb225_defconfig1149
-rw-r--r--arch/mips/emma/Kconfig29
-rw-r--r--arch/mips/emma/common/Makefile (renamed from arch/mips/emma2rh/common/Makefile)2
-rw-r--r--arch/mips/emma/common/prom.c (renamed from arch/mips/emma2rh/common/prom.c)6
-rw-r--r--arch/mips/emma/markeins/Makefile (renamed from arch/mips/emma2rh/markeins/Makefile)2
-rw-r--r--arch/mips/emma/markeins/irq.c331
-rw-r--r--arch/mips/emma/markeins/led.c (renamed from arch/mips/emma2rh/markeins/led.c)2
-rw-r--r--arch/mips/emma/markeins/platform.c (renamed from arch/mips/emma2rh/markeins/platform.c)2
-rw-r--r--arch/mips/emma/markeins/setup.c (renamed from arch/mips/emma2rh/markeins/setup.c)2
-rw-r--r--arch/mips/emma2rh/common/irq.c105
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c106
-rw-r--r--arch/mips/emma2rh/markeins/irq.c132
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c158
-rw-r--r--arch/mips/include/asm/bitops.h114
-rw-r--r--arch/mips/include/asm/break.h1
-rw-r--r--arch/mips/include/asm/byteorder.h40
-rw-r--r--arch/mips/include/asm/cpu-features.h2
-rw-r--r--arch/mips/include/asm/ds1286.h15
-rw-r--r--arch/mips/include/asm/emma/emma2rh.h (renamed from arch/mips/include/asm/emma2rh/emma2rh.h)15
-rw-r--r--arch/mips/include/asm/emma/markeins.h (renamed from arch/mips/include/asm/emma2rh/markeins.h)0
-rw-r--r--arch/mips/include/asm/fpu_emulator.h17
-rw-r--r--arch/mips/include/asm/m48t35.h27
-rw-r--r--arch/mips/include/asm/mach-lemote/pci.h30
-rw-r--r--arch/mips/include/asm/mach-pnx833x/gpio.h172
-rw-r--r--arch/mips/include/asm/mach-pnx833x/irq-mapping.h126
-rw-r--r--arch/mips/include/asm/mach-pnx833x/irq.h53
-rw-r--r--arch/mips/include/asm/mach-pnx833x/pnx833x.h202
-rw-r--r--arch/mips/include/asm/mach-pnx833x/war.h25
-rw-r--r--arch/mips/include/asm/mach-tx49xx/mangle-port.h26
-rw-r--r--arch/mips/include/asm/mipsregs.h1
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/ptrace.h17
-rw-r--r--arch/mips/include/asm/txx9/generic.h5
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/cpu-probe.c247
-rw-r--r--arch/mips/kernel/scall32-o32.S4
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/setup.c4
-rw-r--r--arch/mips/kernel/smp.c12
-rw-r--r--arch/mips/kernel/traps.c29
-rw-r--r--arch/mips/kernel/unaligned.c20
-rw-r--r--arch/mips/lemote/lm2e/pci.c13
-rw-r--r--arch/mips/lemote/lm2e/setup.c11
-rw-r--r--arch/mips/lib/Makefile1
-rw-r--r--arch/mips/lib/dump_tlb.c1
-rw-r--r--arch/mips/math-emu/cp1emu.c12
-rw-r--r--arch/mips/math-emu/dsemul.c7
-rw-r--r--arch/mips/math-emu/dsemul.h17
-rw-r--r--arch/mips/mm/Makefile1
-rw-r--r--arch/mips/mm/dma-default.c2
-rw-r--r--arch/mips/nxp/pnx833x/common/Makefile3
-rw-r--r--arch/mips/nxp/pnx833x/common/interrupts.c380
-rw-r--r--arch/mips/nxp/pnx833x/common/platform.c319
-rw-r--r--arch/mips/nxp/pnx833x/common/prom.c70
-rw-r--r--arch/mips/nxp/pnx833x/common/reset.c45
-rw-r--r--arch/mips/nxp/pnx833x/common/setup.c64
-rw-r--r--arch/mips/nxp/pnx833x/stb22x/Makefile3
-rw-r--r--arch/mips/nxp/pnx833x/stb22x/board.c133
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-emma2rh.c2
-rw-r--r--arch/mips/pci/fixup-rc32434.c1
-rw-r--r--arch/mips/pci/ops-emma2rh.c2
-rw-r--r--arch/mips/pci/pci-emma2rh.c2
-rw-r--r--arch/mips/rb532/devices.c2
-rw-r--r--arch/mips/rb532/gpio.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c17
-rw-r--r--arch/mips/txx9/Kconfig6
-rw-r--r--arch/mips/txx9/generic/7segled.c112
-rw-r--r--arch/mips/txx9/generic/Makefile1
-rw-r--r--arch/mips/txx9/generic/setup.c37
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c25
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c88
79 files changed, 3965 insertions, 926 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5f149b030c0f..f4af967a6b30 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -238,21 +238,8 @@ config MIPS_SIM
238 This option enables support for MIPS Technologies MIPSsim software 238 This option enables support for MIPS Technologies MIPSsim software
239 emulator. 239 emulator.
240 240
241config MARKEINS 241config MACH_EMMA
242 bool "NEC EMMA2RH Mark-eins" 242 bool "NEC EMMA series based machines"
243 select CEVT_R4K
244 select CSRC_R4K
245 select DMA_NONCOHERENT
246 select HW_HAS_PCI
247 select IRQ_CPU
248 select SWAP_IO_SPACE
249 select SYS_SUPPORTS_32BIT_KERNEL
250 select SYS_SUPPORTS_BIG_ENDIAN
251 select SYS_SUPPORTS_LITTLE_ENDIAN
252 select SYS_HAS_CPU_R5000
253 help
254 This enables support for the R5432-based NEC Mark-eins
255 boards with R5500 CPU.
256 243
257config MACH_VR41XX 244config MACH_VR41XX
258 bool "NEC VR4100 series based machines" 245 bool "NEC VR4100 series based machines"
@@ -261,6 +248,19 @@ config MACH_VR41XX
261 select SYS_HAS_CPU_VR41XX 248 select SYS_HAS_CPU_VR41XX
262 select GENERIC_HARDIRQS_NO__DO_IRQ 249 select GENERIC_HARDIRQS_NO__DO_IRQ
263 250
251config NXP_STB220
252 bool "NXP STB220 board"
253 select SOC_PNX833X
254 help
255 Support for NXP Semiconductors STB220 Development Board.
256
257config NXP_STB225
258 bool "NXP 225 board"
259 select SOC_PNX833X
260 select SOC_PNX8335
261 help
262 Support for NXP Semiconductors STB225 Development Board.
263
264config PNX8550_JBS 264config PNX8550_JBS
265 bool "NXP PNX8550 based JBS board" 265 bool "NXP PNX8550 based JBS board"
266 select PNX8550 266 select PNX8550
@@ -327,7 +327,6 @@ config SGI_IP22
327 select IP22_CPU_SCACHE 327 select IP22_CPU_SCACHE
328 select IRQ_CPU 328 select IRQ_CPU
329 select GENERIC_ISA_DMA_SUPPORT_BROKEN 329 select GENERIC_ISA_DMA_SUPPORT_BROKEN
330 select SGI_HAS_DS1286
331 select SGI_HAS_I8042 330 select SGI_HAS_I8042
332 select SGI_HAS_INDYDOG 331 select SGI_HAS_INDYDOG
333 select SGI_HAS_HAL2 332 select SGI_HAS_HAL2
@@ -382,7 +381,6 @@ config SGI_IP28
382 select HW_HAS_EISA 381 select HW_HAS_EISA
383 select I8253 382 select I8253
384 select I8259 383 select I8259
385 select SGI_HAS_DS1286
386 select SGI_HAS_I8042 384 select SGI_HAS_I8042
387 select SGI_HAS_INDYDOG 385 select SGI_HAS_INDYDOG
388 select SGI_HAS_HAL2 386 select SGI_HAS_HAL2
@@ -601,6 +599,7 @@ endchoice
601 599
602source "arch/mips/alchemy/Kconfig" 600source "arch/mips/alchemy/Kconfig"
603source "arch/mips/basler/excite/Kconfig" 601source "arch/mips/basler/excite/Kconfig"
602source "arch/mips/emma/Kconfig"
604source "arch/mips/jazz/Kconfig" 603source "arch/mips/jazz/Kconfig"
605source "arch/mips/lasat/Kconfig" 604source "arch/mips/lasat/Kconfig"
606source "arch/mips/pmc-sierra/Kconfig" 605source "arch/mips/pmc-sierra/Kconfig"
@@ -849,6 +848,24 @@ config MIPS_RM9122
849 bool 848 bool
850 select SERIAL_RM9000 849 select SERIAL_RM9000
851 850
851config SOC_PNX833X
852 bool
853 select CEVT_R4K
854 select CSRC_R4K
855 select IRQ_CPU
856 select DMA_NONCOHERENT
857 select SYS_HAS_CPU_MIPS32_R2
858 select SYS_SUPPORTS_32BIT_KERNEL
859 select SYS_SUPPORTS_LITTLE_ENDIAN
860 select SYS_SUPPORTS_BIG_ENDIAN
861 select GENERIC_HARDIRQS_NO__DO_IRQ
862 select GENERIC_GPIO
863 select CPU_MIPSR2_IRQ_VI
864
865config SOC_PNX8335
866 bool
867 select SOC_PNX833X
868
852config PNX8550 869config PNX8550
853 bool 870 bool
854 select SOC_PNX8550 871 select SOC_PNX8550
@@ -874,9 +891,6 @@ config EMMA2RH
874config SERIAL_RM9000 891config SERIAL_RM9000
875 bool 892 bool
876 893
877config SGI_HAS_DS1286
878 bool
879
880config SGI_HAS_INDYDOG 894config SGI_HAS_INDYDOG
881 bool 895 bool
882 896
@@ -1092,6 +1106,16 @@ config CPU_R5432
1092 select CPU_SUPPORTS_32BIT_KERNEL 1106 select CPU_SUPPORTS_32BIT_KERNEL
1093 select CPU_SUPPORTS_64BIT_KERNEL 1107 select CPU_SUPPORTS_64BIT_KERNEL
1094 1108
1109config CPU_R5500
1110 bool "R5500"
1111 depends on SYS_HAS_CPU_R5500
1112 select CPU_HAS_LLSC
1113 select CPU_SUPPORTS_32BIT_KERNEL
1114 select CPU_SUPPORTS_64BIT_KERNEL
1115 help
1116 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1117 instruction set.
1118
1095config CPU_R6000 1119config CPU_R6000
1096 bool "R6000" 1120 bool "R6000"
1097 depends on EXPERIMENTAL 1121 depends on EXPERIMENTAL
@@ -1202,6 +1226,9 @@ config SYS_HAS_CPU_R5000
1202config SYS_HAS_CPU_R5432 1226config SYS_HAS_CPU_R5432
1203 bool 1227 bool
1204 1228
1229config SYS_HAS_CPU_R5500
1230 bool
1231
1205config SYS_HAS_CPU_R6000 1232config SYS_HAS_CPU_R6000
1206 bool 1233 bool
1207 1234
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 7f39fd8a91fe..28c55f608913 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -131,6 +131,8 @@ cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_
131cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap 131cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
132cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \ 132cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \
133 -Wa,--trap 133 -Wa,--trap
134cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \
135 -Wa,--trap
134cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ 136cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \
135 -Wa,--trap 137 -Wa,--trap
136cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ 138cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \
@@ -381,6 +383,14 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
381# 383#
382load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 384load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
383 385
386# NXP STB225
387core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/
388cflags-$(CONFIG_SOC_PNX833X) += -Iarch/mips/include/asm/mach-pnx833x
389libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/
390load-$(CONFIG_NXP_STB220) += 0xffffffff80001000
391libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/
392load-$(CONFIG_NXP_STB225) += 0xffffffff80001000
393
384# 394#
385# Common NXP PNX8550 395# Common NXP PNX8550
386# 396#
@@ -399,14 +409,17 @@ load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
399libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/ 409libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/
400load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 410load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
401 411
402# NEC EMMA2RH boards
403# 412#
404core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/ 413# Common NEC EMMAXXX
405cflags-$(CONFIG_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh 414#
415core-$(CONFIG_SOC_EMMA) += arch/mips/emma/common/
416cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
406 417
418#
407# NEC EMMA2RH Mark-eins 419# NEC EMMA2RH Mark-eins
408core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/ 420#
409load-$(CONFIG_MARKEINS) += 0xffffffff88100000 421core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
422load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
410 423
411# 424#
412# SGI IP22 (Indy/Indigo2) 425# SGI IP22 (Indy/Indigo2)
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index dc8a67efac28..5c76c6448e04 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -17,6 +17,8 @@
17#include <linux/init.h> 17#include <linux/init.h>
18 18
19#include <asm/mach-au1x00/au1xxx.h> 19#include <asm/mach-au1x00/au1xxx.h>
20#include <asm/mach-au1x00/au1xxx_dbdma.h>
21#include <asm/mach-au1x00/au1100_mmc.h>
20 22
21#define PORT(_base, _irq) \ 23#define PORT(_base, _irq) \
22 { \ 24 { \
@@ -163,24 +165,6 @@ static struct resource au1xxx_usb_gdt_resources[] = {
163 }, 165 },
164}; 166};
165 167
166static struct resource au1xxx_mmc_resources[] = {
167 [0] = {
168 .start = SD0_PHYS_ADDR,
169 .end = SD0_PHYS_ADDR + 0x7ffff,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = SD1_PHYS_ADDR,
174 .end = SD1_PHYS_ADDR + 0x7ffff,
175 .flags = IORESOURCE_MEM,
176 },
177 [2] = {
178 .start = AU1200_SD_INT,
179 .end = AU1200_SD_INT,
180 .flags = IORESOURCE_IRQ,
181 }
182};
183
184static u64 udc_dmamask = DMA_32BIT_MASK; 168static u64 udc_dmamask = DMA_32BIT_MASK;
185 169
186static struct platform_device au1xxx_usb_gdt_device = { 170static struct platform_device au1xxx_usb_gdt_device = {
@@ -249,16 +233,79 @@ static struct platform_device au1200_lcd_device = {
249 233
250static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; 234static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK;
251 235
252static struct platform_device au1xxx_mmc_device = { 236extern struct au1xmmc_platform_data au1xmmc_platdata[2];
237
238static struct resource au1200_mmc0_resources[] = {
239 [0] = {
240 .start = SD0_PHYS_ADDR,
241 .end = SD0_PHYS_ADDR + 0x7ffff,
242 .flags = IORESOURCE_MEM,
243 },
244 [1] = {
245 .start = AU1200_SD_INT,
246 .end = AU1200_SD_INT,
247 .flags = IORESOURCE_IRQ,
248 },
249 [2] = {
250 .start = DSCR_CMD0_SDMS_TX0,
251 .end = DSCR_CMD0_SDMS_TX0,
252 .flags = IORESOURCE_DMA,
253 },
254 [3] = {
255 .start = DSCR_CMD0_SDMS_RX0,
256 .end = DSCR_CMD0_SDMS_RX0,
257 .flags = IORESOURCE_DMA,
258 }
259};
260
261static struct platform_device au1200_mmc0_device = {
253 .name = "au1xxx-mmc", 262 .name = "au1xxx-mmc",
254 .id = 0, 263 .id = 0,
255 .dev = { 264 .dev = {
256 .dma_mask = &au1xxx_mmc_dmamask, 265 .dma_mask = &au1xxx_mmc_dmamask,
257 .coherent_dma_mask = DMA_32BIT_MASK, 266 .coherent_dma_mask = DMA_32BIT_MASK,
267 .platform_data = &au1xmmc_platdata[0],
258 }, 268 },
259 .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), 269 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
260 .resource = au1xxx_mmc_resources, 270 .resource = au1200_mmc0_resources,
261}; 271};
272
273#ifndef CONFIG_MIPS_DB1200
274static struct resource au1200_mmc1_resources[] = {
275 [0] = {
276 .start = SD1_PHYS_ADDR,
277 .end = SD1_PHYS_ADDR + 0x7ffff,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = AU1200_SD_INT,
282 .end = AU1200_SD_INT,
283 .flags = IORESOURCE_IRQ,
284 },
285 [2] = {
286 .start = DSCR_CMD0_SDMS_TX1,
287 .end = DSCR_CMD0_SDMS_TX1,
288 .flags = IORESOURCE_DMA,
289 },
290 [3] = {
291 .start = DSCR_CMD0_SDMS_RX1,
292 .end = DSCR_CMD0_SDMS_RX1,
293 .flags = IORESOURCE_DMA,
294 }
295};
296
297static struct platform_device au1200_mmc1_device = {
298 .name = "au1xxx-mmc",
299 .id = 1,
300 .dev = {
301 .dma_mask = &au1xxx_mmc_dmamask,
302 .coherent_dma_mask = DMA_32BIT_MASK,
303 .platform_data = &au1xmmc_platdata[1],
304 },
305 .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
306 .resource = au1200_mmc1_resources,
307};
308#endif /* #ifndef CONFIG_MIPS_DB1200 */
262#endif /* #ifdef CONFIG_SOC_AU1200 */ 309#endif /* #ifdef CONFIG_SOC_AU1200 */
263 310
264static struct platform_device au1x00_pcmcia_device = { 311static struct platform_device au1x00_pcmcia_device = {
@@ -296,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
296 &au1xxx_usb_gdt_device, 343 &au1xxx_usb_gdt_device,
297 &au1xxx_usb_otg_device, 344 &au1xxx_usb_otg_device,
298 &au1200_lcd_device, 345 &au1200_lcd_device,
299 &au1xxx_mmc_device, 346 &au1200_mmc0_device,
347#ifndef CONFIG_MIPS_DB1200
348 &au1200_mmc1_device,
349#endif
300#endif 350#endif
301#ifdef SMBUS_PSC_BASE 351#ifdef SMBUS_PSC_BASE
302 &pbdb_smbus_device, 352 &pbdb_smbus_device,
diff --git a/arch/mips/alchemy/pb1200/platform.c b/arch/mips/alchemy/pb1200/platform.c
index f8fb0aeac571..95303297c534 100644
--- a/arch/mips/alchemy/pb1200/platform.c
+++ b/arch/mips/alchemy/pb1200/platform.c
@@ -20,9 +20,90 @@
20 20
21#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/leds.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24 25
25#include <asm/mach-au1x00/au1xxx.h> 26#include <asm/mach-au1x00/au1xxx.h>
27#include <asm/mach-au1x00/au1100_mmc.h>
28
29static int mmc_activity;
30
31static void pb1200mmc0_set_power(void *mmc_host, int state)
32{
33 if (state)
34 bcsr->board |= BCSR_BOARD_SD0PWR;
35 else
36 bcsr->board &= ~BCSR_BOARD_SD0PWR;
37
38 au_sync_delay(1);
39}
40
41static int pb1200mmc0_card_readonly(void *mmc_host)
42{
43 return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0;
44}
45
46static int pb1200mmc0_card_inserted(void *mmc_host)
47{
48 return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0;
49}
50
51static void pb1200_mmcled_set(struct led_classdev *led,
52 enum led_brightness brightness)
53{
54 if (brightness != LED_OFF) {
55 if (++mmc_activity == 1)
56 bcsr->disk_leds &= ~(1 << 8);
57 } else {
58 if (--mmc_activity == 0)
59 bcsr->disk_leds |= (1 << 8);
60 }
61}
62
63static struct led_classdev pb1200mmc_led = {
64 .brightness_set = pb1200_mmcled_set,
65};
66
67#ifndef CONFIG_MIPS_DB1200
68static void pb1200mmc1_set_power(void *mmc_host, int state)
69{
70 if (state)
71 bcsr->board |= BCSR_BOARD_SD1PWR;
72 else
73 bcsr->board &= ~BCSR_BOARD_SD1PWR;
74
75 au_sync_delay(1);
76}
77
78static int pb1200mmc1_card_readonly(void *mmc_host)
79{
80 return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0;
81}
82
83static int pb1200mmc1_card_inserted(void *mmc_host)
84{
85 return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0;
86}
87#endif
88
89const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
90 [0] = {
91 .set_power = pb1200mmc0_set_power,
92 .card_inserted = pb1200mmc0_card_inserted,
93 .card_readonly = pb1200mmc0_card_readonly,
94 .cd_setup = NULL, /* use poll-timer in driver */
95 .led = &pb1200mmc_led,
96 },
97#ifndef CONFIG_MIPS_DB1200
98 [1] = {
99 .set_power = pb1200mmc1_set_power,
100 .card_inserted = pb1200mmc1_card_inserted,
101 .card_readonly = pb1200mmc1_card_readonly,
102 .cd_setup = NULL, /* use poll-timer in driver */
103 .led = &pb1200mmc_led,
104 },
105#endif
106};
26 107
27static struct resource ide_resources[] = { 108static struct resource ide_resources[] = {
28 [0] = { 109 [0] = {
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index cc8e6bf2b245..f719bf5e01aa 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -771,7 +771,6 @@ CONFIG_WATCHDOG=y
771CONFIG_INDYDOG=m 771CONFIG_INDYDOG=m
772# CONFIG_HW_RANDOM is not set 772# CONFIG_HW_RANDOM is not set
773# CONFIG_RTC is not set 773# CONFIG_RTC is not set
774CONFIG_SGI_DS1286=m
775# CONFIG_R3964 is not set 774# CONFIG_R3964 is not set
776CONFIG_RAW_DRIVER=m 775CONFIG_RAW_DRIVER=m
777CONFIG_MAX_RAW_DEVS=256 776CONFIG_MAX_RAW_DEVS=256
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 831d3e5a1ea6..34ea319be94c 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -701,7 +701,6 @@ CONFIG_LEGACY_PTY_COUNT=256
701# CONFIG_WATCHDOG is not set 701# CONFIG_WATCHDOG is not set
702CONFIG_HW_RANDOM=m 702CONFIG_HW_RANDOM=m
703# CONFIG_RTC is not set 703# CONFIG_RTC is not set
704CONFIG_SGI_IP27_RTC=y
705# CONFIG_R3964 is not set 704# CONFIG_R3964 is not set
706# CONFIG_APPLICOM is not set 705# CONFIG_APPLICOM is not set
707# CONFIG_DRM is not set 706# CONFIG_DRM is not set
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 822b01f643e3..70a744e9a8c5 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -70,7 +70,6 @@ CONFIG_CPU_BIG_ENDIAN=y
70CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 70CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
71CONFIG_IRQ_CPU=y 71CONFIG_IRQ_CPU=y
72CONFIG_SWAP_IO_SPACE=y 72CONFIG_SWAP_IO_SPACE=y
73CONFIG_SGI_HAS_DS1286=y
74CONFIG_SGI_HAS_INDYDOG=y 73CONFIG_SGI_HAS_INDYDOG=y
75CONFIG_SGI_HAS_SEEQ=y 74CONFIG_SGI_HAS_SEEQ=y
76CONFIG_SGI_HAS_WD93=y 75CONFIG_SGI_HAS_WD93=y
@@ -585,7 +584,6 @@ CONFIG_LEGACY_PTY_COUNT=256
585# CONFIG_IPMI_HANDLER is not set 584# CONFIG_IPMI_HANDLER is not set
586# CONFIG_HW_RANDOM is not set 585# CONFIG_HW_RANDOM is not set
587# CONFIG_RTC is not set 586# CONFIG_RTC is not set
588CONFIG_SGI_DS1286=y
589# CONFIG_DTLK is not set 587# CONFIG_DTLK is not set
590# CONFIG_R3964 is not set 588# CONFIG_R3964 is not set
591# CONFIG_RAW_DRIVER is not set 589# CONFIG_RAW_DRIVER is not set
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
new file mode 100644
index 000000000000..d9536522cff5
--- /dev/null
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -0,0 +1,1149 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26
4# Sat Jul 26 09:02:59 2008
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
19# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set
21# CONFIG_MARKEINS is not set
22# CONFIG_MACH_VR41XX is not set
23# CONFIG_NXP_STB220 is not set
24CONFIG_NXP_STB225=y
25# CONFIG_PNX8550_JBS is not set
26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set
29# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP28 is not set
32# CONFIG_SGI_IP32 is not set
33# CONFIG_SIBYTE_CRHINE is not set
34# CONFIG_SIBYTE_CARMEL is not set
35# CONFIG_SIBYTE_CRHONE is not set
36# CONFIG_SIBYTE_RHONE is not set
37# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set
39# CONFIG_SIBYTE_SENTOSA is not set
40# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set
42# CONFIG_MACH_TX39XX is not set
43# CONFIG_MACH_TX49XX is not set
44# CONFIG_WR_PPMC is not set
45CONFIG_RWSEM_GENERIC_SPINLOCK=y
46# CONFIG_ARCH_HAS_ILOG2_U32 is not set
47# CONFIG_ARCH_HAS_ILOG2_U64 is not set
48CONFIG_ARCH_SUPPORTS_OPROFILE=y
49CONFIG_GENERIC_FIND_NEXT_BIT=y
50CONFIG_GENERIC_HWEIGHT=y
51CONFIG_GENERIC_CALIBRATE_DELAY=y
52CONFIG_GENERIC_CLOCKEVENTS=y
53CONFIG_GENERIC_TIME=y
54CONFIG_GENERIC_CMOS_UPDATE=y
55CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
56CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
57CONFIG_CEVT_R4K=y
58CONFIG_CSRC_R4K=y
59CONFIG_DMA_NONCOHERENT=y
60CONFIG_DMA_NEED_PCI_MAP_STATE=y
61# CONFIG_HOTPLUG_CPU is not set
62# CONFIG_NO_IOPORT is not set
63CONFIG_GENERIC_GPIO=y
64# CONFIG_CPU_BIG_ENDIAN is not set
65CONFIG_CPU_LITTLE_ENDIAN=y
66CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
67CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
68CONFIG_IRQ_CPU=y
69CONFIG_SOC_PNX833X=y
70CONFIG_SOC_PNX8335=y
71CONFIG_MIPS_L1_CACHE_SHIFT=5
72
73#
74# CPU selection
75#
76# CONFIG_CPU_LOONGSON2 is not set
77# CONFIG_CPU_MIPS32_R1 is not set
78CONFIG_CPU_MIPS32_R2=y
79# CONFIG_CPU_MIPS64_R1 is not set
80# CONFIG_CPU_MIPS64_R2 is not set
81# CONFIG_CPU_R3000 is not set
82# CONFIG_CPU_TX39XX is not set
83# CONFIG_CPU_VR41XX is not set
84# CONFIG_CPU_R4300 is not set
85# CONFIG_CPU_R4X00 is not set
86# CONFIG_CPU_TX49XX is not set
87# CONFIG_CPU_R5000 is not set
88# CONFIG_CPU_R5432 is not set
89# CONFIG_CPU_R6000 is not set
90# CONFIG_CPU_NEVADA is not set
91# CONFIG_CPU_R8000 is not set
92# CONFIG_CPU_R10000 is not set
93# CONFIG_CPU_RM7000 is not set
94# CONFIG_CPU_RM9000 is not set
95# CONFIG_CPU_SB1 is not set
96CONFIG_SYS_HAS_CPU_MIPS32_R2=y
97CONFIG_CPU_MIPS32=y
98CONFIG_CPU_MIPSR2=y
99CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
100CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
101
102#
103# Kernel type
104#
105CONFIG_32BIT=y
106# CONFIG_64BIT is not set
107CONFIG_PAGE_SIZE_4KB=y
108# CONFIG_PAGE_SIZE_8KB is not set
109# CONFIG_PAGE_SIZE_16KB is not set
110# CONFIG_PAGE_SIZE_64KB is not set
111CONFIG_CPU_HAS_PREFETCH=y
112CONFIG_MIPS_MT_DISABLED=y
113# CONFIG_MIPS_MT_SMP is not set
114# CONFIG_MIPS_MT_SMTC is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_MIPSR2_IRQ_VI=y
117CONFIG_CPU_HAS_SYNC=y
118CONFIG_GENERIC_HARDIRQS=y
119CONFIG_GENERIC_IRQ_PROBE=y
120CONFIG_CPU_SUPPORTS_HIGHMEM=y
121CONFIG_ARCH_FLATMEM_ENABLE=y
122CONFIG_ARCH_POPULATES_NODE_MAP=y
123CONFIG_SELECT_MEMORY_MODEL=y
124CONFIG_FLATMEM_MANUAL=y
125# CONFIG_DISCONTIGMEM_MANUAL is not set
126# CONFIG_SPARSEMEM_MANUAL is not set
127CONFIG_FLATMEM=y
128CONFIG_FLAT_NODE_MEM_MAP=y
129# CONFIG_SPARSEMEM_STATIC is not set
130# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
131CONFIG_PAGEFLAGS_EXTENDED=y
132CONFIG_SPLIT_PTLOCK_CPUS=4
133# CONFIG_RESOURCES_64BIT is not set
134CONFIG_ZONE_DMA_FLAG=0
135CONFIG_VIRT_TO_BUS=y
136CONFIG_TICK_ONESHOT=y
137CONFIG_NO_HZ=y
138CONFIG_HIGH_RES_TIMERS=y
139CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
140# CONFIG_HZ_48 is not set
141# CONFIG_HZ_100 is not set
142CONFIG_HZ_128=y
143# CONFIG_HZ_250 is not set
144# CONFIG_HZ_256 is not set
145# CONFIG_HZ_1000 is not set
146# CONFIG_HZ_1024 is not set
147CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
148CONFIG_HZ=128
149# CONFIG_PREEMPT_NONE is not set
150CONFIG_PREEMPT_VOLUNTARY=y
151# CONFIG_PREEMPT is not set
152# CONFIG_KEXEC is not set
153# CONFIG_SECCOMP is not set
154CONFIG_LOCKDEP_SUPPORT=y
155CONFIG_STACKTRACE_SUPPORT=y
156CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
157
158#
159# General setup
160#
161CONFIG_EXPERIMENTAL=y
162CONFIG_BROKEN_ON_SMP=y
163CONFIG_INIT_ENV_ARG_LIMIT=32
164CONFIG_LOCALVERSION=""
165# CONFIG_LOCALVERSION_AUTO is not set
166# CONFIG_SWAP is not set
167CONFIG_SYSVIPC=y
168CONFIG_SYSVIPC_SYSCTL=y
169# CONFIG_POSIX_MQUEUE is not set
170# CONFIG_BSD_PROCESS_ACCT is not set
171# CONFIG_TASKSTATS is not set
172# CONFIG_AUDIT is not set
173# CONFIG_IKCONFIG is not set
174CONFIG_LOG_BUF_SHIFT=14
175# CONFIG_CGROUPS is not set
176# CONFIG_GROUP_SCHED is not set
177CONFIG_SYSFS_DEPRECATED=y
178CONFIG_SYSFS_DEPRECATED_V2=y
179# CONFIG_RELAY is not set
180# CONFIG_NAMESPACES is not set
181# CONFIG_BLK_DEV_INITRD is not set
182CONFIG_CC_OPTIMIZE_FOR_SIZE=y
183CONFIG_SYSCTL=y
184CONFIG_EMBEDDED=y
185CONFIG_SYSCTL_SYSCALL=y
186CONFIG_SYSCTL_SYSCALL_CHECK=y
187CONFIG_KALLSYMS=y
188# CONFIG_KALLSYMS_EXTRA_PASS is not set
189CONFIG_HOTPLUG=y
190CONFIG_PRINTK=y
191CONFIG_BUG=y
192CONFIG_ELF_CORE=y
193CONFIG_PCSPKR_PLATFORM=y
194CONFIG_COMPAT_BRK=y
195CONFIG_BASE_FULL=y
196CONFIG_FUTEX=y
197CONFIG_ANON_INODES=y
198CONFIG_EPOLL=y
199CONFIG_SIGNALFD=y
200CONFIG_TIMERFD=y
201CONFIG_EVENTFD=y
202CONFIG_SHMEM=y
203CONFIG_VM_EVENT_COUNTERS=y
204CONFIG_SLAB=y
205# CONFIG_SLUB is not set
206# CONFIG_SLOB is not set
207# CONFIG_PROFILING is not set
208# CONFIG_MARKERS is not set
209CONFIG_HAVE_OPROFILE=y
210# CONFIG_HAVE_KPROBES is not set
211# CONFIG_HAVE_KRETPROBES is not set
212# CONFIG_HAVE_DMA_ATTRS is not set
213# CONFIG_USE_GENERIC_SMP_HELPERS is not set
214CONFIG_PROC_PAGE_MONITOR=y
215CONFIG_SLABINFO=y
216CONFIG_RT_MUTEXES=y
217# CONFIG_TINY_SHMEM is not set
218CONFIG_BASE_SMALL=0
219CONFIG_MODULES=y
220# CONFIG_MODULE_FORCE_LOAD is not set
221CONFIG_MODULE_UNLOAD=y
222# CONFIG_MODULE_FORCE_UNLOAD is not set
223# CONFIG_MODVERSIONS is not set
224# CONFIG_MODULE_SRCVERSION_ALL is not set
225CONFIG_KMOD=y
226CONFIG_BLOCK=y
227# CONFIG_LBD is not set
228# CONFIG_BLK_DEV_IO_TRACE is not set
229# CONFIG_LSF is not set
230# CONFIG_BLK_DEV_BSG is not set
231# CONFIG_BLK_DEV_INTEGRITY is not set
232
233#
234# IO Schedulers
235#
236CONFIG_IOSCHED_NOOP=y
237# CONFIG_IOSCHED_AS is not set
238# CONFIG_IOSCHED_DEADLINE is not set
239# CONFIG_IOSCHED_CFQ is not set
240# CONFIG_DEFAULT_AS is not set
241# CONFIG_DEFAULT_DEADLINE is not set
242# CONFIG_DEFAULT_CFQ is not set
243CONFIG_DEFAULT_NOOP=y
244CONFIG_DEFAULT_IOSCHED="noop"
245CONFIG_CLASSIC_RCU=y
246
247#
248# Bus options (PCI, PCMCIA, EISA, ISA, TC)
249#
250# CONFIG_ARCH_SUPPORTS_MSI is not set
251CONFIG_MMU=y
252# CONFIG_PCCARD is not set
253
254#
255# Executable file formats
256#
257CONFIG_BINFMT_ELF=y
258# CONFIG_BINFMT_MISC is not set
259CONFIG_TRAD_SIGNALS=y
260
261#
262# Power management options
263#
264CONFIG_ARCH_SUSPEND_POSSIBLE=y
265CONFIG_PM=y
266# CONFIG_PM_DEBUG is not set
267CONFIG_PM_SLEEP=y
268CONFIG_SUSPEND=y
269CONFIG_SUSPEND_FREEZER=y
270
271#
272# Networking
273#
274CONFIG_NET=y
275
276#
277# Networking options
278#
279CONFIG_PACKET=y
280# CONFIG_PACKET_MMAP is not set
281CONFIG_UNIX=y
282CONFIG_XFRM=y
283# CONFIG_XFRM_USER is not set
284# CONFIG_XFRM_SUB_POLICY is not set
285# CONFIG_XFRM_MIGRATE is not set
286# CONFIG_XFRM_STATISTICS is not set
287# CONFIG_NET_KEY is not set
288CONFIG_INET=y
289CONFIG_IP_MULTICAST=y
290# CONFIG_IP_ADVANCED_ROUTER is not set
291CONFIG_IP_FIB_HASH=y
292CONFIG_IP_PNP=y
293CONFIG_IP_PNP_DHCP=y
294# CONFIG_IP_PNP_BOOTP is not set
295# CONFIG_IP_PNP_RARP is not set
296# CONFIG_NET_IPIP is not set
297# CONFIG_NET_IPGRE is not set
298# CONFIG_IP_MROUTE is not set
299# CONFIG_ARPD is not set
300# CONFIG_SYN_COOKIES is not set
301CONFIG_INET_AH=y
302# CONFIG_INET_ESP is not set
303# CONFIG_INET_IPCOMP is not set
304# CONFIG_INET_XFRM_TUNNEL is not set
305# CONFIG_INET_TUNNEL is not set
306CONFIG_INET_XFRM_MODE_TRANSPORT=y
307CONFIG_INET_XFRM_MODE_TUNNEL=y
308CONFIG_INET_XFRM_MODE_BEET=y
309# CONFIG_INET_LRO is not set
310CONFIG_INET_DIAG=y
311CONFIG_INET_TCP_DIAG=y
312# CONFIG_TCP_CONG_ADVANCED is not set
313CONFIG_TCP_CONG_CUBIC=y
314CONFIG_DEFAULT_TCP_CONG="cubic"
315# CONFIG_TCP_MD5SIG is not set
316# CONFIG_IPV6 is not set
317# CONFIG_NETWORK_SECMARK is not set
318# CONFIG_NETFILTER is not set
319# CONFIG_IP_DCCP is not set
320# CONFIG_IP_SCTP is not set
321# CONFIG_TIPC is not set
322# CONFIG_ATM is not set
323# CONFIG_BRIDGE is not set
324# CONFIG_VLAN_8021Q is not set
325# CONFIG_DECNET is not set
326# CONFIG_LLC2 is not set
327# CONFIG_IPX is not set
328# CONFIG_ATALK is not set
329# CONFIG_X25 is not set
330# CONFIG_LAPB is not set
331# CONFIG_ECONET is not set
332# CONFIG_WAN_ROUTER is not set
333# CONFIG_NET_SCHED is not set
334
335#
336# Network testing
337#
338# CONFIG_NET_PKTGEN is not set
339# CONFIG_HAMRADIO is not set
340# CONFIG_CAN is not set
341# CONFIG_IRDA is not set
342# CONFIG_BT is not set
343# CONFIG_AF_RXRPC is not set
344
345#
346# Wireless
347#
348# CONFIG_CFG80211 is not set
349# CONFIG_WIRELESS_EXT is not set
350# CONFIG_MAC80211 is not set
351# CONFIG_IEEE80211 is not set
352# CONFIG_RFKILL is not set
353# CONFIG_NET_9P is not set
354
355#
356# Device Drivers
357#
358
359#
360# Generic Driver Options
361#
362CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
363CONFIG_STANDALONE=y
364CONFIG_PREVENT_FIRMWARE_BUILD=y
365CONFIG_FW_LOADER=y
366CONFIG_FIRMWARE_IN_KERNEL=y
367CONFIG_EXTRA_FIRMWARE=""
368# CONFIG_SYS_HYPERVISOR is not set
369# CONFIG_CONNECTOR is not set
370CONFIG_MTD=y
371# CONFIG_MTD_DEBUG is not set
372# CONFIG_MTD_CONCAT is not set
373CONFIG_MTD_PARTITIONS=y
374# CONFIG_MTD_REDBOOT_PARTS is not set
375CONFIG_MTD_CMDLINE_PARTS=y
376# CONFIG_MTD_AR7_PARTS is not set
377
378#
379# User Modules And Translation Layers
380#
381CONFIG_MTD_CHAR=y
382CONFIG_MTD_BLKDEVS=y
383CONFIG_MTD_BLOCK=y
384# CONFIG_FTL is not set
385# CONFIG_NFTL is not set
386# CONFIG_INFTL is not set
387# CONFIG_RFD_FTL is not set
388# CONFIG_SSFDC is not set
389# CONFIG_MTD_OOPS is not set
390
391#
392# RAM/ROM/Flash chip drivers
393#
394CONFIG_MTD_CFI=y
395# CONFIG_MTD_JEDECPROBE is not set
396CONFIG_MTD_GEN_PROBE=y
397CONFIG_MTD_CFI_ADV_OPTIONS=y
398# CONFIG_MTD_CFI_NOSWAP is not set
399# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
400CONFIG_MTD_CFI_LE_BYTE_SWAP=y
401CONFIG_MTD_CFI_GEOMETRY=y
402CONFIG_MTD_MAP_BANK_WIDTH_1=y
403CONFIG_MTD_MAP_BANK_WIDTH_2=y
404CONFIG_MTD_MAP_BANK_WIDTH_4=y
405# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
406# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
407# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
408CONFIG_MTD_CFI_I1=y
409CONFIG_MTD_CFI_I2=y
410# CONFIG_MTD_CFI_I4 is not set
411# CONFIG_MTD_CFI_I8 is not set
412# CONFIG_MTD_OTP is not set
413# CONFIG_MTD_CFI_INTELEXT is not set
414CONFIG_MTD_CFI_AMDSTD=y
415# CONFIG_MTD_CFI_STAA is not set
416CONFIG_MTD_CFI_UTIL=y
417# CONFIG_MTD_RAM is not set
418# CONFIG_MTD_ROM is not set
419# CONFIG_MTD_ABSENT is not set
420
421#
422# Mapping drivers for chip access
423#
424# CONFIG_MTD_COMPLEX_MAPPINGS is not set
425CONFIG_MTD_PHYSMAP=y
426CONFIG_MTD_PHYSMAP_START=0x18000000
427CONFIG_MTD_PHYSMAP_LEN=0x04000000
428CONFIG_MTD_PHYSMAP_BANKWIDTH=2
429# CONFIG_MTD_PLATRAM is not set
430
431#
432# Self-contained MTD device drivers
433#
434# CONFIG_MTD_SLRAM is not set
435# CONFIG_MTD_PHRAM is not set
436# CONFIG_MTD_MTDRAM is not set
437# CONFIG_MTD_BLOCK2MTD is not set
438
439#
440# Disk-On-Chip Device Drivers
441#
442# CONFIG_MTD_DOC2000 is not set
443# CONFIG_MTD_DOC2001 is not set
444# CONFIG_MTD_DOC2001PLUS is not set
445# CONFIG_MTD_NAND is not set
446# CONFIG_MTD_ONENAND is not set
447
448#
449# UBI - Unsorted block images
450#
451# CONFIG_MTD_UBI is not set
452# CONFIG_PARPORT is not set
453CONFIG_BLK_DEV=y
454# CONFIG_BLK_DEV_COW_COMMON is not set
455CONFIG_BLK_DEV_LOOP=y
456# CONFIG_BLK_DEV_CRYPTOLOOP is not set
457# CONFIG_BLK_DEV_NBD is not set
458# CONFIG_BLK_DEV_RAM is not set
459# CONFIG_CDROM_PKTCDVD is not set
460# CONFIG_ATA_OVER_ETH is not set
461# CONFIG_BLK_DEV_HD is not set
462# CONFIG_MISC_DEVICES is not set
463CONFIG_HAVE_IDE=y
464# CONFIG_IDE is not set
465
466#
467# SCSI device support
468#
469# CONFIG_RAID_ATTRS is not set
470CONFIG_SCSI=y
471CONFIG_SCSI_DMA=y
472# CONFIG_SCSI_TGT is not set
473# CONFIG_SCSI_NETLINK is not set
474CONFIG_SCSI_PROC_FS=y
475
476#
477# SCSI support type (disk, tape, CD-ROM)
478#
479CONFIG_BLK_DEV_SD=y
480# CONFIG_CHR_DEV_ST is not set
481# CONFIG_CHR_DEV_OSST is not set
482# CONFIG_BLK_DEV_SR is not set
483# CONFIG_CHR_DEV_SG is not set
484# CONFIG_CHR_DEV_SCH is not set
485
486#
487# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
488#
489# CONFIG_SCSI_MULTI_LUN is not set
490# CONFIG_SCSI_CONSTANTS is not set
491# CONFIG_SCSI_LOGGING is not set
492# CONFIG_SCSI_SCAN_ASYNC is not set
493CONFIG_SCSI_WAIT_SCAN=m
494
495#
496# SCSI Transports
497#
498# CONFIG_SCSI_SPI_ATTRS is not set
499# CONFIG_SCSI_FC_ATTRS is not set
500# CONFIG_SCSI_ISCSI_ATTRS is not set
501# CONFIG_SCSI_SAS_LIBSAS is not set
502# CONFIG_SCSI_SRP_ATTRS is not set
503# CONFIG_SCSI_LOWLEVEL is not set
504# CONFIG_SCSI_DH is not set
505CONFIG_ATA=y
506# CONFIG_ATA_NONSTANDARD is not set
507CONFIG_SATA_PMP=y
508CONFIG_ATA_SFF=y
509# CONFIG_SATA_MV is not set
510# CONFIG_PATA_PLATFORM is not set
511# CONFIG_MD is not set
512CONFIG_NETDEVICES=y
513# CONFIG_DUMMY is not set
514# CONFIG_BONDING is not set
515# CONFIG_MACVLAN is not set
516# CONFIG_EQUALIZER is not set
517# CONFIG_TUN is not set
518# CONFIG_VETH is not set
519# CONFIG_PHYLIB is not set
520CONFIG_NET_ETHERNET=y
521CONFIG_MII=y
522# CONFIG_AX88796 is not set
523# CONFIG_DM9000 is not set
524# CONFIG_IBM_NEW_EMAC_ZMII is not set
525# CONFIG_IBM_NEW_EMAC_RGMII is not set
526# CONFIG_IBM_NEW_EMAC_TAH is not set
527# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
528# CONFIG_B44 is not set
529# CONFIG_NETDEV_1000 is not set
530# CONFIG_NETDEV_10000 is not set
531
532#
533# Wireless LAN
534#
535# CONFIG_WLAN_PRE80211 is not set
536# CONFIG_WLAN_80211 is not set
537# CONFIG_IWLWIFI_LEDS is not set
538# CONFIG_WAN is not set
539# CONFIG_PPP is not set
540# CONFIG_SLIP is not set
541# CONFIG_NETCONSOLE is not set
542# CONFIG_NETPOLL is not set
543# CONFIG_NET_POLL_CONTROLLER is not set
544# CONFIG_ISDN is not set
545# CONFIG_PHONE is not set
546
547#
548# Input device support
549#
550CONFIG_INPUT=y
551# CONFIG_INPUT_FF_MEMLESS is not set
552# CONFIG_INPUT_POLLDEV is not set
553
554#
555# Userland interfaces
556#
557# CONFIG_INPUT_MOUSEDEV is not set
558# CONFIG_INPUT_JOYDEV is not set
559CONFIG_INPUT_EVDEV=m
560CONFIG_INPUT_EVBUG=m
561
562#
563# Input Device Drivers
564#
565# CONFIG_INPUT_KEYBOARD is not set
566# CONFIG_INPUT_MOUSE is not set
567# CONFIG_INPUT_JOYSTICK is not set
568# CONFIG_INPUT_TABLET is not set
569# CONFIG_INPUT_TOUCHSCREEN is not set
570# CONFIG_INPUT_MISC is not set
571
572#
573# Hardware I/O ports
574#
575CONFIG_SERIO=y
576# CONFIG_SERIO_I8042 is not set
577CONFIG_SERIO_SERPORT=y
578# CONFIG_SERIO_LIBPS2 is not set
579# CONFIG_SERIO_RAW is not set
580# CONFIG_GAMEPORT is not set
581
582#
583# Character devices
584#
585CONFIG_VT=y
586CONFIG_CONSOLE_TRANSLATIONS=y
587# CONFIG_VT_CONSOLE is not set
588CONFIG_HW_CONSOLE=y
589# CONFIG_VT_HW_CONSOLE_BINDING is not set
590CONFIG_DEVKMEM=y
591# CONFIG_SERIAL_NONSTANDARD is not set
592
593#
594# Serial drivers
595#
596# CONFIG_SERIAL_8250 is not set
597
598#
599# Non-8250 serial port support
600#
601CONFIG_SERIAL_PNX8XXX=y
602CONFIG_SERIAL_PNX8XXX_CONSOLE=y
603CONFIG_SERIAL_CORE=y
604CONFIG_SERIAL_CORE_CONSOLE=y
605CONFIG_UNIX98_PTYS=y
606# CONFIG_LEGACY_PTYS is not set
607# CONFIG_IPMI_HANDLER is not set
608CONFIG_HW_RANDOM=y
609# CONFIG_R3964 is not set
610# CONFIG_RAW_DRIVER is not set
611# CONFIG_TCG_TPM is not set
612CONFIG_I2C=y
613CONFIG_I2C_BOARDINFO=y
614CONFIG_I2C_CHARDEV=y
615
616#
617# I2C Hardware Bus support
618#
619
620#
621# I2C system bus drivers (mostly embedded / system-on-chip)
622#
623# CONFIG_I2C_GPIO is not set
624# CONFIG_I2C_OCORES is not set
625# CONFIG_I2C_SIMTEC is not set
626
627#
628# External I2C/SMBus adapter drivers
629#
630# CONFIG_I2C_PARPORT_LIGHT is not set
631# CONFIG_I2C_TAOS_EVM is not set
632
633#
634# Other I2C/SMBus bus drivers
635#
636# CONFIG_I2C_PCA_PLATFORM is not set
637# CONFIG_I2C_STUB is not set
638
639#
640# Miscellaneous I2C Chip support
641#
642# CONFIG_DS1682 is not set
643# CONFIG_AT24 is not set
644# CONFIG_SENSORS_EEPROM is not set
645# CONFIG_SENSORS_PCF8574 is not set
646# CONFIG_PCF8575 is not set
647# CONFIG_SENSORS_PCA9539 is not set
648# CONFIG_SENSORS_PCF8591 is not set
649# CONFIG_SENSORS_MAX6875 is not set
650# CONFIG_SENSORS_TSL2550 is not set
651# CONFIG_I2C_DEBUG_CORE is not set
652# CONFIG_I2C_DEBUG_ALGO is not set
653# CONFIG_I2C_DEBUG_BUS is not set
654# CONFIG_I2C_DEBUG_CHIP is not set
655# CONFIG_SPI is not set
656# CONFIG_W1 is not set
657# CONFIG_POWER_SUPPLY is not set
658# CONFIG_HWMON is not set
659# CONFIG_THERMAL is not set
660# CONFIG_THERMAL_HWMON is not set
661# CONFIG_WATCHDOG is not set
662
663#
664# Sonics Silicon Backplane
665#
666CONFIG_SSB_POSSIBLE=y
667# CONFIG_SSB is not set
668
669#
670# Multifunction device drivers
671#
672# CONFIG_MFD_CORE is not set
673# CONFIG_MFD_SM501 is not set
674# CONFIG_HTC_PASIC3 is not set
675
676#
677# Multimedia devices
678#
679
680#
681# Multimedia core support
682#
683# CONFIG_VIDEO_DEV is not set
684CONFIG_DVB_CORE=y
685CONFIG_VIDEO_MEDIA=y
686
687#
688# Multimedia drivers
689#
690# CONFIG_MEDIA_ATTACH is not set
691CONFIG_MEDIA_TUNER=y
692# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
693CONFIG_MEDIA_TUNER_SIMPLE=y
694CONFIG_MEDIA_TUNER_TDA8290=y
695CONFIG_MEDIA_TUNER_TDA9887=y
696CONFIG_MEDIA_TUNER_TEA5761=y
697CONFIG_MEDIA_TUNER_TEA5767=y
698CONFIG_MEDIA_TUNER_MT20XX=y
699CONFIG_MEDIA_TUNER_XC2028=y
700CONFIG_MEDIA_TUNER_XC5000=y
701CONFIG_DVB_CAPTURE_DRIVERS=y
702# CONFIG_TTPCI_EEPROM is not set
703# CONFIG_DVB_B2C2_FLEXCOP is not set
704
705#
706# Supported DVB Frontends
707#
708
709#
710# Customise DVB Frontends
711#
712# CONFIG_DVB_FE_CUSTOMISE is not set
713
714#
715# DVB-S (satellite) frontends
716#
717# CONFIG_DVB_CX24110 is not set
718# CONFIG_DVB_CX24123 is not set
719# CONFIG_DVB_MT312 is not set
720# CONFIG_DVB_S5H1420 is not set
721# CONFIG_DVB_STV0299 is not set
722# CONFIG_DVB_TDA8083 is not set
723# CONFIG_DVB_TDA10086 is not set
724# CONFIG_DVB_VES1X93 is not set
725# CONFIG_DVB_TUNER_ITD1000 is not set
726# CONFIG_DVB_TDA826X is not set
727# CONFIG_DVB_TUA6100 is not set
728
729#
730# DVB-T (terrestrial) frontends
731#
732# CONFIG_DVB_SP8870 is not set
733# CONFIG_DVB_SP887X is not set
734# CONFIG_DVB_CX22700 is not set
735# CONFIG_DVB_CX22702 is not set
736# CONFIG_DVB_DRX397XD is not set
737# CONFIG_DVB_L64781 is not set
738CONFIG_DVB_TDA1004X=y
739# CONFIG_DVB_NXT6000 is not set
740# CONFIG_DVB_MT352 is not set
741# CONFIG_DVB_ZL10353 is not set
742# CONFIG_DVB_DIB3000MB is not set
743# CONFIG_DVB_DIB3000MC is not set
744# CONFIG_DVB_DIB7000M is not set
745# CONFIG_DVB_DIB7000P is not set
746# CONFIG_DVB_TDA10048 is not set
747
748#
749# DVB-C (cable) frontends
750#
751# CONFIG_DVB_VES1820 is not set
752# CONFIG_DVB_TDA10021 is not set
753# CONFIG_DVB_TDA10023 is not set
754# CONFIG_DVB_STV0297 is not set
755
756#
757# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
758#
759# CONFIG_DVB_NXT200X is not set
760# CONFIG_DVB_OR51211 is not set
761# CONFIG_DVB_OR51132 is not set
762# CONFIG_DVB_BCM3510 is not set
763# CONFIG_DVB_LGDT330X is not set
764# CONFIG_DVB_S5H1409 is not set
765# CONFIG_DVB_AU8522 is not set
766# CONFIG_DVB_S5H1411 is not set
767
768#
769# Digital terrestrial only tuners/PLL
770#
771# CONFIG_DVB_PLL is not set
772# CONFIG_DVB_TUNER_DIB0070 is not set
773
774#
775# SEC control devices for DVB-S
776#
777# CONFIG_DVB_LNBP21 is not set
778# CONFIG_DVB_ISL6405 is not set
779# CONFIG_DVB_ISL6421 is not set
780# CONFIG_DAB is not set
781
782#
783# Graphics support
784#
785# CONFIG_VGASTATE is not set
786# CONFIG_VIDEO_OUTPUT_CONTROL is not set
787CONFIG_FB=y
788# CONFIG_FIRMWARE_EDID is not set
789# CONFIG_FB_DDC is not set
790# CONFIG_FB_CFB_FILLRECT is not set
791# CONFIG_FB_CFB_COPYAREA is not set
792# CONFIG_FB_CFB_IMAGEBLIT is not set
793# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
794# CONFIG_FB_SYS_FILLRECT is not set
795# CONFIG_FB_SYS_COPYAREA is not set
796# CONFIG_FB_SYS_IMAGEBLIT is not set
797# CONFIG_FB_FOREIGN_ENDIAN is not set
798# CONFIG_FB_SYS_FOPS is not set
799# CONFIG_FB_SVGALIB is not set
800# CONFIG_FB_MACMODES is not set
801# CONFIG_FB_BACKLIGHT is not set
802# CONFIG_FB_MODE_HELPERS is not set
803# CONFIG_FB_TILEBLITTING is not set
804
805#
806# Frame buffer hardware drivers
807#
808# CONFIG_FB_S1D13XXX is not set
809# CONFIG_FB_VIRTUAL is not set
810# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
811
812#
813# Display device support
814#
815# CONFIG_DISPLAY_SUPPORT is not set
816
817#
818# Console display driver support
819#
820# CONFIG_VGA_CONSOLE is not set
821CONFIG_DUMMY_CONSOLE=y
822# CONFIG_FRAMEBUFFER_CONSOLE is not set
823# CONFIG_LOGO is not set
824CONFIG_SOUND=m
825CONFIG_SND=m
826CONFIG_SND_TIMER=m
827CONFIG_SND_PCM=m
828CONFIG_SND_SEQUENCER=m
829# CONFIG_SND_SEQ_DUMMY is not set
830CONFIG_SND_OSSEMUL=y
831CONFIG_SND_MIXER_OSS=m
832CONFIG_SND_PCM_OSS=m
833CONFIG_SND_PCM_OSS_PLUGINS=y
834CONFIG_SND_SEQUENCER_OSS=y
835# CONFIG_SND_DYNAMIC_MINORS is not set
836CONFIG_SND_SUPPORT_OLD_API=y
837CONFIG_SND_VERBOSE_PROCFS=y
838CONFIG_SND_VERBOSE_PRINTK=y
839CONFIG_SND_DEBUG=y
840# CONFIG_SND_DEBUG_VERBOSE is not set
841# CONFIG_SND_PCM_XRUN_DEBUG is not set
842CONFIG_SND_DRIVERS=y
843# CONFIG_SND_DUMMY is not set
844# CONFIG_SND_VIRMIDI is not set
845# CONFIG_SND_MTPAV is not set
846# CONFIG_SND_SERIAL_U16550 is not set
847# CONFIG_SND_MPU401 is not set
848CONFIG_SND_MIPS=y
849# CONFIG_SND_SOC is not set
850# CONFIG_SOUND_PRIME is not set
851CONFIG_HID_SUPPORT=y
852CONFIG_HID=y
853# CONFIG_HID_DEBUG is not set
854# CONFIG_HIDRAW is not set
855CONFIG_USB_SUPPORT=y
856# CONFIG_USB_ARCH_HAS_HCD is not set
857# CONFIG_USB_ARCH_HAS_OHCI is not set
858# CONFIG_USB_ARCH_HAS_EHCI is not set
859# CONFIG_USB_OTG_WHITELIST is not set
860# CONFIG_USB_OTG_BLACKLIST_HUB is not set
861
862#
863# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
864#
865# CONFIG_USB_GADGET is not set
866# CONFIG_MMC is not set
867# CONFIG_MEMSTICK is not set
868# CONFIG_NEW_LEDS is not set
869# CONFIG_ACCESSIBILITY is not set
870CONFIG_RTC_LIB=y
871# CONFIG_RTC_CLASS is not set
872# CONFIG_DMADEVICES is not set
873# CONFIG_UIO is not set
874
875#
876# File systems
877#
878CONFIG_EXT2_FS=m
879# CONFIG_EXT2_FS_XATTR is not set
880# CONFIG_EXT2_FS_XIP is not set
881# CONFIG_EXT3_FS is not set
882# CONFIG_EXT4DEV_FS is not set
883# CONFIG_REISERFS_FS is not set
884# CONFIG_JFS_FS is not set
885# CONFIG_FS_POSIX_ACL is not set
886# CONFIG_XFS_FS is not set
887# CONFIG_OCFS2_FS is not set
888# CONFIG_DNOTIFY is not set
889CONFIG_INOTIFY=y
890CONFIG_INOTIFY_USER=y
891# CONFIG_QUOTA is not set
892# CONFIG_AUTOFS_FS is not set
893# CONFIG_AUTOFS4_FS is not set
894# CONFIG_FUSE_FS is not set
895
896#
897# CD-ROM/DVD Filesystems
898#
899# CONFIG_ISO9660_FS is not set
900# CONFIG_UDF_FS is not set
901
902#
903# DOS/FAT/NT Filesystems
904#
905CONFIG_FAT_FS=m
906CONFIG_MSDOS_FS=m
907CONFIG_VFAT_FS=m
908CONFIG_FAT_DEFAULT_CODEPAGE=437
909CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
910# CONFIG_NTFS_FS is not set
911
912#
913# Pseudo filesystems
914#
915CONFIG_PROC_FS=y
916# CONFIG_PROC_KCORE is not set
917CONFIG_PROC_SYSCTL=y
918CONFIG_SYSFS=y
919CONFIG_TMPFS=y
920# CONFIG_TMPFS_POSIX_ACL is not set
921# CONFIG_HUGETLB_PAGE is not set
922# CONFIG_CONFIGFS_FS is not set
923
924#
925# Miscellaneous filesystems
926#
927# CONFIG_ADFS_FS is not set
928# CONFIG_AFFS_FS is not set
929# CONFIG_HFS_FS is not set
930# CONFIG_HFSPLUS_FS is not set
931# CONFIG_BEFS_FS is not set
932# CONFIG_BFS_FS is not set
933# CONFIG_EFS_FS is not set
934CONFIG_JFFS2_FS=y
935CONFIG_JFFS2_FS_DEBUG=0
936CONFIG_JFFS2_FS_WRITEBUFFER=y
937# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
938# CONFIG_JFFS2_SUMMARY is not set
939# CONFIG_JFFS2_FS_XATTR is not set
940# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
941CONFIG_JFFS2_ZLIB=y
942# CONFIG_JFFS2_LZO is not set
943CONFIG_JFFS2_RTIME=y
944# CONFIG_JFFS2_RUBIN is not set
945CONFIG_CRAMFS=y
946# CONFIG_VXFS_FS is not set
947# CONFIG_MINIX_FS is not set
948# CONFIG_HPFS_FS is not set
949# CONFIG_QNX4FS_FS is not set
950# CONFIG_ROMFS_FS is not set
951# CONFIG_SYSV_FS is not set
952# CONFIG_UFS_FS is not set
953CONFIG_NETWORK_FILESYSTEMS=y
954CONFIG_NFS_FS=y
955CONFIG_NFS_V3=y
956# CONFIG_NFS_V3_ACL is not set
957# CONFIG_NFS_V4 is not set
958CONFIG_ROOT_NFS=y
959CONFIG_NFSD=m
960CONFIG_NFSD_V3=y
961# CONFIG_NFSD_V3_ACL is not set
962# CONFIG_NFSD_V4 is not set
963CONFIG_LOCKD=y
964CONFIG_LOCKD_V4=y
965CONFIG_EXPORTFS=m
966CONFIG_NFS_COMMON=y
967CONFIG_SUNRPC=y
968# CONFIG_RPCSEC_GSS_KRB5 is not set
969# CONFIG_RPCSEC_GSS_SPKM3 is not set
970# CONFIG_SMB_FS is not set
971# CONFIG_CIFS is not set
972# CONFIG_NCP_FS is not set
973# CONFIG_CODA_FS is not set
974# CONFIG_AFS_FS is not set
975
976#
977# Partition Types
978#
979# CONFIG_PARTITION_ADVANCED is not set
980CONFIG_MSDOS_PARTITION=y
981CONFIG_NLS=y
982CONFIG_NLS_DEFAULT="iso8859-1"
983CONFIG_NLS_CODEPAGE_437=m
984# CONFIG_NLS_CODEPAGE_737 is not set
985# CONFIG_NLS_CODEPAGE_775 is not set
986CONFIG_NLS_CODEPAGE_850=m
987# CONFIG_NLS_CODEPAGE_852 is not set
988# CONFIG_NLS_CODEPAGE_855 is not set
989# CONFIG_NLS_CODEPAGE_857 is not set
990# CONFIG_NLS_CODEPAGE_860 is not set
991# CONFIG_NLS_CODEPAGE_861 is not set
992# CONFIG_NLS_CODEPAGE_862 is not set
993# CONFIG_NLS_CODEPAGE_863 is not set
994# CONFIG_NLS_CODEPAGE_864 is not set
995# CONFIG_NLS_CODEPAGE_865 is not set
996# CONFIG_NLS_CODEPAGE_866 is not set
997# CONFIG_NLS_CODEPAGE_869 is not set
998# CONFIG_NLS_CODEPAGE_936 is not set
999# CONFIG_NLS_CODEPAGE_950 is not set
1000CONFIG_NLS_CODEPAGE_932=m
1001# CONFIG_NLS_CODEPAGE_949 is not set
1002# CONFIG_NLS_CODEPAGE_874 is not set
1003# CONFIG_NLS_ISO8859_8 is not set
1004# CONFIG_NLS_CODEPAGE_1250 is not set
1005# CONFIG_NLS_CODEPAGE_1251 is not set
1006CONFIG_NLS_ASCII=m
1007CONFIG_NLS_ISO8859_1=m
1008# CONFIG_NLS_ISO8859_2 is not set
1009# CONFIG_NLS_ISO8859_3 is not set
1010# CONFIG_NLS_ISO8859_4 is not set
1011# CONFIG_NLS_ISO8859_5 is not set
1012# CONFIG_NLS_ISO8859_6 is not set
1013# CONFIG_NLS_ISO8859_7 is not set
1014# CONFIG_NLS_ISO8859_9 is not set
1015# CONFIG_NLS_ISO8859_13 is not set
1016# CONFIG_NLS_ISO8859_14 is not set
1017CONFIG_NLS_ISO8859_15=m
1018# CONFIG_NLS_KOI8_R is not set
1019# CONFIG_NLS_KOI8_U is not set
1020CONFIG_NLS_UTF8=m
1021# CONFIG_DLM is not set
1022
1023#
1024# Kernel hacking
1025#
1026CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1027# CONFIG_PRINTK_TIME is not set
1028CONFIG_ENABLE_WARN_DEPRECATED=y
1029CONFIG_ENABLE_MUST_CHECK=y
1030CONFIG_FRAME_WARN=1024
1031# CONFIG_MAGIC_SYSRQ is not set
1032# CONFIG_UNUSED_SYMBOLS is not set
1033# CONFIG_DEBUG_FS is not set
1034# CONFIG_HEADERS_CHECK is not set
1035# CONFIG_DEBUG_KERNEL is not set
1036# CONFIG_SAMPLES is not set
1037# CONFIG_KERNEL_TESTS is not set
1038CONFIG_CMDLINE=""
1039
1040#
1041# Security options
1042#
1043# CONFIG_KEYS is not set
1044# CONFIG_SECURITY is not set
1045# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1046CONFIG_CRYPTO=y
1047
1048#
1049# Crypto core or helper
1050#
1051CONFIG_CRYPTO_ALGAPI=y
1052CONFIG_CRYPTO_HASH=y
1053CONFIG_CRYPTO_MANAGER=y
1054# CONFIG_CRYPTO_GF128MUL is not set
1055# CONFIG_CRYPTO_NULL is not set
1056# CONFIG_CRYPTO_CRYPTD is not set
1057# CONFIG_CRYPTO_AUTHENC is not set
1058# CONFIG_CRYPTO_TEST is not set
1059
1060#
1061# Authenticated Encryption with Associated Data
1062#
1063# CONFIG_CRYPTO_CCM is not set
1064# CONFIG_CRYPTO_GCM is not set
1065# CONFIG_CRYPTO_SEQIV is not set
1066
1067#
1068# Block modes
1069#
1070# CONFIG_CRYPTO_CBC is not set
1071# CONFIG_CRYPTO_CTR is not set
1072# CONFIG_CRYPTO_CTS is not set
1073# CONFIG_CRYPTO_ECB is not set
1074# CONFIG_CRYPTO_LRW is not set
1075# CONFIG_CRYPTO_PCBC is not set
1076# CONFIG_CRYPTO_XTS is not set
1077
1078#
1079# Hash modes
1080#
1081CONFIG_CRYPTO_HMAC=y
1082# CONFIG_CRYPTO_XCBC is not set
1083
1084#
1085# Digest
1086#
1087# CONFIG_CRYPTO_CRC32C is not set
1088# CONFIG_CRYPTO_MD4 is not set
1089CONFIG_CRYPTO_MD5=y
1090# CONFIG_CRYPTO_MICHAEL_MIC is not set
1091# CONFIG_CRYPTO_RMD128 is not set
1092# CONFIG_CRYPTO_RMD160 is not set
1093# CONFIG_CRYPTO_RMD256 is not set
1094# CONFIG_CRYPTO_RMD320 is not set
1095CONFIG_CRYPTO_SHA1=y
1096# CONFIG_CRYPTO_SHA256 is not set
1097# CONFIG_CRYPTO_SHA512 is not set
1098# CONFIG_CRYPTO_TGR192 is not set
1099# CONFIG_CRYPTO_WP512 is not set
1100
1101#
1102# Ciphers
1103#
1104# CONFIG_CRYPTO_AES is not set
1105# CONFIG_CRYPTO_ANUBIS is not set
1106# CONFIG_CRYPTO_ARC4 is not set
1107# CONFIG_CRYPTO_BLOWFISH is not set
1108# CONFIG_CRYPTO_CAMELLIA is not set
1109# CONFIG_CRYPTO_CAST5 is not set
1110# CONFIG_CRYPTO_CAST6 is not set
1111# CONFIG_CRYPTO_DES is not set
1112# CONFIG_CRYPTO_FCRYPT is not set
1113# CONFIG_CRYPTO_KHAZAD is not set
1114# CONFIG_CRYPTO_SALSA20 is not set
1115# CONFIG_CRYPTO_SEED is not set
1116# CONFIG_CRYPTO_SERPENT is not set
1117# CONFIG_CRYPTO_TEA is not set
1118# CONFIG_CRYPTO_TWOFISH is not set
1119
1120#
1121# Compression
1122#
1123# CONFIG_CRYPTO_DEFLATE is not set
1124# CONFIG_CRYPTO_LZO is not set
1125
1126#
1127# Random Number Generation
1128#
1129# CONFIG_CRYPTO_PRNG is not set
1130CONFIG_CRYPTO_HW=y
1131
1132#
1133# Library routines
1134#
1135CONFIG_BITREVERSE=y
1136# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1137# CONFIG_CRC_CCITT is not set
1138# CONFIG_CRC16 is not set
1139# CONFIG_CRC_T10DIF is not set
1140# CONFIG_CRC_ITU_T is not set
1141CONFIG_CRC32=y
1142# CONFIG_CRC7 is not set
1143# CONFIG_LIBCRC32C is not set
1144CONFIG_ZLIB_INFLATE=y
1145CONFIG_ZLIB_DEFLATE=y
1146CONFIG_PLIST=y
1147CONFIG_HAS_IOMEM=y
1148CONFIG_HAS_IOPORT=y
1149CONFIG_HAS_DMA=y
diff --git a/arch/mips/emma/Kconfig b/arch/mips/emma/Kconfig
new file mode 100644
index 000000000000..9669c72123c9
--- /dev/null
+++ b/arch/mips/emma/Kconfig
@@ -0,0 +1,29 @@
1choice
2 prompt "Machine type"
3 depends on MACH_EMMA
4 default NEC_MARKEINS
5
6config NEC_MARKEINS
7 bool "NEC EMMA2RH Mark-eins board"
8 select SOC_EMMA2RH
9 select HW_HAS_PCI
10 help
11 This enables support for the NEC Electronics Mark-eins boards.
12
13endchoice
14
15config SOC_EMMA2RH
16 bool
17 select SOC_EMMA
18 select SYS_HAS_CPU_R5500
19 select SYS_SUPPORTS_32BIT_KERNEL
20 select SYS_SUPPORTS_64BIT_KERNEL
21
22config SOC_EMMA
23 bool
24 select CEVT_R4K
25 select CSRC_R4K
26 select DMA_NONCOHERENT
27 select IRQ_CPU
28 select SWAP_IO_SPACE
29 select SYS_SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/emma2rh/common/Makefile b/arch/mips/emma/common/Makefile
index 859121b3867d..c392d28c1ef1 100644
--- a/arch/mips/emma2rh/common/Makefile
+++ b/arch/mips/emma/common/Makefile
@@ -10,4 +10,4 @@
10# (at your option) any later version. 10# (at your option) any later version.
11# 11#
12 12
13obj-$(CONFIG_MARKEINS) += irq.o irq_emma2rh.o prom.o 13obj-$(CONFIG_NEC_MARKEINS) += prom.o
diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma/common/prom.c
index e14a2e3d8842..120f53fbdb45 100644
--- a/arch/mips/emma2rh/common/prom.c
+++ b/arch/mips/emma/common/prom.c
@@ -29,11 +29,11 @@
29 29
30#include <asm/addrspace.h> 30#include <asm/addrspace.h>
31#include <asm/bootinfo.h> 31#include <asm/bootinfo.h>
32#include <asm/emma2rh/emma2rh.h> 32#include <asm/emma/emma2rh.h>
33 33
34const char *get_system_type(void) 34const char *get_system_type(void)
35{ 35{
36#if defined(CONFIG_MARKEINS) 36#ifdef CONFIG_NEC_MARKEINS
37 return "NEC EMMA2RH Mark-eins"; 37 return "NEC EMMA2RH Mark-eins";
38#else 38#else
39#error Unknown NEC board 39#error Unknown NEC board
@@ -60,7 +60,7 @@ void __init prom_init(void)
60 strcat(arcs_cmdline, " "); 60 strcat(arcs_cmdline, " ");
61 } 61 }
62 62
63#if defined(CONFIG_MARKEINS) 63#ifdef CONFIG_NEC_MARKEINS
64 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); 64 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
65#else 65#else
66#error Unknown NEC board 66#error Unknown NEC board
diff --git a/arch/mips/emma2rh/markeins/Makefile b/arch/mips/emma/markeins/Makefile
index 14fc268b175c..16e0017ba919 100644
--- a/arch/mips/emma2rh/markeins/Makefile
+++ b/arch/mips/emma/markeins/Makefile
@@ -10,4 +10,4 @@
10# (at your option) any later version. 10# (at your option) any later version.
11# 11#
12 12
13obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o 13obj-$(CONFIG_NEC_MARKEINS) += irq.o setup.o led.o platform.o
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
new file mode 100644
index 000000000000..c2583ecc93cf
--- /dev/null
+++ b/arch/mips/emma/markeins/irq.c
@@ -0,0 +1,331 @@
1/*
2 * arch/mips/emma2rh/markeins/irq.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/types.h>
29#include <linux/ptrace.h>
30#include <linux/delay.h>
31
32#include <asm/irq_cpu.h>
33#include <asm/system.h>
34#include <asm/mipsregs.h>
35#include <asm/addrspace.h>
36#include <asm/bootinfo.h>
37
38#include <asm/emma/emma2rh.h>
39
40static void emma2rh_irq_enable(unsigned int irq)
41{
42 u32 reg_value;
43 u32 reg_bitmask;
44 u32 reg_index;
45
46 irq -= EMMA2RH_IRQ_BASE;
47
48 reg_index = EMMA2RH_BHIF_INT_EN_0 +
49 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
50 reg_value = emma2rh_in32(reg_index);
51 reg_bitmask = 0x1 << (irq % 32);
52 emma2rh_out32(reg_index, reg_value | reg_bitmask);
53}
54
55static void emma2rh_irq_disable(unsigned int irq)
56{
57 u32 reg_value;
58 u32 reg_bitmask;
59 u32 reg_index;
60
61 irq -= EMMA2RH_IRQ_BASE;
62
63 reg_index = EMMA2RH_BHIF_INT_EN_0 +
64 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
65 reg_value = emma2rh_in32(reg_index);
66 reg_bitmask = 0x1 << (irq % 32);
67 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
68}
69
70struct irq_chip emma2rh_irq_controller = {
71 .name = "emma2rh_irq",
72 .ack = emma2rh_irq_disable,
73 .mask = emma2rh_irq_disable,
74 .mask_ack = emma2rh_irq_disable,
75 .unmask = emma2rh_irq_enable,
76};
77
78void emma2rh_irq_init(void)
79{
80 u32 i;
81
82 for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
83 set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
84 &emma2rh_irq_controller,
85 handle_level_irq);
86}
87
88static void emma2rh_sw_irq_enable(unsigned int irq)
89{
90 u32 reg;
91
92 irq -= EMMA2RH_SW_IRQ_BASE;
93
94 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
95 reg |= 1 << irq;
96 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
97}
98
99static void emma2rh_sw_irq_disable(unsigned int irq)
100{
101 u32 reg;
102
103 irq -= EMMA2RH_SW_IRQ_BASE;
104
105 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
106 reg &= ~(1 << irq);
107 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
108}
109
110struct irq_chip emma2rh_sw_irq_controller = {
111 .name = "emma2rh_sw_irq",
112 .ack = emma2rh_sw_irq_disable,
113 .mask = emma2rh_sw_irq_disable,
114 .mask_ack = emma2rh_sw_irq_disable,
115 .unmask = emma2rh_sw_irq_enable,
116};
117
118void emma2rh_sw_irq_init(void)
119{
120 u32 i;
121
122 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
123 set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
124 &emma2rh_sw_irq_controller,
125 handle_level_irq);
126}
127
128static void emma2rh_gpio_irq_enable(unsigned int irq)
129{
130 u32 reg;
131
132 irq -= EMMA2RH_GPIO_IRQ_BASE;
133
134 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
135 reg |= 1 << irq;
136 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
137}
138
139static void emma2rh_gpio_irq_disable(unsigned int irq)
140{
141 u32 reg;
142
143 irq -= EMMA2RH_GPIO_IRQ_BASE;
144
145 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
146 reg &= ~(1 << irq);
147 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
148}
149
150static void emma2rh_gpio_irq_ack(unsigned int irq)
151{
152 u32 reg;
153
154 irq -= EMMA2RH_GPIO_IRQ_BASE;
155 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
156
157 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
158 reg &= ~(1 << irq);
159 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
160}
161
162static void emma2rh_gpio_irq_end(unsigned int irq)
163{
164 u32 reg;
165
166 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
167
168 irq -= EMMA2RH_GPIO_IRQ_BASE;
169
170 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
171 reg |= 1 << irq;
172 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
173 }
174}
175
176struct irq_chip emma2rh_gpio_irq_controller = {
177 .name = "emma2rh_gpio_irq",
178 .ack = emma2rh_gpio_irq_ack,
179 .mask = emma2rh_gpio_irq_disable,
180 .mask_ack = emma2rh_gpio_irq_ack,
181 .unmask = emma2rh_gpio_irq_enable,
182 .end = emma2rh_gpio_irq_end,
183};
184
185void emma2rh_gpio_irq_init(void)
186{
187 u32 i;
188
189 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
190 set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
191 &emma2rh_gpio_irq_controller);
192}
193
194static struct irqaction irq_cascade = {
195 .handler = no_action,
196 .flags = 0,
197 .mask = CPU_MASK_NONE,
198 .name = "cascade",
199 .dev_id = NULL,
200 .next = NULL,
201};
202
203/*
204 * the first level int-handler will jump here if it is a emma2rh irq
205 */
206void emma2rh_irq_dispatch(void)
207{
208 u32 intStatus;
209 u32 bitmask;
210 u32 i;
211
212 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
213 emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
214
215#ifdef EMMA2RH_SW_CASCADE
216 if (intStatus &
217 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
218 u32 swIntStatus;
219 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
220 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
221 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
222 if (swIntStatus & bitmask) {
223 do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
224 return;
225 }
226 }
227 }
228#endif
229
230 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
231 if (intStatus & bitmask) {
232 do_IRQ(EMMA2RH_IRQ_BASE + i);
233 return;
234 }
235 }
236
237 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
238 emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
239
240#ifdef EMMA2RH_GPIO_CASCADE
241 if (intStatus &
242 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
243 u32 gpioIntStatus;
244 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
245 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
246 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
247 if (gpioIntStatus & bitmask) {
248 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
249 return;
250 }
251 }
252 }
253#endif
254
255 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
256 if (intStatus & bitmask) {
257 do_IRQ(EMMA2RH_IRQ_BASE + i);
258 return;
259 }
260 }
261
262 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
263 emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
264
265 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
266 if (intStatus & bitmask) {
267 do_IRQ(EMMA2RH_IRQ_BASE + i);
268 return;
269 }
270 }
271}
272
273void __init arch_init_irq(void)
274{
275 u32 reg;
276
277 /* by default, interrupts are disabled. */
278 emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
279 emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
280 emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
281 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
282 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
283 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
284 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
285
286 clear_c0_status(0xff00);
287 set_c0_status(0x0400);
288
289#define GPIO_PCI (0xf<<15)
290 /* setup GPIO interrupt for PCI interface */
291 /* direction input */
292 reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
293 emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
294 /* disable interrupt */
295 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
296 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
297 /* level triggerd */
298 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
299 emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
300 reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
301 emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
302 /* interrupt clear */
303 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
304
305 /* init all controllers */
306 emma2rh_irq_init();
307 emma2rh_sw_irq_init();
308 emma2rh_gpio_irq_init();
309 mips_cpu_irq_init();
310
311 /* setup cascade interrupts */
312 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
313 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
314 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
315}
316
317asmlinkage void plat_irq_dispatch(void)
318{
319 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
320
321 if (pending & STATUSF_IP7)
322 do_IRQ(CPU_IRQ_BASE + 7);
323 else if (pending & STATUSF_IP2)
324 emma2rh_irq_dispatch();
325 else if (pending & STATUSF_IP1)
326 do_IRQ(CPU_IRQ_BASE + 1);
327 else if (pending & STATUSF_IP0)
328 do_IRQ(CPU_IRQ_BASE + 0);
329 else
330 spurious_interrupt();
331}
diff --git a/arch/mips/emma2rh/markeins/led.c b/arch/mips/emma/markeins/led.c
index b65254c1bfe9..377a181b6561 100644
--- a/arch/mips/emma2rh/markeins/led.c
+++ b/arch/mips/emma/markeins/led.c
@@ -21,7 +21,7 @@
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/types.h> 22#include <linux/types.h>
23#include <linux/string.h> 23#include <linux/string.h>
24#include <asm/emma2rh/emma2rh.h> 24#include <asm/emma/emma2rh.h>
25 25
26const unsigned long clear = 0x20202020; 26const unsigned long clear = 0x20202020;
27 27
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma/markeins/platform.c
index fb9cda253ab0..88e87f6b3442 100644
--- a/arch/mips/emma2rh/markeins/platform.c
+++ b/arch/mips/emma/markeins/platform.c
@@ -36,7 +36,7 @@
36#include <asm/reboot.h> 36#include <asm/reboot.h>
37#include <asm/traps.h> 37#include <asm/traps.h>
38 38
39#include <asm/emma2rh/emma2rh.h> 39#include <asm/emma/emma2rh.h>
40 40
41 41
42#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */ 42#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma/markeins/setup.c
index b6a23ad539f8..67f456500084 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma/markeins/setup.c
@@ -29,7 +29,7 @@
29#include <asm/time.h> 29#include <asm/time.h>
30#include <asm/reboot.h> 30#include <asm/reboot.h>
31 31
32#include <asm/emma2rh/emma2rh.h> 32#include <asm/emma/emma2rh.h>
33 33
34#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ 34#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
35 35
diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c
deleted file mode 100644
index 91cbd959ab67..000000000000
--- a/arch/mips/emma2rh/common/irq.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * arch/mips/emma2rh/common/irq.c
3 * This file is common irq dispatcher.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/types.h>
29
30#include <asm/system.h>
31#include <asm/mipsregs.h>
32#include <asm/addrspace.h>
33#include <asm/bootinfo.h>
34
35#include <asm/emma2rh/emma2rh.h>
36
37/*
38 * the first level int-handler will jump here if it is a emma2rh irq
39 */
40void emma2rh_irq_dispatch(void)
41{
42 u32 intStatus;
43 u32 bitmask;
44 u32 i;
45
46 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
47 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
48
49#ifdef EMMA2RH_SW_CASCADE
50 if (intStatus &
51 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
52 u32 swIntStatus;
53 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
54 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
55 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
56 if (swIntStatus & bitmask) {
57 do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
58 return;
59 }
60 }
61 }
62#endif
63
64 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
65 if (intStatus & bitmask) {
66 do_IRQ(EMMA2RH_IRQ_BASE + i);
67 return;
68 }
69 }
70
71 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
72 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
73
74#ifdef EMMA2RH_GPIO_CASCADE
75 if (intStatus &
76 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
77 u32 gpioIntStatus;
78 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
79 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
80 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
81 if (gpioIntStatus & bitmask) {
82 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
83 return;
84 }
85 }
86 }
87#endif
88
89 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
90 if (intStatus & bitmask) {
91 do_IRQ(EMMA2RH_IRQ_BASE + i);
92 return;
93 }
94 }
95
96 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
97 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
98
99 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
100 if (intStatus & bitmask) {
101 do_IRQ(EMMA2RH_IRQ_BASE + i);
102 return;
103 }
104 }
105}
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
deleted file mode 100644
index 96df37b77759..000000000000
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * arch/mips/emma2rh/common/irq_emma2rh.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26/*
27 * EMMA2RH defines 64 IRQs.
28 *
29 * This file exports one function:
30 * emma2rh_irq_init(u32 irq_base);
31 */
32
33#include <linux/interrupt.h>
34#include <linux/types.h>
35#include <linux/ptrace.h>
36
37#include <asm/debug.h>
38
39#include <asm/emma2rh/emma2rh.h>
40
41/* number of total irqs supported by EMMA2RH */
42#define NUM_EMMA2RH_IRQ 96
43
44static int emma2rh_irq_base = -1;
45
46void ll_emma2rh_irq_enable(int);
47void ll_emma2rh_irq_disable(int);
48
49static void emma2rh_irq_enable(unsigned int irq)
50{
51 ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
52}
53
54static void emma2rh_irq_disable(unsigned int irq)
55{
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57}
58
59struct irq_chip emma2rh_irq_controller = {
60 .name = "emma2rh_irq",
61 .ack = emma2rh_irq_disable,
62 .mask = emma2rh_irq_disable,
63 .mask_ack = emma2rh_irq_disable,
64 .unmask = emma2rh_irq_enable,
65};
66
67void emma2rh_irq_init(u32 irq_base)
68{
69 u32 i;
70
71 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
72 set_irq_chip_and_handler(i, &emma2rh_irq_controller,
73 handle_level_irq);
74
75 emma2rh_irq_base = irq_base;
76}
77
78void ll_emma2rh_irq_enable(int emma2rh_irq)
79{
80 u32 reg_value;
81 u32 reg_bitmask;
82 u32 reg_index;
83
84 reg_index = EMMA2RH_BHIF_INT_EN_0
85 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
86 * (emma2rh_irq / 32);
87 reg_value = emma2rh_in32(reg_index);
88 reg_bitmask = 0x1 << (emma2rh_irq % 32);
89 db_assert((reg_value & reg_bitmask) == 0);
90 emma2rh_out32(reg_index, reg_value | reg_bitmask);
91}
92
93void ll_emma2rh_irq_disable(int emma2rh_irq)
94{
95 u32 reg_value;
96 u32 reg_bitmask;
97 u32 reg_index;
98
99 reg_index = EMMA2RH_BHIF_INT_EN_0
100 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
101 * (emma2rh_irq / 32);
102 reg_value = emma2rh_in32(reg_index);
103 reg_bitmask = 0x1 << (emma2rh_irq % 32);
104 db_assert((reg_value & reg_bitmask) != 0);
105 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
106}
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
deleted file mode 100644
index 6bcf6a06367a..000000000000
--- a/arch/mips/emma2rh/markeins/irq.c
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * arch/mips/emma2rh/markeins/irq.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/types.h>
29#include <linux/ptrace.h>
30#include <linux/delay.h>
31
32#include <asm/irq_cpu.h>
33#include <asm/system.h>
34#include <asm/mipsregs.h>
35#include <asm/debug.h>
36#include <asm/addrspace.h>
37#include <asm/bootinfo.h>
38
39#include <asm/emma2rh/emma2rh.h>
40
41/*
42 * IRQ mapping
43 *
44 * 0-7: 8 CPU interrupts
45 * 0 - software interrupt 0
46 * 1 - software interrupt 1
47 * 2 - most Vrc5477 interrupts are routed to this pin
48 * 3 - (optional) some other interrupts routed to this pin for debugg
49 * 4 - not used
50 * 5 - not used
51 * 6 - not used
52 * 7 - cpu timer (used by default)
53 *
54 */
55
56extern void emma2rh_sw_irq_init(u32 base);
57extern void emma2rh_gpio_irq_init(u32 base);
58extern void emma2rh_irq_init(u32 base);
59extern void emma2rh_irq_dispatch(void);
60
61static struct irqaction irq_cascade = {
62 .handler = no_action,
63 .flags = 0,
64 .mask = CPU_MASK_NONE,
65 .name = "cascade",
66 .dev_id = NULL,
67 .next = NULL,
68};
69
70void __init arch_init_irq(void)
71{
72 u32 reg;
73
74 db_run(printk("markeins_irq_setup invoked.\n"));
75
76 /* by default, interrupts are disabled. */
77 emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
78 emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
79 emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
80 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
81 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
82 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
83 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
84
85 clear_c0_status(0xff00);
86 set_c0_status(0x0400);
87
88#define GPIO_PCI (0xf<<15)
89 /* setup GPIO interrupt for PCI interface */
90 /* direction input */
91 reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
92 emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
93 /* disable interrupt */
94 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
95 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
96 /* level triggerd */
97 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
98 emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
99 reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
100 emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
101 /* interrupt clear */
102 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
103
104 /* init all controllers */
105 emma2rh_irq_init(EMMA2RH_IRQ_BASE);
106 emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
107 emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
108 mips_cpu_irq_init();
109
110 /* setup cascade interrupts */
111 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
112 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
113 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
114}
115
116asmlinkage void plat_irq_dispatch(void)
117{
118 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
119
120 if (pending & STATUSF_IP7)
121 do_IRQ(CPU_IRQ_BASE + 7);
122 else if (pending & STATUSF_IP2)
123 emma2rh_irq_dispatch();
124 else if (pending & STATUSF_IP1)
125 do_IRQ(CPU_IRQ_BASE + 1);
126 else if (pending & STATUSF_IP0)
127 do_IRQ(CPU_IRQ_BASE + 0);
128 else
129 spurious_interrupt();
130}
131
132
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
deleted file mode 100644
index fba5c156f472..000000000000
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ /dev/null
@@ -1,158 +0,0 @@
1/*
2 * arch/mips/emma2rh/markeins/irq_markeins.c
3 * This file defines the irq handler for Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/types.h>
28#include <linux/ptrace.h>
29
30#include <asm/debug.h>
31#include <asm/emma2rh/emma2rh.h>
32
33static int emma2rh_sw_irq_base = -1;
34static int emma2rh_gpio_irq_base = -1;
35
36void ll_emma2rh_sw_irq_enable(int reg);
37void ll_emma2rh_sw_irq_disable(int reg);
38void ll_emma2rh_gpio_irq_enable(int reg);
39void ll_emma2rh_gpio_irq_disable(int reg);
40
41static void emma2rh_sw_irq_enable(unsigned int irq)
42{
43 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
44}
45
46static void emma2rh_sw_irq_disable(unsigned int irq)
47{
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49}
50
51struct irq_chip emma2rh_sw_irq_controller = {
52 .name = "emma2rh_sw_irq",
53 .ack = emma2rh_sw_irq_disable,
54 .mask = emma2rh_sw_irq_disable,
55 .mask_ack = emma2rh_sw_irq_disable,
56 .unmask = emma2rh_sw_irq_enable,
57};
58
59void emma2rh_sw_irq_init(u32 irq_base)
60{
61 u32 i;
62
63 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
64 set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
65 handle_level_irq);
66
67 emma2rh_sw_irq_base = irq_base;
68}
69
70void ll_emma2rh_sw_irq_enable(int irq)
71{
72 u32 reg;
73
74 db_assert(irq >= 0);
75 db_assert(irq < NUM_EMMA2RH_IRQ_SW);
76
77 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
78 reg |= 1 << irq;
79 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
80}
81
82void ll_emma2rh_sw_irq_disable(int irq)
83{
84 u32 reg;
85
86 db_assert(irq >= 0);
87 db_assert(irq < 32);
88
89 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
90 reg &= ~(1 << irq);
91 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
92}
93
94static void emma2rh_gpio_irq_enable(unsigned int irq)
95{
96 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
97}
98
99static void emma2rh_gpio_irq_disable(unsigned int irq)
100{
101 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
102}
103
104static void emma2rh_gpio_irq_ack(unsigned int irq)
105{
106 irq -= emma2rh_gpio_irq_base;
107 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
108 ll_emma2rh_gpio_irq_disable(irq);
109}
110
111static void emma2rh_gpio_irq_end(unsigned int irq)
112{
113 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
114 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
115}
116
117struct irq_chip emma2rh_gpio_irq_controller = {
118 .name = "emma2rh_gpio_irq",
119 .ack = emma2rh_gpio_irq_ack,
120 .mask = emma2rh_gpio_irq_disable,
121 .mask_ack = emma2rh_gpio_irq_ack,
122 .unmask = emma2rh_gpio_irq_enable,
123 .end = emma2rh_gpio_irq_end,
124};
125
126void emma2rh_gpio_irq_init(u32 irq_base)
127{
128 u32 i;
129
130 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
131 set_irq_chip(i, &emma2rh_gpio_irq_controller);
132
133 emma2rh_gpio_irq_base = irq_base;
134}
135
136void ll_emma2rh_gpio_irq_enable(int irq)
137{
138 u32 reg;
139
140 db_assert(irq >= 0);
141 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
142
143 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
144 reg |= 1 << irq;
145 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
146}
147
148void ll_emma2rh_gpio_irq_disable(int irq)
149{
150 u32 reg;
151
152 db_assert(irq >= 0);
153 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
154
155 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
156 reg &= ~(1 << irq);
157 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
158}
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 49df8c4c9d25..bac4a960b24c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
558 __clear_bit(nr, addr); 558 __clear_bit(nr, addr);
559} 559}
560 560
561#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
562
563/* 561/*
564 * Return the bit position (0..63) of the most significant 1 bit in a word 562 * Return the bit position (0..63) of the most significant 1 bit in a word
565 * Returns -1 if no 1 bit exists 563 * Returns -1 if no 1 bit exists
566 */ 564 */
567static inline unsigned long __fls(unsigned long x) 565static inline unsigned long __fls(unsigned long word)
568{ 566{
569 int lz; 567 int num;
570 568
571 if (sizeof(x) == 4) { 569 if (BITS_PER_LONG == 32 &&
570 __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
572 __asm__( 571 __asm__(
573 " .set push \n" 572 " .set push \n"
574 " .set mips32 \n" 573 " .set mips32 \n"
575 " clz %0, %1 \n" 574 " clz %0, %1 \n"
576 " .set pop \n" 575 " .set pop \n"
577 : "=r" (lz) 576 : "=r" (num)
578 : "r" (x)); 577 : "r" (word));
579 578
580 return 31 - lz; 579 return 31 - num;
581 } 580 }
582 581
583 BUG_ON(sizeof(x) != 8); 582 if (BITS_PER_LONG == 64 &&
583 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
584 __asm__(
585 " .set push \n"
586 " .set mips64 \n"
587 " dclz %0, %1 \n"
588 " .set pop \n"
589 : "=r" (num)
590 : "r" (word));
584 591
585 __asm__( 592 return 63 - num;
586 " .set push \n" 593 }
587 " .set mips64 \n" 594
588 " dclz %0, %1 \n" 595 num = BITS_PER_LONG - 1;
589 " .set pop \n"
590 : "=r" (lz)
591 : "r" (x));
592 596
593 return 63 - lz; 597#if BITS_PER_LONG == 64
598 if (!(word & (~0ul << 32))) {
599 num -= 32;
600 word <<= 32;
601 }
602#endif
603 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
604 num -= 16;
605 word <<= 16;
606 }
607 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
608 num -= 8;
609 word <<= 8;
610 }
611 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
612 num -= 4;
613 word <<= 4;
614 }
615 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
616 num -= 2;
617 word <<= 2;
618 }
619 if (!(word & (~0ul << (BITS_PER_LONG-1))))
620 num -= 1;
621 return num;
594} 622}
595 623
596/* 624/*
@@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word)
612 * This is defined the same way as ffs. 640 * This is defined the same way as ffs.
613 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. 641 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
614 */ 642 */
615static inline int fls(int word) 643static inline int fls(int x)
616{ 644{
617 __asm__("clz %0, %1" : "=r" (word) : "r" (word)); 645 int r;
618 646
619 return 32 - word; 647 if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
620} 648 __asm__("clz %0, %1" : "=r" (x) : "r" (x));
621 649
622#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) 650 return 32 - x;
623static inline int fls64(__u64 word) 651 }
624{
625 __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
626 652
627 return 64 - word; 653 r = 32;
654 if (!x)
655 return 0;
656 if (!(x & 0xffff0000u)) {
657 x <<= 16;
658 r -= 16;
659 }
660 if (!(x & 0xff000000u)) {
661 x <<= 8;
662 r -= 8;
663 }
664 if (!(x & 0xf0000000u)) {
665 x <<= 4;
666 r -= 4;
667 }
668 if (!(x & 0xc0000000u)) {
669 x <<= 2;
670 r -= 2;
671 }
672 if (!(x & 0x80000000u)) {
673 x <<= 1;
674 r -= 1;
675 }
676 return r;
628} 677}
629#else 678
630#include <asm-generic/bitops/fls64.h> 679#include <asm-generic/bitops/fls64.h>
631#endif
632 680
633/* 681/*
634 * ffs - find first bit set. 682 * ffs - find first bit set.
@@ -646,16 +694,6 @@ static inline int ffs(int word)
646 return fls(word & -word); 694 return fls(word & -word);
647} 695}
648 696
649#else
650
651#include <asm-generic/bitops/__ffs.h>
652#include <asm-generic/bitops/__fls.h>
653#include <asm-generic/bitops/ffs.h>
654#include <asm-generic/bitops/fls.h>
655#include <asm-generic/bitops/fls64.h>
656
657#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
658
659#include <asm-generic/bitops/ffz.h> 697#include <asm-generic/bitops/ffz.h>
660#include <asm-generic/bitops/find.h> 698#include <asm-generic/bitops/find.h>
661 699
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 25b980c91e7e..44437ed765e8 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -29,6 +29,7 @@
29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ 29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
30#define BRK_BUG 512 /* Used by BUG() */ 30#define BRK_BUG 512 /* Used by BUG() */
31#define BRK_KDB 513 /* Used in KDB_ENTER() */ 31#define BRK_KDB 513 /* Used in KDB_ENTER() */
32#define BRK_MEMU 514 /* Used by FPU emulator */
32#define BRK_MULOVF 1023 /* Multiply overflow */ 33#define BRK_MULOVF 1023 /* Multiply overflow */
33 34
34#endif /* __ASM_BREAK_H */ 35#endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index fe7dc2d59b69..2988d29a0867 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -11,11 +11,19 @@
11#include <linux/compiler.h> 11#include <linux/compiler.h>
12#include <asm/types.h> 12#include <asm/types.h>
13 13
14#ifdef __GNUC__ 14#if defined(__MIPSEB__)
15# define __BIG_ENDIAN
16#elif defined(__MIPSEL__)
17# define __LITTLE_ENDIAN
18#else
19# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
20#endif
21
22#define __SWAB_64_THRU_32__
15 23
16#ifdef CONFIG_CPU_MIPSR2 24#ifdef CONFIG_CPU_MIPSR2
17 25
18static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) 26static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
19{ 27{
20 __asm__( 28 __asm__(
21 " wsbh %0, %1 \n" 29 " wsbh %0, %1 \n"
@@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
24 32
25 return x; 33 return x;
26} 34}
27#define __arch__swab16(x) ___arch__swab16(x) 35#define __arch_swab16 __arch_swab16
28 36
29static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) 37static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
30{ 38{
31 __asm__( 39 __asm__(
32 " wsbh %0, %1 \n" 40 " wsbh %0, %1 \n"
@@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
36 44
37 return x; 45 return x;
38} 46}
39#define __arch__swab32(x) ___arch__swab32(x) 47#define __arch_swab32 __arch_swab32
40 48
41#ifdef CONFIG_CPU_MIPS64_R2 49#ifdef CONFIG_CPU_MIPS64_R2
42 50static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
43static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
44{ 51{
45 __asm__( 52 __asm__(
46 " dsbh %0, %1 \n" 53 " dsbh %0, %1 \n"
@@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
51 58
52 return x; 59 return x;
53} 60}
54 61#define __arch_swab64 __arch_swab64
55#define __arch__swab64(x) ___arch__swab64(x)
56
57#endif /* CONFIG_CPU_MIPS64_R2 */ 62#endif /* CONFIG_CPU_MIPS64_R2 */
58 63
59#endif /* CONFIG_CPU_MIPSR2 */ 64#endif /* CONFIG_CPU_MIPSR2 */
60 65
61#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 66#include <linux/byteorder.h>
62# define __BYTEORDER_HAS_U64__
63# define __SWAB_64_THRU_32__
64#endif
65
66#endif /* __GNUC__ */
67
68#if defined(__MIPSEB__)
69# include <linux/byteorder/big_endian.h>
70#elif defined(__MIPSEL__)
71# include <linux/byteorder/little_endian.h>
72#else
73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
74#endif
75 67
76#endif /* _ASM_BYTEORDER_H */ 68#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5ea701fc3425..12d12dfe73c0 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -141,6 +141,8 @@
141#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 141#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
142#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 142#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
143#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 143#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
144#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
145 cpu_has_mips64r1 | cpu_has_mips64r2)
144 146
145#ifndef cpu_has_dsp 147#ifndef cpu_has_dsp
146#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 148#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h
deleted file mode 100644
index 6983b6ff0af3..000000000000
--- a/arch/mips/include/asm/ds1286.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Machine dependent access functions for RTC registers.
7 *
8 * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
9 */
10#ifndef _ASM_DS1286_H
11#define _ASM_DS1286_H
12
13#include <ds1286.h>
14
15#endif /* _ASM_DS1286_H */
diff --git a/arch/mips/include/asm/emma2rh/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 6a1af0af51e3..30aea91de626 100644
--- a/arch/mips/include/asm/emma2rh/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-mips/emma2rh/emma2rh.h 2 * arch/mips/include/asm/emma/emma2rh.h
3 * This file is EMMA2RH common header. 3 * This file is EMMA2RH common header.
4 * 4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006 5 * Copyright (C) NEC Electronics Corporation 2005-2006
@@ -21,8 +21,8 @@
21 * along with this program; if not, write to the Free Software 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */ 23 */
24#ifndef __ASM_EMMA2RH_EMMA2RH_H 24#ifndef __ASM_EMMA_EMMA2RH_H
25#define __ASM_EMMA2RH_EMMA2RH_H 25#define __ASM_EMMA_EMMA2RH_H
26 26
27#include <irq.h> 27#include <irq.h>
28 28
@@ -206,7 +206,6 @@ static inline void emma2rh_out32(u32 offset, u32 val)
206static inline u32 emma2rh_in32(u32 offset) 206static inline u32 emma2rh_in32(u32 offset)
207{ 207{
208 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); 208 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
209 emma2rh_sync();
210 return val; 209 return val;
211} 210}
212 211
@@ -219,7 +218,6 @@ static inline void emma2rh_out16(u32 offset, u16 val)
219static inline u16 emma2rh_in16(u32 offset) 218static inline u16 emma2rh_in16(u32 offset)
220{ 219{
221 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); 220 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
222 emma2rh_sync();
223 return val; 221 return val;
224} 222}
225 223
@@ -232,7 +230,6 @@ static inline void emma2rh_out8(u32 offset, u8 val)
232static inline u8 emma2rh_in8(u32 offset) 230static inline u8 emma2rh_in8(u32 offset)
233{ 231{
234 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); 232 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
235 emma2rh_sync();
236 return val; 233 return val;
237} 234}
238 235
@@ -324,10 +321,10 @@ static inline u8 emma2rh_in8(u32 offset)
324/* 321/*
325 * include the board dependent part 322 * include the board dependent part
326 */ 323 */
327#if defined(CONFIG_MARKEINS) 324#ifdef CONFIG_NEC_MARKEINS
328#include <asm/emma2rh/markeins.h> 325#include <asm/emma/markeins.h>
329#else 326#else
330#error "Unknown EMMA2RH board!" 327#error "Unknown EMMA2RH board!"
331#endif 328#endif
332 329
333#endif /* __ASM_EMMA2RH_EMMA2RH_H */ 330#endif /* __ASM_EMMA_EMMA2RH_H */
diff --git a/arch/mips/include/asm/emma2rh/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 973b0628490d..973b0628490d 100644
--- a/arch/mips/include/asm/emma2rh/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 2731c38bd7ae..e5189572956c 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -23,6 +23,9 @@
23#ifndef _ASM_FPU_EMULATOR_H 23#ifndef _ASM_FPU_EMULATOR_H
24#define _ASM_FPU_EMULATOR_H 24#define _ASM_FPU_EMULATOR_H
25 25
26#include <asm/break.h>
27#include <asm/inst.h>
28
26struct mips_fpu_emulator_stats { 29struct mips_fpu_emulator_stats {
27 unsigned int emulated; 30 unsigned int emulated;
28 unsigned int loads; 31 unsigned int loads;
@@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats {
34 37
35extern struct mips_fpu_emulator_stats fpuemustats; 38extern struct mips_fpu_emulator_stats fpuemustats;
36 39
40extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
41 unsigned long cpc);
42extern int do_dsemulret(struct pt_regs *xcp);
43
44/*
45 * Instruction inserted following the badinst to further tag the sequence
46 */
47#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */
48
49/*
50 * Break instruction with special math emu break code set
51 */
52#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16))
53
37#endif /* _ASM_FPU_EMULATOR_H */ 54#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h
deleted file mode 100644
index f44852e9a96d..000000000000
--- a/arch/mips/include/asm/m48t35.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
3 */
4#ifndef _ASM_M48T35_H
5#define _ASM_M48T35_H
6
7#include <linux/spinlock.h>
8
9extern spinlock_t rtc_lock;
10
11struct m48t35_rtc {
12 volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */
13 volatile u8 control;
14 volatile u8 sec;
15 volatile u8 min;
16 volatile u8 hour;
17 volatile u8 day;
18 volatile u8 date;
19 volatile u8 month;
20 volatile u8 year;
21};
22
23#define M48T35_RTC_SET 0x80
24#define M48T35_RTC_STOPPED 0x80
25#define M48T35_RTC_READ 0x40
26
27#endif /* _ASM_M48T35_H */
diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h
new file mode 100644
index 000000000000..ea6aa143b78e
--- /dev/null
+++ b/arch/mips/include/asm/mach-lemote/pci.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3 *
4 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General
6 * Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be
11 * useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this program; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 * 02139, USA.
20 */
21
22#ifndef _LEMOTE_PCI_H_
23#define _LEMOTE_PCI_H_
24
25#define LOONGSON2E_PCI_MEM_START 0x14000000UL
26#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL
27#define LOONGSON2E_PCI_IO_START 0x00004000UL
28#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL
29
30#endif /* !_LEMOTE_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h
new file mode 100644
index 000000000000..8de0eb9c98a3
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/gpio.h
@@ -0,0 +1,172 @@
1/*
2 * gpio.h: GPIO Support for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
23#define __ASM_MIPS_MACH_PNX833X_GPIO_H
24
25/* BIG FAT WARNING: races danger!
26 No protections exist here. Current users are only early init code,
27 when locking is not needed because no cuncurency yet exists there,
28 and GPIO IRQ dispatcher, which does locking.
29 However, if many uses will ever happen, proper locking will be needed
30 - including locking between different uses
31*/
32
33#include "pnx833x.h"
34
35#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
36#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
37
38/* Initialize GPIO to a known state */
39static inline void pnx833x_gpio_init(void)
40{
41 PNX833X_PIO_DIR = 0;
42 PNX833X_PIO_DIR2 = 0;
43 PNX833X_PIO_SEL = 0;
44 PNX833X_PIO_SEL2 = 0;
45 PNX833X_PIO_INT_EDGE = 0;
46 PNX833X_PIO_INT_HI = 0;
47 PNX833X_PIO_INT_LO = 0;
48
49 /* clear any GPIO interrupt requests */
50 PNX833X_PIO_INT_CLEAR = 0xffff;
51 PNX833X_PIO_INT_CLEAR = 0;
52 PNX833X_PIO_INT_ENABLE = 0;
53}
54
55/* Select GPIO direction for a pin */
56static inline void pnx833x_gpio_select_input(unsigned int pin)
57{
58 if (pin < 32)
59 CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
60 else
61 CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
62}
63static inline void pnx833x_gpio_select_output(unsigned int pin)
64{
65 if (pin < 32)
66 SET_REG_BIT(PNX833X_PIO_DIR, pin);
67 else
68 SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
69}
70
71/* Select GPIO or alternate function for a pin */
72static inline void pnx833x_gpio_select_function_io(unsigned int pin)
73{
74 if (pin < 32)
75 CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
76 else
77 CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
78}
79static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
80{
81 if (pin < 32)
82 SET_REG_BIT(PNX833X_PIO_SEL, pin);
83 else
84 SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
85}
86
87/* Read GPIO pin */
88static inline int pnx833x_gpio_read(unsigned int pin)
89{
90 if (pin < 32)
91 return (PNX833X_PIO_IN >> pin) & 1;
92 else
93 return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
94}
95
96/* Write GPIO pin */
97static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
98{
99 if (pin < 32) {
100 if (val)
101 SET_REG_BIT(PNX833X_PIO_OUT, pin);
102 else
103 CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
104 } else {
105 if (val)
106 SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
107 else
108 CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
109 }
110}
111
112/* Configure GPIO interrupt */
113#define GPIO_INT_NONE 0
114#define GPIO_INT_LEVEL_LOW 1
115#define GPIO_INT_LEVEL_HIGH 2
116#define GPIO_INT_EDGE_RISING 3
117#define GPIO_INT_EDGE_FALLING 4
118#define GPIO_INT_EDGE_BOTH 5
119static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
120{
121 switch (when) {
122 case GPIO_INT_LEVEL_LOW:
123 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
124 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
125 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
126 break;
127 case GPIO_INT_LEVEL_HIGH:
128 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
129 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
130 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
131 break;
132 case GPIO_INT_EDGE_RISING:
133 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
134 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
135 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
136 break;
137 case GPIO_INT_EDGE_FALLING:
138 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
139 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
140 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
141 break;
142 case GPIO_INT_EDGE_BOTH:
143 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
144 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
145 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
146 break;
147 default:
148 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
149 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
150 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
151 break;
152 }
153}
154
155/* Enable/disable GPIO interrupt */
156static inline void pnx833x_gpio_enable_irq(unsigned int pin)
157{
158 SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
159}
160static inline void pnx833x_gpio_disable_irq(unsigned int pin)
161{
162 CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
163}
164
165/* Clear GPIO interrupt request */
166static inline void pnx833x_gpio_clear_irq(unsigned int pin)
167{
168 SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
169 CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
170}
171
172#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
new file mode 100644
index 000000000000..657f089b1724
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -0,0 +1,126 @@
1
2/*
3 * irq.h: IRQ mappings for PNX833X.
4 *
5 * Copyright 2008 NXP Semiconductors
6 * Chris Steel <chris.steel@nxp.com>
7 * Daniel Laird <daniel.j.laird@nxp.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
25#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
26/*
27 * The "IRQ numbers" are completely virtual.
28 *
29 * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
30 * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
31 * numbers 49..64 for (virtual) GPIO interrupts.
32 *
33 * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
34 * connected to PIC, which uses core hardware interrupt 2, and also
35 * a timer interrupt through hardware interrupt 5.
36 * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
37 * numbers 65..80 for (virtual) GPIO interrupts.
38 *
39 */
40#include <irq.h>
41
42#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
43
44/* Interrupts supported by PIC */
45#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1)
46#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2)
47#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3)
48#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4)
49#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5)
50#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6)
51#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7)
52#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8)
53#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9)
54#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10)
55#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11)
56#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12)
57#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13)
58#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13)
59#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14)
60#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15)
61#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16)
62#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17)
63#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18)
64#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19)
65#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20)
66#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21)
67#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22)
68#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23)
69#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24)
70#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25)
71#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26)
72#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27)
73#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28)
74#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29)
75#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30)
76#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31)
77#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32)
78#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33)
79#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34)
80#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35)
81#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36)
82
83#if defined(CONFIG_SOC_PNX8335)
84#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37)
85#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38)
86#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39)
87#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40)
88#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41)
89#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42)
90#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43)
91#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44)
92#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45)
93#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46)
94#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47)
95#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48)
96#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49)
97#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50)
98#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51)
99#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52)
100#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53)
101#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54)
102#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55)
103#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56)
104#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57)
105#endif
106
107/* GPIO interrupts */
108#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0)
109#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1)
110#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2)
111#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3)
112#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4)
113#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5)
114#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6)
115#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7)
116#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8)
117#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9)
118#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10)
119#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11)
120#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12)
121#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13)
122#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14)
123#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
124
125#endif
126
diff --git a/arch/mips/include/asm/mach-pnx833x/irq.h b/arch/mips/include/asm/mach-pnx833x/irq.h
new file mode 100644
index 000000000000..745114b1d8d5
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/irq.h
@@ -0,0 +1,53 @@
1/*
2 * irq.h: IRQ mappings for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
24#define __ASM_MIPS_MACH_PNX833X_IRQ_H
25/*
26 * The "IRQ numbers" are completely virtual.
27 *
28 * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
29 * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
30 * numbers 49..64 for (virtual) GPIO interrupts.
31 *
32 * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
33 * connected to PIC, which uses core hardware interrupt 2, and also
34 * a timer interrupt through hardware interrupt 5.
35 * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
36 * numbers 65..80 for (virtual) GPIO interrupts.
37 *
38 */
39#if defined(CONFIG_SOC_PNX8335)
40 #define PNX833X_PIC_NUM_IRQ 58
41#else
42 #define PNX833X_PIC_NUM_IRQ 37
43#endif
44
45#define MIPS_CPU_NUM_IRQ 8
46#define PNX833X_GPIO_NUM_IRQ 16
47
48#define MIPS_CPU_IRQ_BASE 0
49#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
50#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
51#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
52
53#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
new file mode 100644
index 000000000000..100f52870e3c
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
@@ -0,0 +1,202 @@
1/*
2 * pnx833x.h: Register mappings for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
23#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
24
25/* All regs are accessed in KSEG1 */
26#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul)
27
28#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs)))
29
30/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
31
32/* Read access to multibit fields */
33#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
34#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
35
36/* Use PNX833X_FIELD to extract a field from val */
37#define PNX_FIELD(cpu, val, reg, field) \
38 (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
39 PNX##cpu##_##reg##_##field##_SHIFT)
40#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
41#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
42#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
43
44/* Use PNX833X_REGFIELD to extract a field from a register */
45#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
46#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
47#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
48
49
50#define PNX_WRITEFIELD(cpu, val, reg, field) \
51 (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
52 ((val) << PNX##cpu##_##reg##_##field##_SHIFT))
53#define PNX833X_WRITEFIELD(val, reg, field) \
54 PNX_WRITEFIELD(833X, val, reg, field)
55#define PNX8330_WRITEFIELD(val, reg, field) \
56 PNX_WRITEFIELD(8330, val, reg, field)
57#define PNX8335_WRITEFIELD(val, reg, field) \
58 PNX_WRITEFIELD(8335, val, reg, field)
59
60
61/* Macros to detect CPU type */
62
63#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC)
64#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000
65#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12
66#define PNX8330_CONFIG_MODULE_MAJREV 4
67#define PNX8335_CONFIG_MODULE_MAJREV 5
68#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
69 PNX8330_CONFIG_MODULE_MAJREV)
70#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
71 PNX8335_CONFIG_MODULE_MAJREV)
72
73
74
75#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004)
76#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014)
77
78#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs))
79#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0)
80#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4)
81#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */
82#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3
83#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq))
84
85#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
86#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */
87#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */
88#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
89
90#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020)
91#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f
92#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0
93
94#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004)
95#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */
96
97#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040)
98#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000
99#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19
100
101#define PNX833X_PIO_IN PNX833X_REG(0xF000)
102#define PNX833X_PIO_OUT PNX833X_REG(0xF004)
103#define PNX833X_PIO_DIR PNX833X_REG(0xF008)
104#define PNX833X_PIO_SEL PNX833X_REG(0xF014)
105#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020)
106#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024)
107#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028)
108#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0)
109#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4)
110#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8)
111#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C)
112#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060)
113#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064)
114#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068)
115
116#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000)
117#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF)
118#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000)
119#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF)
120
121#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000)
122#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF)
123
124#define PNX833X_CONFIG_USB PNX833X_REG(0x7008)
125
126#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000)
127#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF)
128#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000)
129#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF)
130
131#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000)
132#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF)
133#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC)
134
135#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
136#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16
137#define PNX833X_IDE_MODULE_ID_VALUE 0xA009
138
139
140#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004)
141#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008)
142#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C)
143#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010)
144#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014)
145#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018)
146#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C)
147#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020)
148
149#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14)
150#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
151
152#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
153#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7
154
155#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9)
156#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9
157
158#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000)
159
160#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3)
161#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3
162
163#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
164#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2
165
166#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
167#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1
168
169#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0)
170#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0
171
172#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
173 (PNX833X_MIU_CONFIG_SPI = \
174 ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \
175 ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \
176 ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \
177 ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
178
179#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000)
180#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF)
181#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC)
182
183#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
184#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16
185#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902
186
187 /* I/O location(gets remapped)*/
188#define PNX8335_NAND_BASE 0x18000000
189/* I/O location with CLE high */
190#define PNX8335_NAND_CLE_MASK 0x00100000
191/* I/O location with ALE high */
192#define PNX8335_NAND_ALE_MASK 0x00010000
193
194#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000)
195#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF)
196#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC)
197
198#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
199#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16
200#define PNX8335_SATA_MODULE_ID_VALUE 0xA099
201
202#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
new file mode 100644
index 000000000000..82cd1e97bc2e
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
9#define __ASM_MIPS_MACH_PNX833X_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
new file mode 100644
index 000000000000..5e6912fdd0ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_MACH_TX49XX_MANGLE_PORT_H
2#define __ASM_MACH_TX49XX_MANGLE_PORT_H
3
4#define __swizzle_addr_b(port) (port)
5#define __swizzle_addr_w(port) (port)
6#define __swizzle_addr_l(port) (port)
7#define __swizzle_addr_q(port) (port)
8
9#define ioswabb(a, x) (x)
10#define __mem_ioswabb(a, x) (x)
11#if defined(CONFIG_TOSHIBA_RBTX4939) && \
12 (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \
13 defined(__BIG_ENDIAN)
14#define NEEDS_TXX9_IOSWABW
15extern u16 (*ioswabw)(volatile u16 *a, u16 x);
16extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
17#else
18#define ioswabw(a, x) le16_to_cpu(x)
19#define __mem_ioswabw(a, x) (x)
20#endif
21#define ioswabl(a, x) le32_to_cpu(x)
22#define __mem_ioswabl(a, x) (x)
23#define ioswabq(a, x) le64_to_cpu(x)
24#define __mem_ioswabq(a, x) (x)
25
26#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 979866000da4..9316324d070d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -192,6 +192,7 @@
192#define PM_16M 0x01ffe000 192#define PM_16M 0x01ffe000
193#define PM_64M 0x07ffe000 193#define PM_64M 0x07ffe000
194#define PM_256M 0x1fffe000 194#define PM_256M 0x1fffe000
195#define PM_1G 0x7fffe000
195 196
196#endif 197#endif
197 198
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index de6d09ebbd80..e2e09b2cd265 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -98,6 +98,8 @@ search_module_dbetables(unsigned long addr)
98#define MODULE_PROC_FAMILY "R5000 " 98#define MODULE_PROC_FAMILY "R5000 "
99#elif defined CONFIG_CPU_R5432 99#elif defined CONFIG_CPU_R5432
100#define MODULE_PROC_FAMILY "R5432 " 100#define MODULE_PROC_FAMILY "R5432 "
101#elif defined CONFIG_CPU_R5500
102#define MODULE_PROC_FAMILY "R5500 "
101#elif defined CONFIG_CPU_R6000 103#elif defined CONFIG_CPU_R6000
102#define MODULE_PROC_FAMILY "R6000 " 104#define MODULE_PROC_FAMILY "R6000 "
103#elif defined CONFIG_CPU_NEVADA 105#elif defined CONFIG_CPU_NEVADA
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 9c22571b160d..813abd16255d 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -80,25 +80,25 @@ enum pt_watch_style {
80 pt_watch_style_mips64 80 pt_watch_style_mips64
81}; 81};
82struct mips32_watch_regs { 82struct mips32_watch_regs {
83 uint32_t watchlo[8]; 83 unsigned int watchlo[8];
84 /* Lower 16 bits of watchhi. */ 84 /* Lower 16 bits of watchhi. */
85 uint16_t watchhi[8]; 85 unsigned short watchhi[8];
86 /* Valid mask and I R W bits. 86 /* Valid mask and I R W bits.
87 * bit 0 -- 1 if W bit is usable. 87 * bit 0 -- 1 if W bit is usable.
88 * bit 1 -- 1 if R bit is usable. 88 * bit 1 -- 1 if R bit is usable.
89 * bit 2 -- 1 if I bit is usable. 89 * bit 2 -- 1 if I bit is usable.
90 * bits 3 - 11 -- Valid watchhi mask bits. 90 * bits 3 - 11 -- Valid watchhi mask bits.
91 */ 91 */
92 uint16_t watch_masks[8]; 92 unsigned short watch_masks[8];
93 /* The number of valid watch register pairs. */ 93 /* The number of valid watch register pairs. */
94 uint32_t num_valid; 94 unsigned int num_valid;
95} __attribute__((aligned(8))); 95} __attribute__((aligned(8)));
96 96
97struct mips64_watch_regs { 97struct mips64_watch_regs {
98 uint64_t watchlo[8]; 98 unsigned long long watchlo[8];
99 uint16_t watchhi[8]; 99 unsigned short watchhi[8];
100 uint16_t watch_masks[8]; 100 unsigned short watch_masks[8];
101 uint32_t num_valid; 101 unsigned int num_valid;
102} __attribute__((aligned(8))); 102} __attribute__((aligned(8)));
103 103
104struct pt_watch_regs { 104struct pt_watch_regs {
@@ -116,6 +116,7 @@ struct pt_watch_regs {
116 116
117#include <linux/compiler.h> 117#include <linux/compiler.h>
118#include <linux/linkage.h> 118#include <linux/linkage.h>
119#include <linux/types.h>
119#include <asm/isadep.h> 120#include <asm/isadep.h>
120 121
121struct task_struct; 122struct task_struct;
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 4316a3e57678..9cde0090cbf6 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -86,4 +86,9 @@ void txx9_iocled_init(unsigned long baseaddr,
86 int basenum, unsigned int num, int lowactive, 86 int basenum, unsigned int num, int lowactive,
87 const char *color, char **deftriggers); 87 const char *color, char **deftriggers);
88 88
89/* 7SEG LED */
90void txx9_7segled_init(unsigned int num,
91 void (*putc)(unsigned int pos, unsigned char val));
92int txx9_7segled_putc(unsigned int pos, char c);
93
89#endif /* __ASM_TXX9_GENERIC_H */ 94#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d9da7112aaf8..b1372c27f136 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o
33obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o 33obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o
34obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o 34obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
35obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o 35obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o
36obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o
36obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o 37obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o
37obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o 38obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o
38obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o 39obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0cf15457ecac..c9207b5fd923 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -286,11 +286,12 @@ static inline int __cpu_has_fpu(void)
286#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 286#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
287 | MIPS_CPU_COUNTER) 287 | MIPS_CPU_COUNTER)
288 288
289static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 289static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
290{ 290{
291 switch (c->processor_id & 0xff00) { 291 switch (c->processor_id & 0xff00) {
292 case PRID_IMP_R2000: 292 case PRID_IMP_R2000:
293 c->cputype = CPU_R2000; 293 c->cputype = CPU_R2000;
294 __cpu_name[cpu] = "R2000";
294 c->isa_level = MIPS_CPU_ISA_I; 295 c->isa_level = MIPS_CPU_ISA_I;
295 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 296 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
296 MIPS_CPU_NOFPUEX; 297 MIPS_CPU_NOFPUEX;
@@ -299,13 +300,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
299 c->tlbsize = 64; 300 c->tlbsize = 64;
300 break; 301 break;
301 case PRID_IMP_R3000: 302 case PRID_IMP_R3000:
302 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 303 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
303 if (cpu_has_confreg()) 304 if (cpu_has_confreg()) {
304 c->cputype = CPU_R3081E; 305 c->cputype = CPU_R3081E;
305 else 306 __cpu_name[cpu] = "R3081";
307 } else {
306 c->cputype = CPU_R3000A; 308 c->cputype = CPU_R3000A;
307 else 309 __cpu_name[cpu] = "R3000A";
310 }
311 break;
312 } else {
308 c->cputype = CPU_R3000; 313 c->cputype = CPU_R3000;
314 __cpu_name[cpu] = "R3000";
315 }
309 c->isa_level = MIPS_CPU_ISA_I; 316 c->isa_level = MIPS_CPU_ISA_I;
310 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 317 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
311 MIPS_CPU_NOFPUEX; 318 MIPS_CPU_NOFPUEX;
@@ -315,15 +322,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
315 break; 322 break;
316 case PRID_IMP_R4000: 323 case PRID_IMP_R4000:
317 if (read_c0_config() & CONF_SC) { 324 if (read_c0_config() & CONF_SC) {
318 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 325 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
319 c->cputype = CPU_R4400PC; 326 c->cputype = CPU_R4400PC;
320 else 327 __cpu_name[cpu] = "R4400PC";
328 } else {
321 c->cputype = CPU_R4000PC; 329 c->cputype = CPU_R4000PC;
330 __cpu_name[cpu] = "R4000PC";
331 }
322 } else { 332 } else {
323 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 333 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
324 c->cputype = CPU_R4400SC; 334 c->cputype = CPU_R4400SC;
325 else 335 __cpu_name[cpu] = "R4400SC";
336 } else {
326 c->cputype = CPU_R4000SC; 337 c->cputype = CPU_R4000SC;
338 __cpu_name[cpu] = "R4000SC";
339 }
327 } 340 }
328 341
329 c->isa_level = MIPS_CPU_ISA_III; 342 c->isa_level = MIPS_CPU_ISA_III;
@@ -336,25 +349,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
336 switch (c->processor_id & 0xf0) { 349 switch (c->processor_id & 0xf0) {
337 case PRID_REV_VR4111: 350 case PRID_REV_VR4111:
338 c->cputype = CPU_VR4111; 351 c->cputype = CPU_VR4111;
352 __cpu_name[cpu] = "NEC VR4111";
339 break; 353 break;
340 case PRID_REV_VR4121: 354 case PRID_REV_VR4121:
341 c->cputype = CPU_VR4121; 355 c->cputype = CPU_VR4121;
356 __cpu_name[cpu] = "NEC VR4121";
342 break; 357 break;
343 case PRID_REV_VR4122: 358 case PRID_REV_VR4122:
344 if ((c->processor_id & 0xf) < 0x3) 359 if ((c->processor_id & 0xf) < 0x3) {
345 c->cputype = CPU_VR4122; 360 c->cputype = CPU_VR4122;
346 else 361 __cpu_name[cpu] = "NEC VR4122";
362 } else {
347 c->cputype = CPU_VR4181A; 363 c->cputype = CPU_VR4181A;
364 __cpu_name[cpu] = "NEC VR4181A";
365 }
348 break; 366 break;
349 case PRID_REV_VR4130: 367 case PRID_REV_VR4130:
350 if ((c->processor_id & 0xf) < 0x4) 368 if ((c->processor_id & 0xf) < 0x4) {
351 c->cputype = CPU_VR4131; 369 c->cputype = CPU_VR4131;
352 else 370 __cpu_name[cpu] = "NEC VR4131";
371 } else {
353 c->cputype = CPU_VR4133; 372 c->cputype = CPU_VR4133;
373 __cpu_name[cpu] = "NEC VR4133";
374 }
354 break; 375 break;
355 default: 376 default:
356 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 377 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
357 c->cputype = CPU_VR41XX; 378 c->cputype = CPU_VR41XX;
379 __cpu_name[cpu] = "NEC Vr41xx";
358 break; 380 break;
359 } 381 }
360 c->isa_level = MIPS_CPU_ISA_III; 382 c->isa_level = MIPS_CPU_ISA_III;
@@ -363,6 +385,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
363 break; 385 break;
364 case PRID_IMP_R4300: 386 case PRID_IMP_R4300:
365 c->cputype = CPU_R4300; 387 c->cputype = CPU_R4300;
388 __cpu_name[cpu] = "R4300";
366 c->isa_level = MIPS_CPU_ISA_III; 389 c->isa_level = MIPS_CPU_ISA_III;
367 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
368 MIPS_CPU_LLSC; 391 MIPS_CPU_LLSC;
@@ -370,6 +393,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
370 break; 393 break;
371 case PRID_IMP_R4600: 394 case PRID_IMP_R4600:
372 c->cputype = CPU_R4600; 395 c->cputype = CPU_R4600;
396 __cpu_name[cpu] = "R4600";
373 c->isa_level = MIPS_CPU_ISA_III; 397 c->isa_level = MIPS_CPU_ISA_III;
374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 398 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
375 MIPS_CPU_LLSC; 399 MIPS_CPU_LLSC;
@@ -384,6 +408,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
384 * it's c0_prid id number with the TX3900. 408 * it's c0_prid id number with the TX3900.
385 */ 409 */
386 c->cputype = CPU_R4650; 410 c->cputype = CPU_R4650;
411 __cpu_name[cpu] = "R4650";
387 c->isa_level = MIPS_CPU_ISA_III; 412 c->isa_level = MIPS_CPU_ISA_III;
388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 413 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
389 c->tlbsize = 48; 414 c->tlbsize = 48;
@@ -395,25 +420,26 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
395 420
396 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 421 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
397 c->cputype = CPU_TX3927; 422 c->cputype = CPU_TX3927;
423 __cpu_name[cpu] = "TX3927";
398 c->tlbsize = 64; 424 c->tlbsize = 64;
399 } else { 425 } else {
400 switch (c->processor_id & 0xff) { 426 switch (c->processor_id & 0xff) {
401 case PRID_REV_TX3912: 427 case PRID_REV_TX3912:
402 c->cputype = CPU_TX3912; 428 c->cputype = CPU_TX3912;
429 __cpu_name[cpu] = "TX3912";
403 c->tlbsize = 32; 430 c->tlbsize = 32;
404 break; 431 break;
405 case PRID_REV_TX3922: 432 case PRID_REV_TX3922:
406 c->cputype = CPU_TX3922; 433 c->cputype = CPU_TX3922;
434 __cpu_name[cpu] = "TX3922";
407 c->tlbsize = 64; 435 c->tlbsize = 64;
408 break; 436 break;
409 default:
410 c->cputype = CPU_UNKNOWN;
411 break;
412 } 437 }
413 } 438 }
414 break; 439 break;
415 case PRID_IMP_R4700: 440 case PRID_IMP_R4700:
416 c->cputype = CPU_R4700; 441 c->cputype = CPU_R4700;
442 __cpu_name[cpu] = "R4700";
417 c->isa_level = MIPS_CPU_ISA_III; 443 c->isa_level = MIPS_CPU_ISA_III;
418 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 444 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
419 MIPS_CPU_LLSC; 445 MIPS_CPU_LLSC;
@@ -421,6 +447,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
421 break; 447 break;
422 case PRID_IMP_TX49: 448 case PRID_IMP_TX49:
423 c->cputype = CPU_TX49XX; 449 c->cputype = CPU_TX49XX;
450 __cpu_name[cpu] = "R49XX";
424 c->isa_level = MIPS_CPU_ISA_III; 451 c->isa_level = MIPS_CPU_ISA_III;
425 c->options = R4K_OPTS | MIPS_CPU_LLSC; 452 c->options = R4K_OPTS | MIPS_CPU_LLSC;
426 if (!(c->processor_id & 0x08)) 453 if (!(c->processor_id & 0x08))
@@ -429,6 +456,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
429 break; 456 break;
430 case PRID_IMP_R5000: 457 case PRID_IMP_R5000:
431 c->cputype = CPU_R5000; 458 c->cputype = CPU_R5000;
459 __cpu_name[cpu] = "R5000";
432 c->isa_level = MIPS_CPU_ISA_IV; 460 c->isa_level = MIPS_CPU_ISA_IV;
433 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 461 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
434 MIPS_CPU_LLSC; 462 MIPS_CPU_LLSC;
@@ -436,6 +464,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
436 break; 464 break;
437 case PRID_IMP_R5432: 465 case PRID_IMP_R5432:
438 c->cputype = CPU_R5432; 466 c->cputype = CPU_R5432;
467 __cpu_name[cpu] = "R5432";
439 c->isa_level = MIPS_CPU_ISA_IV; 468 c->isa_level = MIPS_CPU_ISA_IV;
440 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 469 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
441 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 470 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -443,6 +472,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
443 break; 472 break;
444 case PRID_IMP_R5500: 473 case PRID_IMP_R5500:
445 c->cputype = CPU_R5500; 474 c->cputype = CPU_R5500;
475 __cpu_name[cpu] = "R5500";
446 c->isa_level = MIPS_CPU_ISA_IV; 476 c->isa_level = MIPS_CPU_ISA_IV;
447 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 477 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
448 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 478 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -450,6 +480,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
450 break; 480 break;
451 case PRID_IMP_NEVADA: 481 case PRID_IMP_NEVADA:
452 c->cputype = CPU_NEVADA; 482 c->cputype = CPU_NEVADA;
483 __cpu_name[cpu] = "Nevada";
453 c->isa_level = MIPS_CPU_ISA_IV; 484 c->isa_level = MIPS_CPU_ISA_IV;
454 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 485 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
455 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 486 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
@@ -457,6 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
457 break; 488 break;
458 case PRID_IMP_R6000: 489 case PRID_IMP_R6000:
459 c->cputype = CPU_R6000; 490 c->cputype = CPU_R6000;
491 __cpu_name[cpu] = "R6000";
460 c->isa_level = MIPS_CPU_ISA_II; 492 c->isa_level = MIPS_CPU_ISA_II;
461 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 493 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
462 MIPS_CPU_LLSC; 494 MIPS_CPU_LLSC;
@@ -464,6 +496,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
464 break; 496 break;
465 case PRID_IMP_R6000A: 497 case PRID_IMP_R6000A:
466 c->cputype = CPU_R6000A; 498 c->cputype = CPU_R6000A;
499 __cpu_name[cpu] = "R6000A";
467 c->isa_level = MIPS_CPU_ISA_II; 500 c->isa_level = MIPS_CPU_ISA_II;
468 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 501 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
469 MIPS_CPU_LLSC; 502 MIPS_CPU_LLSC;
@@ -471,6 +504,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
471 break; 504 break;
472 case PRID_IMP_RM7000: 505 case PRID_IMP_RM7000:
473 c->cputype = CPU_RM7000; 506 c->cputype = CPU_RM7000;
507 __cpu_name[cpu] = "RM7000";
474 c->isa_level = MIPS_CPU_ISA_IV; 508 c->isa_level = MIPS_CPU_ISA_IV;
475 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 509 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
476 MIPS_CPU_LLSC; 510 MIPS_CPU_LLSC;
@@ -486,6 +520,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
486 break; 520 break;
487 case PRID_IMP_RM9000: 521 case PRID_IMP_RM9000:
488 c->cputype = CPU_RM9000; 522 c->cputype = CPU_RM9000;
523 __cpu_name[cpu] = "RM9000";
489 c->isa_level = MIPS_CPU_ISA_IV; 524 c->isa_level = MIPS_CPU_ISA_IV;
490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 525 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
491 MIPS_CPU_LLSC; 526 MIPS_CPU_LLSC;
@@ -500,6 +535,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
500 break; 535 break;
501 case PRID_IMP_R8000: 536 case PRID_IMP_R8000:
502 c->cputype = CPU_R8000; 537 c->cputype = CPU_R8000;
538 __cpu_name[cpu] = "RM8000";
503 c->isa_level = MIPS_CPU_ISA_IV; 539 c->isa_level = MIPS_CPU_ISA_IV;
504 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 540 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
505 MIPS_CPU_FPU | MIPS_CPU_32FPR | 541 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -508,6 +544,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
508 break; 544 break;
509 case PRID_IMP_R10000: 545 case PRID_IMP_R10000:
510 c->cputype = CPU_R10000; 546 c->cputype = CPU_R10000;
547 __cpu_name[cpu] = "R10000";
511 c->isa_level = MIPS_CPU_ISA_IV; 548 c->isa_level = MIPS_CPU_ISA_IV;
512 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 549 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
513 MIPS_CPU_FPU | MIPS_CPU_32FPR | 550 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -517,6 +554,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
517 break; 554 break;
518 case PRID_IMP_R12000: 555 case PRID_IMP_R12000:
519 c->cputype = CPU_R12000; 556 c->cputype = CPU_R12000;
557 __cpu_name[cpu] = "R12000";
520 c->isa_level = MIPS_CPU_ISA_IV; 558 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 559 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
522 MIPS_CPU_FPU | MIPS_CPU_32FPR | 560 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -526,6 +564,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
526 break; 564 break;
527 case PRID_IMP_R14000: 565 case PRID_IMP_R14000:
528 c->cputype = CPU_R14000; 566 c->cputype = CPU_R14000;
567 __cpu_name[cpu] = "R14000";
529 c->isa_level = MIPS_CPU_ISA_IV; 568 c->isa_level = MIPS_CPU_ISA_IV;
530 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 569 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
531 MIPS_CPU_FPU | MIPS_CPU_32FPR | 570 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -535,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
535 break; 574 break;
536 case PRID_IMP_LOONGSON2: 575 case PRID_IMP_LOONGSON2:
537 c->cputype = CPU_LOONGSON2; 576 c->cputype = CPU_LOONGSON2;
577 __cpu_name[cpu] = "ICT Loongson-2";
538 c->isa_level = MIPS_CPU_ISA_III; 578 c->isa_level = MIPS_CPU_ISA_III;
539 c->options = R4K_OPTS | 579 c->options = R4K_OPTS |
540 MIPS_CPU_FPU | MIPS_CPU_LLSC | 580 MIPS_CPU_FPU | MIPS_CPU_LLSC |
@@ -652,21 +692,24 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
652 692
653static void __cpuinit decode_configs(struct cpuinfo_mips *c) 693static void __cpuinit decode_configs(struct cpuinfo_mips *c)
654{ 694{
695 int ok;
696
655 /* MIPS32 or MIPS64 compliant CPU. */ 697 /* MIPS32 or MIPS64 compliant CPU. */
656 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 698 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
657 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 699 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
658 700
659 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 701 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
660 702
661 /* Read Config registers. */ 703 ok = decode_config0(c); /* Read Config registers. */
662 if (!decode_config0(c)) 704 BUG_ON(!ok); /* Arch spec violation! */
663 return; /* actually worth a panic() */ 705 if (ok)
664 if (!decode_config1(c)) 706 ok = decode_config1(c);
665 return; 707 if (ok)
666 if (!decode_config2(c)) 708 ok = decode_config2(c);
667 return; 709 if (ok)
668 if (!decode_config3(c)) 710 ok = decode_config3(c);
669 return; 711
712 mips_probe_watch_registers(c);
670} 713}
671 714
672#ifdef CONFIG_CPU_MIPSR2 715#ifdef CONFIG_CPU_MIPSR2
@@ -675,52 +718,62 @@ extern void spram_config(void);
675static inline void spram_config(void) {} 718static inline void spram_config(void) {}
676#endif 719#endif
677 720
678static inline void cpu_probe_mips(struct cpuinfo_mips *c) 721static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
679{ 722{
680 decode_configs(c); 723 decode_configs(c);
681 mips_probe_watch_registers(c);
682 switch (c->processor_id & 0xff00) { 724 switch (c->processor_id & 0xff00) {
683 case PRID_IMP_4KC: 725 case PRID_IMP_4KC:
684 c->cputype = CPU_4KC; 726 c->cputype = CPU_4KC;
727 __cpu_name[cpu] = "MIPS 4Kc";
685 break; 728 break;
686 case PRID_IMP_4KEC: 729 case PRID_IMP_4KEC:
687 c->cputype = CPU_4KEC; 730 c->cputype = CPU_4KEC;
731 __cpu_name[cpu] = "MIPS 4KEc";
688 break; 732 break;
689 case PRID_IMP_4KECR2: 733 case PRID_IMP_4KECR2:
690 c->cputype = CPU_4KEC; 734 c->cputype = CPU_4KEC;
735 __cpu_name[cpu] = "MIPS 4KEc";
691 break; 736 break;
692 case PRID_IMP_4KSC: 737 case PRID_IMP_4KSC:
693 case PRID_IMP_4KSD: 738 case PRID_IMP_4KSD:
694 c->cputype = CPU_4KSC; 739 c->cputype = CPU_4KSC;
740 __cpu_name[cpu] = "MIPS 4KSc";
695 break; 741 break;
696 case PRID_IMP_5KC: 742 case PRID_IMP_5KC:
697 c->cputype = CPU_5KC; 743 c->cputype = CPU_5KC;
744 __cpu_name[cpu] = "MIPS 5Kc";
698 break; 745 break;
699 case PRID_IMP_20KC: 746 case PRID_IMP_20KC:
700 c->cputype = CPU_20KC; 747 c->cputype = CPU_20KC;
748 __cpu_name[cpu] = "MIPS 20Kc";
701 break; 749 break;
702 case PRID_IMP_24K: 750 case PRID_IMP_24K:
703 case PRID_IMP_24KE: 751 case PRID_IMP_24KE:
704 c->cputype = CPU_24K; 752 c->cputype = CPU_24K;
753 __cpu_name[cpu] = "MIPS 24Kc";
705 break; 754 break;
706 case PRID_IMP_25KF: 755 case PRID_IMP_25KF:
707 c->cputype = CPU_25KF; 756 c->cputype = CPU_25KF;
757 __cpu_name[cpu] = "MIPS 25Kc";
708 break; 758 break;
709 case PRID_IMP_34K: 759 case PRID_IMP_34K:
710 c->cputype = CPU_34K; 760 c->cputype = CPU_34K;
761 __cpu_name[cpu] = "MIPS 34Kc";
711 break; 762 break;
712 case PRID_IMP_74K: 763 case PRID_IMP_74K:
713 c->cputype = CPU_74K; 764 c->cputype = CPU_74K;
765 __cpu_name[cpu] = "MIPS 74Kc";
714 break; 766 break;
715 case PRID_IMP_1004K: 767 case PRID_IMP_1004K:
716 c->cputype = CPU_1004K; 768 c->cputype = CPU_1004K;
769 __cpu_name[cpu] = "MIPS 1004Kc";
717 break; 770 break;
718 } 771 }
719 772
720 spram_config(); 773 spram_config();
721} 774}
722 775
723static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 776static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
724{ 777{
725 decode_configs(c); 778 decode_configs(c);
726 switch (c->processor_id & 0xff00) { 779 switch (c->processor_id & 0xff00) {
@@ -729,23 +782,31 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
729 switch ((c->processor_id >> 24) & 0xff) { 782 switch ((c->processor_id >> 24) & 0xff) {
730 case 0: 783 case 0:
731 c->cputype = CPU_AU1000; 784 c->cputype = CPU_AU1000;
785 __cpu_name[cpu] = "Au1000";
732 break; 786 break;
733 case 1: 787 case 1:
734 c->cputype = CPU_AU1500; 788 c->cputype = CPU_AU1500;
789 __cpu_name[cpu] = "Au1500";
735 break; 790 break;
736 case 2: 791 case 2:
737 c->cputype = CPU_AU1100; 792 c->cputype = CPU_AU1100;
793 __cpu_name[cpu] = "Au1100";
738 break; 794 break;
739 case 3: 795 case 3:
740 c->cputype = CPU_AU1550; 796 c->cputype = CPU_AU1550;
797 __cpu_name[cpu] = "Au1550";
741 break; 798 break;
742 case 4: 799 case 4:
743 c->cputype = CPU_AU1200; 800 c->cputype = CPU_AU1200;
744 if (2 == (c->processor_id & 0xff)) 801 __cpu_name[cpu] = "Au1200";
802 if ((c->processor_id & 0xff) == 2) {
745 c->cputype = CPU_AU1250; 803 c->cputype = CPU_AU1250;
804 __cpu_name[cpu] = "Au1250";
805 }
746 break; 806 break;
747 case 5: 807 case 5:
748 c->cputype = CPU_AU1210; 808 c->cputype = CPU_AU1210;
809 __cpu_name[cpu] = "Au1210";
749 break; 810 break;
750 default: 811 default:
751 panic("Unknown Au Core!"); 812 panic("Unknown Au Core!");
@@ -755,154 +816,67 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
755 } 816 }
756} 817}
757 818
758static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 819static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
759{ 820{
760 decode_configs(c); 821 decode_configs(c);
761 822
762 switch (c->processor_id & 0xff00) { 823 switch (c->processor_id & 0xff00) {
763 case PRID_IMP_SB1: 824 case PRID_IMP_SB1:
764 c->cputype = CPU_SB1; 825 c->cputype = CPU_SB1;
826 __cpu_name[cpu] = "SiByte SB1";
765 /* FPU in pass1 is known to have issues. */ 827 /* FPU in pass1 is known to have issues. */
766 if ((c->processor_id & 0xff) < 0x02) 828 if ((c->processor_id & 0xff) < 0x02)
767 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 829 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
768 break; 830 break;
769 case PRID_IMP_SB1A: 831 case PRID_IMP_SB1A:
770 c->cputype = CPU_SB1A; 832 c->cputype = CPU_SB1A;
833 __cpu_name[cpu] = "SiByte SB1A";
771 break; 834 break;
772 } 835 }
773} 836}
774 837
775static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 838static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
776{ 839{
777 decode_configs(c); 840 decode_configs(c);
778 switch (c->processor_id & 0xff00) { 841 switch (c->processor_id & 0xff00) {
779 case PRID_IMP_SR71000: 842 case PRID_IMP_SR71000:
780 c->cputype = CPU_SR71000; 843 c->cputype = CPU_SR71000;
844 __cpu_name[cpu] = "Sandcraft SR71000";
781 c->scache.ways = 8; 845 c->scache.ways = 8;
782 c->tlbsize = 64; 846 c->tlbsize = 64;
783 break; 847 break;
784 } 848 }
785} 849}
786 850
787static inline void cpu_probe_nxp(struct cpuinfo_mips *c) 851static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
788{ 852{
789 decode_configs(c); 853 decode_configs(c);
790 switch (c->processor_id & 0xff00) { 854 switch (c->processor_id & 0xff00) {
791 case PRID_IMP_PR4450: 855 case PRID_IMP_PR4450:
792 c->cputype = CPU_PR4450; 856 c->cputype = CPU_PR4450;
857 __cpu_name[cpu] = "Philips PR4450";
793 c->isa_level = MIPS_CPU_ISA_M32R1; 858 c->isa_level = MIPS_CPU_ISA_M32R1;
794 break; 859 break;
795 default:
796 panic("Unknown NXP Core!"); /* REVISIT: die? */
797 break;
798 } 860 }
799} 861}
800 862
801 863static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
802static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
803{ 864{
804 decode_configs(c); 865 decode_configs(c);
805 switch (c->processor_id & 0xff00) { 866 switch (c->processor_id & 0xff00) {
806 case PRID_IMP_BCM3302: 867 case PRID_IMP_BCM3302:
807 c->cputype = CPU_BCM3302; 868 c->cputype = CPU_BCM3302;
869 __cpu_name[cpu] = "Broadcom BCM3302";
808 break; 870 break;
809 case PRID_IMP_BCM4710: 871 case PRID_IMP_BCM4710:
810 c->cputype = CPU_BCM4710; 872 c->cputype = CPU_BCM4710;
811 break; 873 __cpu_name[cpu] = "Broadcom BCM4710";
812 default:
813 c->cputype = CPU_UNKNOWN;
814 break; 874 break;
815 } 875 }
816} 876}
817 877
818const char *__cpu_name[NR_CPUS]; 878const char *__cpu_name[NR_CPUS];
819 879
820/*
821 * Name a CPU
822 */
823static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
824{
825 const char *name = NULL;
826
827 switch (c->cputype) {
828 case CPU_UNKNOWN: name = "unknown"; break;
829 case CPU_R2000: name = "R2000"; break;
830 case CPU_R3000: name = "R3000"; break;
831 case CPU_R3000A: name = "R3000A"; break;
832 case CPU_R3041: name = "R3041"; break;
833 case CPU_R3051: name = "R3051"; break;
834 case CPU_R3052: name = "R3052"; break;
835 case CPU_R3081: name = "R3081"; break;
836 case CPU_R3081E: name = "R3081E"; break;
837 case CPU_R4000PC: name = "R4000PC"; break;
838 case CPU_R4000SC: name = "R4000SC"; break;
839 case CPU_R4000MC: name = "R4000MC"; break;
840 case CPU_R4200: name = "R4200"; break;
841 case CPU_R4400PC: name = "R4400PC"; break;
842 case CPU_R4400SC: name = "R4400SC"; break;
843 case CPU_R4400MC: name = "R4400MC"; break;
844 case CPU_R4600: name = "R4600"; break;
845 case CPU_R6000: name = "R6000"; break;
846 case CPU_R6000A: name = "R6000A"; break;
847 case CPU_R8000: name = "R8000"; break;
848 case CPU_R10000: name = "R10000"; break;
849 case CPU_R12000: name = "R12000"; break;
850 case CPU_R14000: name = "R14000"; break;
851 case CPU_R4300: name = "R4300"; break;
852 case CPU_R4650: name = "R4650"; break;
853 case CPU_R4700: name = "R4700"; break;
854 case CPU_R5000: name = "R5000"; break;
855 case CPU_R5000A: name = "R5000A"; break;
856 case CPU_R4640: name = "R4640"; break;
857 case CPU_NEVADA: name = "Nevada"; break;
858 case CPU_RM7000: name = "RM7000"; break;
859 case CPU_RM9000: name = "RM9000"; break;
860 case CPU_R5432: name = "R5432"; break;
861 case CPU_4KC: name = "MIPS 4Kc"; break;
862 case CPU_5KC: name = "MIPS 5Kc"; break;
863 case CPU_R4310: name = "R4310"; break;
864 case CPU_SB1: name = "SiByte SB1"; break;
865 case CPU_SB1A: name = "SiByte SB1A"; break;
866 case CPU_TX3912: name = "TX3912"; break;
867 case CPU_TX3922: name = "TX3922"; break;
868 case CPU_TX3927: name = "TX3927"; break;
869 case CPU_AU1000: name = "Au1000"; break;
870 case CPU_AU1500: name = "Au1500"; break;
871 case CPU_AU1100: name = "Au1100"; break;
872 case CPU_AU1550: name = "Au1550"; break;
873 case CPU_AU1200: name = "Au1200"; break;
874 case CPU_AU1210: name = "Au1210"; break;
875 case CPU_AU1250: name = "Au1250"; break;
876 case CPU_4KEC: name = "MIPS 4KEc"; break;
877 case CPU_4KSC: name = "MIPS 4KSc"; break;
878 case CPU_VR41XX: name = "NEC Vr41xx"; break;
879 case CPU_R5500: name = "R5500"; break;
880 case CPU_TX49XX: name = "TX49xx"; break;
881 case CPU_20KC: name = "MIPS 20Kc"; break;
882 case CPU_24K: name = "MIPS 24K"; break;
883 case CPU_25KF: name = "MIPS 25Kf"; break;
884 case CPU_34K: name = "MIPS 34K"; break;
885 case CPU_1004K: name = "MIPS 1004K"; break;
886 case CPU_74K: name = "MIPS 74K"; break;
887 case CPU_VR4111: name = "NEC VR4111"; break;
888 case CPU_VR4121: name = "NEC VR4121"; break;
889 case CPU_VR4122: name = "NEC VR4122"; break;
890 case CPU_VR4131: name = "NEC VR4131"; break;
891 case CPU_VR4133: name = "NEC VR4133"; break;
892 case CPU_VR4181: name = "NEC VR4181"; break;
893 case CPU_VR4181A: name = "NEC VR4181A"; break;
894 case CPU_SR71000: name = "Sandcraft SR71000"; break;
895 case CPU_BCM3302: name = "Broadcom BCM3302"; break;
896 case CPU_BCM4710: name = "Broadcom BCM4710"; break;
897 case CPU_PR4450: name = "Philips PR4450"; break;
898 case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
899 default:
900 BUG();
901 }
902
903 return name;
904}
905
906__cpuinit void cpu_probe(void) 880__cpuinit void cpu_probe(void)
907{ 881{
908 struct cpuinfo_mips *c = &current_cpu_data; 882 struct cpuinfo_mips *c = &current_cpu_data;
@@ -915,30 +889,31 @@ __cpuinit void cpu_probe(void)
915 c->processor_id = read_c0_prid(); 889 c->processor_id = read_c0_prid();
916 switch (c->processor_id & 0xff0000) { 890 switch (c->processor_id & 0xff0000) {
917 case PRID_COMP_LEGACY: 891 case PRID_COMP_LEGACY:
918 cpu_probe_legacy(c); 892 cpu_probe_legacy(c, cpu);
919 break; 893 break;
920 case PRID_COMP_MIPS: 894 case PRID_COMP_MIPS:
921 cpu_probe_mips(c); 895 cpu_probe_mips(c, cpu);
922 break; 896 break;
923 case PRID_COMP_ALCHEMY: 897 case PRID_COMP_ALCHEMY:
924 cpu_probe_alchemy(c); 898 cpu_probe_alchemy(c, cpu);
925 break; 899 break;
926 case PRID_COMP_SIBYTE: 900 case PRID_COMP_SIBYTE:
927 cpu_probe_sibyte(c); 901 cpu_probe_sibyte(c, cpu);
928 break; 902 break;
929 case PRID_COMP_BROADCOM: 903 case PRID_COMP_BROADCOM:
930 cpu_probe_broadcom(c); 904 cpu_probe_broadcom(c, cpu);
931 break; 905 break;
932 case PRID_COMP_SANDCRAFT: 906 case PRID_COMP_SANDCRAFT:
933 cpu_probe_sandcraft(c); 907 cpu_probe_sandcraft(c, cpu);
934 break; 908 break;
935 case PRID_COMP_NXP: 909 case PRID_COMP_NXP:
936 cpu_probe_nxp(c); 910 cpu_probe_nxp(c, cpu);
937 break; 911 break;
938 default:
939 c->cputype = CPU_UNKNOWN;
940 } 912 }
941 913
914 BUG_ON(!__cpu_name[cpu]);
915 BUG_ON(c->cputype == CPU_UNKNOWN);
916
942 /* 917 /*
943 * Platform code can force the cpu type to optimize code 918 * Platform code can force the cpu type to optimize code
944 * generation. In that case be sure the cpu type is correctly 919 * generation. In that case be sure the cpu type is correctly
@@ -958,8 +933,6 @@ __cpuinit void cpu_probe(void)
958 } 933 }
959 } 934 }
960 935
961 __cpu_name[cpu] = cpu_to_name(c);
962
963 if (cpu_has_mips_r2) 936 if (cpu_has_mips_r2)
964 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 937 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
965 else 938 else
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 5e75a316f6b1..759f68066b5d 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -180,7 +180,7 @@ bad_stack:
180 * The system call does not exist in this kernel 180 * The system call does not exist in this kernel
181 */ 181 */
182illegal_syscall: 182illegal_syscall:
183 li v0, -ENOSYS # error 183 li v0, ENOSYS # error
184 sw v0, PT_R2(sp) 184 sw v0, PT_R2(sp)
185 li t0, 1 # set error flag 185 li t0, 1 # set error flag
186 sw t0, PT_R7(sp) 186 sw t0, PT_R7(sp)
@@ -293,7 +293,7 @@ bad_alignment:
293 jr t2 293 jr t2
294 /* Unreached */ 294 /* Unreached */
295 295
296einval: li v0, -EINVAL 296einval: li v0, -ENOSYS
297 jr ra 297 jr ra
298 END(sys_syscall) 298 END(sys_syscall)
299 299
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 3d58204c9d44..a9e171618994 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -117,7 +117,7 @@ syscall_trace_entry:
117 117
118illegal_syscall: 118illegal_syscall:
119 /* This also isn't a 64-bit syscall, throw an error. */ 119 /* This also isn't a 64-bit syscall, throw an error. */
120 li v0, -ENOSYS # error 120 li v0, ENOSYS # error
121 sd v0, PT_R2(sp) 121 sd v0, PT_R2(sp)
122 li t0, 1 # set error flag 122 li t0, 1 # set error flag
123 sd t0, PT_R7(sp) 123 sd t0, PT_R7(sp)
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 16f8edfe5cdc..4430a1f8fdf1 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -601,8 +601,8 @@ static int __init debugfs_mips(void)
601 struct dentry *d; 601 struct dentry *d;
602 602
603 d = debugfs_create_dir("mips", NULL); 603 d = debugfs_create_dir("mips", NULL);
604 if (IS_ERR(d)) 604 if (!d)
605 return PTR_ERR(d); 605 return -ENOMEM;
606 mips_debugfs_dir = d; 606 mips_debugfs_dir = d;
607 return 0; 607 return 0;
608} 608}
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 7b59cfb7e602..8bf88faf5afd 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -163,8 +163,10 @@ static void stop_this_cpu(void *dummy)
163 * Remove this CPU: 163 * Remove this CPU:
164 */ 164 */
165 cpu_clear(smp_processor_id(), cpu_online_map); 165 cpu_clear(smp_processor_id(), cpu_online_map);
166 local_irq_enable(); /* May need to service _machine_restart IPI */ 166 for (;;) {
167 for (;;); /* Wait if available. */ 167 if (cpu_wait)
168 (*cpu_wait)(); /* Wait if available. */
169 }
168} 170}
169 171
170void smp_send_stop(void) 172void smp_send_stop(void)
@@ -193,12 +195,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
193/* preload SMP state for boot cpu */ 195/* preload SMP state for boot cpu */
194void __devinit smp_prepare_boot_cpu(void) 196void __devinit smp_prepare_boot_cpu(void)
195{ 197{
196 /*
197 * This assumes that bootup is always handled by the processor
198 * with the logic and physical number 0.
199 */
200 __cpu_number_map[0] = 0;
201 __cpu_logical_map[0] = 0;
202 cpu_set(0, phys_cpu_present_map); 198 cpu_set(0, phys_cpu_present_map);
203 cpu_set(0, cpu_online_map); 199 cpu_set(0, cpu_online_map);
204 cpu_set(0, cpu_callin_map); 200 cpu_set(0, cpu_callin_map);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 80b9e070c207..353056110f2b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -32,6 +32,7 @@
32#include <asm/cpu.h> 32#include <asm/cpu.h>
33#include <asm/dsp.h> 33#include <asm/dsp.h>
34#include <asm/fpu.h> 34#include <asm/fpu.h>
35#include <asm/fpu_emulator.h>
35#include <asm/mipsregs.h> 36#include <asm/mipsregs.h>
36#include <asm/mipsmtregs.h> 37#include <asm/mipsmtregs.h>
37#include <asm/module.h> 38#include <asm/module.h>
@@ -722,6 +723,21 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
722 die_if_kernel("Kernel bug detected", regs); 723 die_if_kernel("Kernel bug detected", regs);
723 force_sig(SIGTRAP, current); 724 force_sig(SIGTRAP, current);
724 break; 725 break;
726 case BRK_MEMU:
727 /*
728 * Address errors may be deliberately induced by the FPU
729 * emulator to retake control of the CPU after executing the
730 * instruction in the delay slot of an emulated branch.
731 *
732 * Terminate if exception was recognized as a delay slot return
733 * otherwise handle as normal.
734 */
735 if (do_dsemulret(regs))
736 return;
737
738 die_if_kernel("Math emu break/trap", regs);
739 force_sig(SIGTRAP, current);
740 break;
725 default: 741 default:
726 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 742 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
727 die_if_kernel(b, regs); 743 die_if_kernel(b, regs);
@@ -1555,6 +1571,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1555#ifdef CONFIG_64BIT 1571#ifdef CONFIG_64BIT
1556 unsigned long uncached_ebase = TO_UNCAC(ebase); 1572 unsigned long uncached_ebase = TO_UNCAC(ebase);
1557#endif 1573#endif
1574 if (cpu_has_mips_r2)
1575 ebase += (read_c0_ebase() & 0x3ffff000);
1558 1576
1559 if (!addr) 1577 if (!addr)
1560 panic(panic_null_cerr); 1578 panic(panic_null_cerr);
@@ -1588,8 +1606,11 @@ void __init trap_init(void)
1588 1606
1589 if (cpu_has_veic || cpu_has_vint) 1607 if (cpu_has_veic || cpu_has_vint)
1590 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1608 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1591 else 1609 else {
1592 ebase = CAC_BASE; 1610 ebase = CAC_BASE;
1611 if (cpu_has_mips_r2)
1612 ebase += (read_c0_ebase() & 0x3ffff000);
1613 }
1593 1614
1594 per_cpu_trap_init(); 1615 per_cpu_trap_init();
1595 1616
@@ -1697,11 +1718,11 @@ void __init trap_init(void)
1697 1718
1698 if (cpu_has_vce) 1719 if (cpu_has_vce)
1699 /* Special exception: R4[04]00 uses also the divec space. */ 1720 /* Special exception: R4[04]00 uses also the divec space. */
1700 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1721 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1701 else if (cpu_has_4kex) 1722 else if (cpu_has_4kex)
1702 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1723 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1703 else 1724 else
1704 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1725 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1705 1726
1706 signal_init(); 1727 signal_init();
1707#ifdef CONFIG_MIPS32_COMPAT 1728#ifdef CONFIG_MIPS32_COMPAT
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index c327b21bca81..bf4c4a979abb 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -499,22 +499,10 @@ sigill:
499 499
500asmlinkage void do_ade(struct pt_regs *regs) 500asmlinkage void do_ade(struct pt_regs *regs)
501{ 501{
502 extern int do_dsemulret(struct pt_regs *);
503 unsigned int __user *pc; 502 unsigned int __user *pc;
504 mm_segment_t seg; 503 mm_segment_t seg;
505 504
506 /* 505 /*
507 * Address errors may be deliberately induced by the FPU emulator to
508 * retake control of the CPU after executing the instruction in the
509 * delay slot of an emulated branch.
510 */
511 /* Terminate if exception was recognized as a delay slot return */
512 if (do_dsemulret(regs))
513 return;
514
515 /* Otherwise handle as normal */
516
517 /*
518 * Did we catch a fault trying to load an instruction? 506 * Did we catch a fault trying to load an instruction?
519 * Or are we running in MIPS16 mode? 507 * Or are we running in MIPS16 mode?
520 */ 508 */
@@ -560,12 +548,12 @@ static int __init debugfs_unaligned(void)
560 return -ENODEV; 548 return -ENODEV;
561 d = debugfs_create_u32("unaligned_instructions", S_IRUGO, 549 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
562 mips_debugfs_dir, &unaligned_instructions); 550 mips_debugfs_dir, &unaligned_instructions);
563 if (IS_ERR(d)) 551 if (!d)
564 return PTR_ERR(d); 552 return -ENOMEM;
565 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR, 553 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
566 mips_debugfs_dir, &unaligned_action); 554 mips_debugfs_dir, &unaligned_action);
567 if (IS_ERR(d)) 555 if (!d)
568 return PTR_ERR(d); 556 return -ENOMEM;
569 return 0; 557 return 0;
570} 558}
571__initcall(debugfs_unaligned); 559__initcall(debugfs_unaligned);
diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c
index c1e41f15cc7e..8be03a8e1ad4 100644
--- a/arch/mips/lemote/lm2e/pci.c
+++ b/arch/mips/lemote/lm2e/pci.c
@@ -30,19 +30,20 @@
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/mips-boards/bonito64.h> 32#include <asm/mips-boards/bonito64.h>
33#include <asm/mach-lemote/pci.h>
33 34
34extern struct pci_ops bonito64_pci_ops; 35extern struct pci_ops bonito64_pci_ops;
35 36
36static struct resource loongson2e_pci_mem_resource = { 37static struct resource loongson2e_pci_mem_resource = {
37 .name = "LOONGSON2E PCI MEM", 38 .name = "LOONGSON2E PCI MEM",
38 .start = 0x14000000UL, 39 .start = LOONGSON2E_PCI_MEM_START,
39 .end = 0x1fffffffUL, 40 .end = LOONGSON2E_PCI_MEM_END,
40 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
41}; 42};
42 43
43static struct resource loongson2e_pci_io_resource = { 44static struct resource loongson2e_pci_io_resource = {
44 .name = "LOONGSON2E PCI IO MEM", 45 .name = "LOONGSON2E PCI IO MEM",
45 .start = 0x00004000UL, 46 .start = LOONGSON2E_PCI_IO_START,
46 .end = IO_SPACE_LIMIT, 47 .end = IO_SPACE_LIMIT,
47 .flags = IORESOURCE_IO, 48 .flags = IORESOURCE_IO,
48}; 49};
@@ -82,6 +83,12 @@ static void __init ict_pcimap(void)
82static int __init pcibios_init(void) 83static int __init pcibios_init(void)
83{ 84{
84 ict_pcimap(); 85 ict_pcimap();
86
87 loongson2e_pci_controller.io_map_base =
88 (unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE,
89 loongson2e_pci_io_resource.end -
90 loongson2e_pci_io_resource.start + 1);
91
85 register_pci_controller(&loongson2e_pci_controller); 92 register_pci_controller(&loongson2e_pci_controller);
86 93
87 return 0; 94 return 0;
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
index 2cc6745991ab..ebd6ceaef2fd 100644
--- a/arch/mips/lemote/lm2e/setup.c
+++ b/arch/mips/lemote/lm2e/setup.c
@@ -34,6 +34,7 @@
34#include <asm/mc146818-time.h> 34#include <asm/mc146818-time.h>
35#include <asm/time.h> 35#include <asm/time.h>
36#include <asm/wbflush.h> 36#include <asm/wbflush.h>
37#include <asm/mach-lemote/pci.h>
37 38
38#ifdef CONFIG_VT 39#ifdef CONFIG_VT
39#include <linux/console.h> 40#include <linux/console.h>
@@ -42,12 +43,6 @@
42 43
43extern void mips_reboot_setup(void); 44extern void mips_reboot_setup(void);
44 45
45#ifdef CONFIG_64BIT
46#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p)))
47#else
48#define PTR_PAD(p) (p)
49#endif
50
51unsigned long cpu_clock_freq; 46unsigned long cpu_clock_freq;
52unsigned long bus_clock; 47unsigned long bus_clock;
53unsigned int memsize; 48unsigned int memsize;
@@ -80,8 +75,8 @@ static void wbflush_loongson2e(void)
80 75
81void __init plat_mem_setup(void) 76void __init plat_mem_setup(void)
82{ 77{
83 set_io_port_base(PTR_PAD(0xbfd00000)); 78 set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE,
84 79 IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1));
85 mips_reboot_setup(); 80 mips_reboot_setup();
86 81
87 __wbflush = wbflush_loongson2e; 82 __wbflush = wbflush_loongson2e;
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 8810dfb915dd..dbcf6511b74e 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CPU_R4300) += dump_tlb.o
18obj-$(CONFIG_CPU_R4X00) += dump_tlb.o 18obj-$(CONFIG_CPU_R4X00) += dump_tlb.o
19obj-$(CONFIG_CPU_R5000) += dump_tlb.o 19obj-$(CONFIG_CPU_R5000) += dump_tlb.o
20obj-$(CONFIG_CPU_R5432) += dump_tlb.o 20obj-$(CONFIG_CPU_R5432) += dump_tlb.o
21obj-$(CONFIG_CPU_R5500) += dump_tlb.o
21obj-$(CONFIG_CPU_R6000) += 22obj-$(CONFIG_CPU_R6000) +=
22obj-$(CONFIG_CPU_R8000) += 23obj-$(CONFIG_CPU_R8000) +=
23obj-$(CONFIG_CPU_RM7000) += dump_tlb.o 24obj-$(CONFIG_CPU_RM7000) += dump_tlb.o
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 465ff0ec85b9..779821cd54ab 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -25,6 +25,7 @@ static inline const char *msk2str(unsigned int mask)
25 case PM_16M: return "16Mb"; 25 case PM_16M: return "16Mb";
26 case PM_64M: return "64Mb"; 26 case PM_64M: return "64Mb";
27 case PM_256M: return "256Mb"; 27 case PM_256M: return "256Mb";
28 case PM_1G: return "1Gb";
28#endif 29#endif
29 } 30 }
30 return ""; 31 return "";
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index b08fc65c13a6..890f77927d62 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -48,7 +48,6 @@
48#include <asm/branch.h> 48#include <asm/branch.h>
49 49
50#include "ieee754.h" 50#include "ieee754.h"
51#include "dsemul.h"
52 51
53/* Strap kernel emulator for full MIPS IV emulation */ 52/* Strap kernel emulator for full MIPS IV emulation */
54 53
@@ -346,9 +345,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
346 /* cop control register rd -> gpr[rt] */ 345 /* cop control register rd -> gpr[rt] */
347 u32 value; 346 u32 value;
348 347
349 if (ir == CP1UNDEF) {
350 return do_dsemulret(xcp);
351 }
352 if (MIPSInst_RD(ir) == FPCREG_CSR) { 348 if (MIPSInst_RD(ir) == FPCREG_CSR) {
353 value = ctx->fcr31; 349 value = ctx->fcr31;
354 value = (value & ~0x3) | mips_rm[value & 0x3]; 350 value = (value & ~0x3) | mips_rm[value & 0x3];
@@ -1299,12 +1295,12 @@ static int __init debugfs_fpuemu(void)
1299 if (!mips_debugfs_dir) 1295 if (!mips_debugfs_dir)
1300 return -ENODEV; 1296 return -ENODEV;
1301 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); 1297 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1302 if (IS_ERR(dir)) 1298 if (!dir)
1303 return PTR_ERR(dir); 1299 return -ENOMEM;
1304 for (i = 0; i < ARRAY_SIZE(vars); i++) { 1300 for (i = 0; i < ARRAY_SIZE(vars); i++) {
1305 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v); 1301 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
1306 if (IS_ERR(d)) 1302 if (!d)
1307 return PTR_ERR(d); 1303 return -ENOMEM;
1308 } 1304 }
1309 return 0; 1305 return 0;
1310} 1306}
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index 653e325849e4..df7b9d928efc 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -18,7 +18,6 @@
18#include <asm/fpu_emulator.h> 18#include <asm/fpu_emulator.h>
19 19
20#include "ieee754.h" 20#include "ieee754.h"
21#include "dsemul.h"
22 21
23/* Strap kernel emulator for full MIPS IV emulation */ 22/* Strap kernel emulator for full MIPS IV emulation */
24 23
@@ -94,7 +93,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
94 return SIGBUS; 93 return SIGBUS;
95 94
96 err = __put_user(ir, &fr->emul); 95 err = __put_user(ir, &fr->emul);
97 err |= __put_user((mips_instruction)BADINST, &fr->badinst); 96 err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst);
98 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); 97 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
99 err |= __put_user(cpc, &fr->epc); 98 err |= __put_user(cpc, &fr->epc);
100 99
@@ -130,13 +129,13 @@ int do_dsemulret(struct pt_regs *xcp)
130 /* 129 /*
131 * Do some sanity checking on the stackframe: 130 * Do some sanity checking on the stackframe:
132 * 131 *
133 * - Is the instruction pointed to by the EPC an BADINST? 132 * - Is the instruction pointed to by the EPC an BREAK_MATH?
134 * - Is the following memory word the BD_COOKIE? 133 * - Is the following memory word the BD_COOKIE?
135 */ 134 */
136 err = __get_user(insn, &fr->badinst); 135 err = __get_user(insn, &fr->badinst);
137 err |= __get_user(cookie, &fr->cookie); 136 err |= __get_user(cookie, &fr->cookie);
138 137
139 if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { 138 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
140 fpuemustats.errors++; 139 fpuemustats.errors++;
141 return 0; 140 return 0;
142 } 141 }
diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h
deleted file mode 100644
index 091f0e76730f..000000000000
--- a/arch/mips/math-emu/dsemul.h
+++ /dev/null
@@ -1,17 +0,0 @@
1extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc);
2extern int do_dsemulret(struct pt_regs *xcp);
3
4/* Instruction which will always cause an address error */
5#define AdELOAD 0x8c000001 /* lw $0,1($0) */
6/* Instruction which will plainly cause a CP1 exception when FPU is disabled */
7#define CP1UNDEF 0x44400001 /* cfc1 $0,$0 undef */
8
9/* Instruction inserted following the badinst to further tag the sequence */
10#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */
11
12/* Setup which instruction to use for trampoline */
13#ifdef STANDALONE_EMULATOR
14#define BADINST CP1UNDEF
15#else
16#define BADINST AdELOAD
17#endif
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 44e8dd8106bf..95ba32b5b720 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o
19obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o 19obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o
20obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o 20obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o
21obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o 21obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o
22obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o
22obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o 23obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o
23obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o 24obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o
24obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o 25obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 891312f8e5a6..5b98d0e731c2 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -324,7 +324,6 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
324 if (cpu_is_noncoherent_r10000(dev)) 324 if (cpu_is_noncoherent_r10000(dev))
325 __dma_sync((unsigned long)page_address(sg_page(sg)), 325 __dma_sync((unsigned long)page_address(sg_page(sg)),
326 sg->length, direction); 326 sg->length, direction);
327 plat_unmap_dma_mem(sg->dma_address);
328 } 327 }
329} 328}
330 329
@@ -342,7 +341,6 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele
342 if (!plat_device_is_coherent(dev)) 341 if (!plat_device_is_coherent(dev))
343 __dma_sync((unsigned long)page_address(sg_page(sg)), 342 __dma_sync((unsigned long)page_address(sg_page(sg)),
344 sg->length, direction); 343 sg->length, direction);
345 plat_unmap_dma_mem(sg->dma_address);
346 } 344 }
347} 345}
348 346
diff --git a/arch/mips/nxp/pnx833x/common/Makefile b/arch/mips/nxp/pnx833x/common/Makefile
new file mode 100644
index 000000000000..4a16f3b503b5
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/Makefile
@@ -0,0 +1,3 @@
1obj-y := interrupts.o platform.o prom.o setup.o reset.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c
new file mode 100644
index 000000000000..30533ba200e2
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/interrupts.c
@@ -0,0 +1,380 @@
1/*
2 * interrupts.c: Interrupt mappings for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22#include <linux/kernel.h>
23#include <linux/irq.h>
24#include <linux/hardirq.h>
25#include <linux/interrupt.h>
26#include <asm/mipsregs.h>
27#include <asm/irq_cpu.h>
28#include <irq.h>
29#include <irq-mapping.h>
30#include <gpio.h>
31
32static int mips_cpu_timer_irq;
33
34static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
35{
36 0, /* unused */
37 4, /* PNX833X_PIC_I2C0_INT 1 */
38 4, /* PNX833X_PIC_I2C1_INT 2 */
39 1, /* PNX833X_PIC_UART0_INT 3 */
40 1, /* PNX833X_PIC_UART1_INT 4 */
41 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */
42 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */
43 7, /* PNX833X_PIC_GPIO_INT 7 */
44 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */
45 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */
46 4, /* PNX833X_PIC_CONFIG_INT 10 */
47 4, /* PNX833X_PIC_AOI_INT 11 */
48 9, /* PNX833X_PIC_SYNC_INT 12 */
49 9, /* PNX8335_PIC_SATA_INT 13 */
50 4, /* PNX833X_PIC_OSD_INT 14 */
51 9, /* PNX833X_PIC_DISP1_INT 15 */
52 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */
53 9, /* PNX833X_PIC_DISPLAY2_INT 17 */
54 4, /* PNX833X_PIC_VC_INT 18 */
55 4, /* PNX833X_PIC_SC_INT 19 */
56 9, /* PNX833X_PIC_IDE_INT 20 */
57 9, /* PNX833X_PIC_IDE_DMA_INT 21 */
58 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */
59 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */
60 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */
61 4, /* PNX833X_PIC_TS_OUT_INT 25 */
62 4, /* PNX833X_PIC_IR_INT 26 */
63 3, /* PNX833X_PIC_VMSP1_INT 27 */
64 3, /* PNX833X_PIC_VMSP2_INT 28 */
65 4, /* PNX833X_PIC_PIBC_INT 29 */
66 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */
67 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */
68 5, /* PNX833X_PIC_USB_INT 32 */
69 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */
70 4, /* PNX833X_PIC_CLOCK_INT 34 */
71 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */
72 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */
73#if defined(CONFIG_SOC_PNX8335)
74 4, /* PNX8335_PIC_MIU_INT 37 */
75 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */
76 9, /* PNX8335_PIC_SYNC_HD_INT 39 */
77 9, /* PNX8335_PIC_DISP_HD_INT 40 */
78 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */
79 4, /* PNX8335_PIC_OSD_HD1_INT 42 */
80 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */
81 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */
82 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */
83 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */
84 4, /* PNX8335_PIC_DENC_TTX_INT 47 */
85 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */
86 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */
87 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */
88 4, /* PNX8335_PIC_PIBCS_INT 51 */
89 12, /* PNX8335_PIC_ETHERNET_INT 52 */
90 3, /* PNX8335_PIC_VMSP1_0_INT 53 */
91 3, /* PNX8335_PIC_VMSP1_1_INT 54 */
92 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */
93 4, /* PNX8335_PIC_TDGR_DE_INT 56 */
94 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */
95#endif
96};
97
98static void pnx833x_timer_dispatch(void)
99{
100 do_IRQ(mips_cpu_timer_irq);
101}
102
103static void pic_dispatch(void)
104{
105 unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
106
107 if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
108 unsigned long priority = PNX833X_PIC_INT_PRIORITY;
109 PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
110
111 if (irq == PNX833X_PIC_GPIO_INT) {
112 unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
113 int pin;
114 while ((pin = ffs(mask & 0xffff))) {
115 pin -= 1;
116 do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
117 mask &= ~(1 << pin);
118 }
119 } else {
120 do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
121 }
122
123 PNX833X_PIC_INT_PRIORITY = priority;
124 } else {
125 printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
126 }
127}
128
129asmlinkage void plat_irq_dispatch(void)
130{
131 unsigned int pending = read_c0_status() & read_c0_cause();
132
133 if (pending & STATUSF_IP4)
134 pic_dispatch();
135 else if (pending & STATUSF_IP7)
136 do_IRQ(PNX833X_TIMER_IRQ);
137 else
138 spurious_interrupt();
139}
140
141static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
142{
143 /* Currently we do this by setting IRQ priority to 1.
144 If priority support is being implemented, 1 should be repalced
145 by a better value. */
146 PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
147}
148
149static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
150{
151 /* Disable IRQ by writing setting it's priority to 0 */
152 PNX833X_PIC_INT_REG(irq) = 0;
153}
154
155static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */
156#define IRQFLAG_STARTED 1
157#define IRQFLAG_DISABLED 2
158
159static DEFINE_SPINLOCK(pnx833x_irq_lock);
160
161static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
162{
163 unsigned long flags;
164 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
165
166 spin_lock_irqsave(&pnx833x_irq_lock, flags);
167
168 irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */
169 pnx833x_hard_enable_pic_irq(pic_irq);
170
171 spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
172 return 0;
173}
174
175static void pnx833x_shutdown_pic_irq(unsigned int irq)
176{
177 unsigned long flags;
178 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
179
180 spin_lock_irqsave(&pnx833x_irq_lock, flags);
181
182 irqflags[pic_irq] = 0; /* not started */
183 pnx833x_hard_disable_pic_irq(pic_irq);
184
185 spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
186}
187
188static void pnx833x_enable_pic_irq(unsigned int irq)
189{
190 unsigned long flags;
191 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
192
193 spin_lock_irqsave(&pnx833x_irq_lock, flags);
194
195 irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
196 if (irqflags[pic_irq] == IRQFLAG_STARTED)
197 pnx833x_hard_enable_pic_irq(pic_irq);
198
199 spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
200}
201
202static void pnx833x_disable_pic_irq(unsigned int irq)
203{
204 unsigned long flags;
205 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
206
207 spin_lock_irqsave(&pnx833x_irq_lock, flags);
208
209 irqflags[pic_irq] |= IRQFLAG_DISABLED;
210 pnx833x_hard_disable_pic_irq(pic_irq);
211
212 spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
213}
214
215static void pnx833x_ack_pic_irq(unsigned int irq)
216{
217}
218
219static void pnx833x_end_pic_irq(unsigned int irq)
220{
221}
222
223static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
224
225static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
226{
227 int pin = irq - PNX833X_GPIO_IRQ_BASE;
228 unsigned long flags;
229 spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
230 pnx833x_gpio_enable_irq(pin);
231 spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
232 return 0;
233}
234
235static void pnx833x_enable_gpio_irq(unsigned int irq)
236{
237 int pin = irq - PNX833X_GPIO_IRQ_BASE;
238 unsigned long flags;
239 spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
240 pnx833x_gpio_enable_irq(pin);
241 spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
242}
243
244static void pnx833x_disable_gpio_irq(unsigned int irq)
245{
246 int pin = irq - PNX833X_GPIO_IRQ_BASE;
247 unsigned long flags;
248 spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
249 pnx833x_gpio_disable_irq(pin);
250 spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
251}
252
253static void pnx833x_ack_gpio_irq(unsigned int irq)
254{
255}
256
257static void pnx833x_end_gpio_irq(unsigned int irq)
258{
259 int pin = irq - PNX833X_GPIO_IRQ_BASE;
260 unsigned long flags;
261 spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
262 pnx833x_gpio_clear_irq(pin);
263 spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
264}
265
266static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
267{
268 int pin = irq - PNX833X_GPIO_IRQ_BASE;
269 int gpio_mode;
270
271 switch (flow_type) {
272 case IRQ_TYPE_EDGE_RISING:
273 gpio_mode = GPIO_INT_EDGE_RISING;
274 break;
275 case IRQ_TYPE_EDGE_FALLING:
276 gpio_mode = GPIO_INT_EDGE_FALLING;
277 break;
278 case IRQ_TYPE_EDGE_BOTH:
279 gpio_mode = GPIO_INT_EDGE_BOTH;
280 break;
281 case IRQ_TYPE_LEVEL_HIGH:
282 gpio_mode = GPIO_INT_LEVEL_HIGH;
283 break;
284 case IRQ_TYPE_LEVEL_LOW:
285 gpio_mode = GPIO_INT_LEVEL_LOW;
286 break;
287 default:
288 gpio_mode = GPIO_INT_NONE;
289 break;
290 }
291
292 pnx833x_gpio_setup_irq(gpio_mode, pin);
293
294 return 0;
295}
296
297static struct irq_chip pnx833x_pic_irq_type = {
298 .typename = "PNX-PIC",
299 .startup = pnx833x_startup_pic_irq,
300 .shutdown = pnx833x_shutdown_pic_irq,
301 .enable = pnx833x_enable_pic_irq,
302 .disable = pnx833x_disable_pic_irq,
303 .ack = pnx833x_ack_pic_irq,
304 .end = pnx833x_end_pic_irq
305};
306
307static struct irq_chip pnx833x_gpio_irq_type = {
308 .typename = "PNX-GPIO",
309 .startup = pnx833x_startup_gpio_irq,
310 .shutdown = pnx833x_disable_gpio_irq,
311 .enable = pnx833x_enable_gpio_irq,
312 .disable = pnx833x_disable_gpio_irq,
313 .ack = pnx833x_ack_gpio_irq,
314 .end = pnx833x_end_gpio_irq,
315 .set_type = pnx833x_set_type_gpio_irq
316};
317
318void __init arch_init_irq(void)
319{
320 unsigned int irq;
321
322 /* setup standard internal cpu irqs */
323 mips_cpu_irq_init();
324
325 /* Set IRQ information in irq_desc */
326 for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
327 pnx833x_hard_disable_pic_irq(irq);
328 set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
329 }
330
331 for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
332 set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
333
334 /* Set PIC priority limiter register to 0 */
335 PNX833X_PIC_INT_PRIORITY = 0;
336
337 /* Setup GPIO IRQ dispatching */
338 pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
339
340 /* Enable PIC IRQs (HWIRQ2) */
341 if (cpu_has_vint)
342 set_vi_handler(4, pic_dispatch);
343
344 write_c0_status(read_c0_status() | IE_IRQ2);
345}
346
347unsigned int __cpuinit get_c0_compare_int(void)
348{
349 if (cpu_has_vint)
350 set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
351
352 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
353 return mips_cpu_timer_irq;
354}
355
356void __init plat_time_init(void)
357{
358 /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
359
360 extern unsigned long mips_hpt_frequency;
361 unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
362
363 if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
364 /* Functional clock is disabled so use crystal frequency */
365 mips_hpt_frequency = 25;
366 } else {
367#if defined(CONFIG_SOC_PNX8335)
368 /* Functional clock is enabled, so get clock multiplier */
369 mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
370#else
371 static const unsigned long int freq[4] = {240, 160, 120, 80};
372 mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
373#endif
374 }
375
376 printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
377
378 mips_hpt_frequency *= 500000;
379}
380
diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/nxp/pnx833x/common/platform.c
new file mode 100644
index 000000000000..b1ccbcc18f78
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/platform.c
@@ -0,0 +1,319 @@
1/*
2 * platform.c: platform support for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * Based on software written by:
9 * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/device.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <linux/resource.h>
31#include <linux/serial.h>
32#include <linux/serial_pnx8xxx.h>
33#include <linux/mtd/nand.h>
34#include <linux/mtd/partitions.h>
35
36#ifdef CONFIG_I2C_PNX0105
37/* Until i2c driver available in kernel.*/
38#include <linux/i2c-pnx0105.h>
39#endif
40
41#include <irq.h>
42#include <irq-mapping.h>
43#include <pnx833x.h>
44
45static u64 uart_dmamask = DMA_32BIT_MASK;
46
47static struct resource pnx833x_uart_resources[] = {
48 [0] = {
49 .start = PNX833X_UART0_PORTS_START,
50 .end = PNX833X_UART0_PORTS_END,
51 .flags = IORESOURCE_MEM,
52 },
53 [1] = {
54 .start = PNX833X_PIC_UART0_INT,
55 .end = PNX833X_PIC_UART0_INT,
56 .flags = IORESOURCE_IRQ,
57 },
58 [2] = {
59 .start = PNX833X_UART1_PORTS_START,
60 .end = PNX833X_UART1_PORTS_END,
61 .flags = IORESOURCE_MEM,
62 },
63 [3] = {
64 .start = PNX833X_PIC_UART1_INT,
65 .end = PNX833X_PIC_UART1_INT,
66 .flags = IORESOURCE_IRQ,
67 },
68};
69
70struct pnx8xxx_port pnx8xxx_ports[] = {
71 [0] = {
72 .port = {
73 .type = PORT_PNX8XXX,
74 .iotype = UPIO_MEM,
75 .membase = (void __iomem *)PNX833X_UART0_PORTS_START,
76 .mapbase = PNX833X_UART0_PORTS_START,
77 .irq = PNX833X_PIC_UART0_INT,
78 .uartclk = 3692300,
79 .fifosize = 16,
80 .flags = UPF_BOOT_AUTOCONF,
81 .line = 0,
82 },
83 },
84 [1] = {
85 .port = {
86 .type = PORT_PNX8XXX,
87 .iotype = UPIO_MEM,
88 .membase = (void __iomem *)PNX833X_UART1_PORTS_START,
89 .mapbase = PNX833X_UART1_PORTS_START,
90 .irq = PNX833X_PIC_UART1_INT,
91 .uartclk = 3692300,
92 .fifosize = 16,
93 .flags = UPF_BOOT_AUTOCONF,
94 .line = 1,
95 },
96 },
97};
98
99static struct platform_device pnx833x_uart_device = {
100 .name = "pnx8xxx-uart",
101 .id = -1,
102 .dev = {
103 .dma_mask = &uart_dmamask,
104 .coherent_dma_mask = DMA_32BIT_MASK,
105 .platform_data = pnx8xxx_ports,
106 },
107 .num_resources = ARRAY_SIZE(pnx833x_uart_resources),
108 .resource = pnx833x_uart_resources,
109};
110
111static u64 ehci_dmamask = DMA_32BIT_MASK;
112
113static struct resource pnx833x_usb_ehci_resources[] = {
114 [0] = {
115 .start = PNX833X_USB_PORTS_START,
116 .end = PNX833X_USB_PORTS_END,
117 .flags = IORESOURCE_MEM,
118 },
119 [1] = {
120 .start = PNX833X_PIC_USB_INT,
121 .end = PNX833X_PIC_USB_INT,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device pnx833x_usb_ehci_device = {
127 .name = "pnx833x-ehci",
128 .id = -1,
129 .dev = {
130 .dma_mask = &ehci_dmamask,
131 .coherent_dma_mask = DMA_32BIT_MASK,
132 },
133 .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources),
134 .resource = pnx833x_usb_ehci_resources,
135};
136
137#ifdef CONFIG_I2C_PNX0105
138static struct resource pnx833x_i2c0_resources[] = {
139 {
140 .start = PNX833X_I2C0_PORTS_START,
141 .end = PNX833X_I2C0_PORTS_END,
142 .flags = IORESOURCE_MEM,
143 },
144 {
145 .start = PNX833X_PIC_I2C0_INT,
146 .end = PNX833X_PIC_I2C0_INT,
147 .flags = IORESOURCE_IRQ,
148 },
149};
150
151static struct resource pnx833x_i2c1_resources[] = {
152 {
153 .start = PNX833X_I2C1_PORTS_START,
154 .end = PNX833X_I2C1_PORTS_END,
155 .flags = IORESOURCE_MEM,
156 },
157 {
158 .start = PNX833X_PIC_I2C1_INT,
159 .end = PNX833X_PIC_I2C1_INT,
160 .flags = IORESOURCE_IRQ,
161 },
162};
163
164static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = {
165 {
166 .base = PNX833X_I2C0_PORTS_START,
167 .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */
168 .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */
169 .bus_addr = 0, /* no slave support */
170 },
171 {
172 .base = PNX833X_I2C1_PORTS_START,
173 .irq = -1, /* on high freq, polling is faster */
174 /*.irq = PNX833X_PIC_I2C1_INT,*/
175 .clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */
176 .bus_addr = 0, /* no slave support */
177 },
178};
179
180static struct platform_device pnx833x_i2c0_device = {
181 .name = "i2c-pnx0105",
182 .id = 0,
183 .dev = {
184 .platform_data = &pnx833x_i2c_dev[0],
185 },
186 .num_resources = ARRAY_SIZE(pnx833x_i2c0_resources),
187 .resource = pnx833x_i2c0_resources,
188};
189
190static struct platform_device pnx833x_i2c1_device = {
191 .name = "i2c-pnx0105",
192 .id = 1,
193 .dev = {
194 .platform_data = &pnx833x_i2c_dev[1],
195 },
196 .num_resources = ARRAY_SIZE(pnx833x_i2c1_resources),
197 .resource = pnx833x_i2c1_resources,
198};
199#endif
200
201static u64 ethernet_dmamask = DMA_32BIT_MASK;
202
203static struct resource pnx833x_ethernet_resources[] = {
204 [0] = {
205 .start = PNX8335_IP3902_PORTS_START,
206 .end = PNX8335_IP3902_PORTS_END,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = PNX8335_PIC_ETHERNET_INT,
211 .end = PNX8335_PIC_ETHERNET_INT,
212 .flags = IORESOURCE_IRQ,
213 },
214};
215
216static struct platform_device pnx833x_ethernet_device = {
217 .name = "ip3902-eth",
218 .id = -1,
219 .dev = {
220 .dma_mask = &ethernet_dmamask,
221 .coherent_dma_mask = DMA_32BIT_MASK,
222 },
223 .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
224 .resource = pnx833x_ethernet_resources,
225};
226
227static struct resource pnx833x_sata_resources[] = {
228 [0] = {
229 .start = PNX8335_SATA_PORTS_START,
230 .end = PNX8335_SATA_PORTS_END,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = PNX8335_PIC_SATA_INT,
235 .end = PNX8335_PIC_SATA_INT,
236 .flags = IORESOURCE_IRQ,
237 },
238};
239
240static struct platform_device pnx833x_sata_device = {
241 .name = "pnx833x-sata",
242 .id = -1,
243 .num_resources = ARRAY_SIZE(pnx833x_sata_resources),
244 .resource = pnx833x_sata_resources,
245};
246
247static const char *part_probes[] = {
248 "cmdlinepart",
249 NULL
250};
251
252static void
253pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
254{
255 struct nand_chip *this = mtd->priv;
256 unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
257
258 if (cmd == NAND_CMD_NONE)
259 return;
260
261 if (ctrl & NAND_CLE)
262 writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK));
263 else
264 writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK));
265}
266
267static struct platform_nand_data pnx833x_flash_nand_data = {
268 .chip = {
269 .chip_delay = 25,
270 .part_probe_types = part_probes,
271 },
272 .ctrl = {
273 .cmd_ctrl = pnx833x_flash_nand_cmd_ctrl
274 }
275};
276
277/*
278 * Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!),
279 * 12 bytes more seems to be the standard that allows for NAND access.
280 */
281static struct resource pnx833x_flash_nand_resource = {
282 .start = PNX8335_NAND_BASE,
283 .end = PNX8335_NAND_BASE + 12,
284 .flags = IORESOURCE_MEM,
285};
286
287static struct platform_device pnx833x_flash_nand = {
288 .name = "gen_nand",
289 .id = -1,
290 .num_resources = 1,
291 .resource = &pnx833x_flash_nand_resource,
292 .dev = {
293 .platform_data = &pnx833x_flash_nand_data,
294 },
295};
296
297static struct platform_device *pnx833x_platform_devices[] __initdata = {
298 &pnx833x_uart_device,
299 &pnx833x_usb_ehci_device,
300#ifdef CONFIG_I2C_PNX0105
301 &pnx833x_i2c0_device,
302 &pnx833x_i2c1_device,
303#endif
304 &pnx833x_ethernet_device,
305 &pnx833x_sata_device,
306 &pnx833x_flash_nand,
307};
308
309static int __init pnx833x_platform_init(void)
310{
311 int res;
312
313 res = platform_add_devices(pnx833x_platform_devices,
314 ARRAY_SIZE(pnx833x_platform_devices));
315
316 return res;
317}
318
319arch_initcall(pnx833x_platform_init);
diff --git a/arch/mips/nxp/pnx833x/common/prom.c b/arch/mips/nxp/pnx833x/common/prom.c
new file mode 100644
index 000000000000..2a41e8fec210
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/prom.c
@@ -0,0 +1,70 @@
1/*
2 * prom.c:
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * Based on software written by:
9 * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/init.h>
26#include <asm/bootinfo.h>
27#include <linux/string.h>
28
29void __init prom_init_cmdline(void)
30{
31 int argc = fw_arg0;
32 char **argv = (char **)fw_arg1;
33 char *c = &(arcs_cmdline[0]);
34 int i;
35
36 for (i = 1; i < argc; i++) {
37 strcpy(c, argv[i]);
38 c += strlen(argv[i]);
39 if (i < argc-1)
40 *c++ = ' ';
41 }
42 *c = 0;
43}
44
45char __init *prom_getenv(char *envname)
46{
47 extern char **prom_envp;
48 char **env = prom_envp;
49 int i;
50
51 i = strlen(envname);
52
53 while (*env) {
54 if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
55 return *env + i + 1;
56 env++;
57 }
58
59 return 0;
60}
61
62void __init prom_free_prom_memory(void)
63{
64}
65
66char * __init prom_getcmdline(void)
67{
68 return arcs_cmdline;
69}
70
diff --git a/arch/mips/nxp/pnx833x/common/reset.c b/arch/mips/nxp/pnx833x/common/reset.c
new file mode 100644
index 000000000000..a9bc9bacad2b
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/reset.c
@@ -0,0 +1,45 @@
1/*
2 * reset.c: reset support for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * Based on software written by:
9 * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/slab.h>
26#include <linux/reboot.h>
27#include <pnx833x.h>
28
29void pnx833x_machine_restart(char *command)
30{
31 PNX833X_RESET_CONTROL_2 = 0;
32 PNX833X_RESET_CONTROL = 0;
33}
34
35void pnx833x_machine_halt(void)
36{
37 while (1)
38 __asm__ __volatile__ ("wait");
39
40}
41
42void pnx833x_machine_power_off(void)
43{
44 pnx833x_machine_halt();
45}
diff --git a/arch/mips/nxp/pnx833x/common/setup.c b/arch/mips/nxp/pnx833x/common/setup.c
new file mode 100644
index 000000000000..e51fbc4b644d
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/common/setup.c
@@ -0,0 +1,64 @@
1/*
2 * setup.c: Setup PNX833X Soc.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * Based on software written by:
9 * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/ioport.h>
28#include <linux/io.h>
29#include <linux/pci.h>
30#include <asm/reboot.h>
31#include <pnx833x.h>
32#include <gpio.h>
33
34extern void pnx833x_board_setup(void);
35extern void pnx833x_machine_restart(char *);
36extern void pnx833x_machine_halt(void);
37extern void pnx833x_machine_power_off(void);
38
39int __init plat_mem_setup(void)
40{
41 /* fake pci bus to avoid bounce buffers */
42 PCI_DMA_BUS_IS_PHYS = 1;
43
44 /* set mips clock to 320MHz */
45#if defined(CONFIG_SOC_PNX8335)
46 PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ);
47#endif
48 pnx833x_gpio_init(); /* so it will be ready in board_setup() */
49
50 pnx833x_board_setup();
51
52 _machine_restart = pnx833x_machine_restart;
53 _machine_halt = pnx833x_machine_halt;
54 pm_power_off = pnx833x_machine_power_off;
55
56 /* IO/MEM resources. */
57 set_io_port_base(KSEG1);
58 ioport_resource.start = 0;
59 ioport_resource.end = ~0;
60 iomem_resource.start = 0;
61 iomem_resource.end = ~0;
62
63 return 0;
64}
diff --git a/arch/mips/nxp/pnx833x/stb22x/Makefile b/arch/mips/nxp/pnx833x/stb22x/Makefile
new file mode 100644
index 000000000000..f81c5801f455
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/stb22x/Makefile
@@ -0,0 +1,3 @@
1lib-y := board.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx833x/stb22x/board.c b/arch/mips/nxp/pnx833x/stb22x/board.c
new file mode 100644
index 000000000000..90cc604bdadf
--- /dev/null
+++ b/arch/mips/nxp/pnx833x/stb22x/board.c
@@ -0,0 +1,133 @@
1/*
2 * board.c: STB225 board support.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * Based on software written by:
9 * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/init.h>
26#include <asm/bootinfo.h>
27#include <linux/mm.h>
28#include <pnx833x.h>
29#include <gpio.h>
30
31/* endianess twiddlers */
32#define PNX8335_DEBUG0 0x4400
33#define PNX8335_DEBUG1 0x4404
34#define PNX8335_DEBUG2 0x4408
35#define PNX8335_DEBUG3 0x440c
36#define PNX8335_DEBUG4 0x4410
37#define PNX8335_DEBUG5 0x4414
38#define PNX8335_DEBUG6 0x4418
39#define PNX8335_DEBUG7 0x441c
40
41int prom_argc;
42char **prom_argv = 0, **prom_envp = 0;
43
44extern void prom_init_cmdline(void);
45extern char *prom_getenv(char *envname);
46
47const char *get_system_type(void)
48{
49 return "NXP STB22x";
50}
51
52static inline unsigned long env_or_default(char *env, unsigned long dfl)
53{
54 char *str = prom_getenv(env);
55 return str ? simple_strtol(str, 0, 0) : dfl;
56}
57
58void __init prom_init(void)
59{
60 unsigned long memsize;
61
62 prom_argc = fw_arg0;
63 prom_argv = (char **)fw_arg1;
64 prom_envp = (char **)fw_arg2;
65
66 prom_init_cmdline();
67
68 memsize = env_or_default("memsize", 0x02000000);
69 add_memory_region(0, memsize, BOOT_MEM_RAM);
70}
71
72void __init pnx833x_board_setup(void)
73{
74 pnx833x_gpio_select_function_alt(4);
75 pnx833x_gpio_select_output(4);
76 pnx833x_gpio_select_function_alt(5);
77 pnx833x_gpio_select_input(5);
78 pnx833x_gpio_select_function_alt(6);
79 pnx833x_gpio_select_input(6);
80 pnx833x_gpio_select_function_alt(7);
81 pnx833x_gpio_select_output(7);
82
83 pnx833x_gpio_select_function_alt(25);
84 pnx833x_gpio_select_function_alt(26);
85
86 pnx833x_gpio_select_function_alt(27);
87 pnx833x_gpio_select_function_alt(28);
88 pnx833x_gpio_select_function_alt(29);
89 pnx833x_gpio_select_function_alt(30);
90 pnx833x_gpio_select_function_alt(31);
91 pnx833x_gpio_select_function_alt(32);
92 pnx833x_gpio_select_function_alt(33);
93
94#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
95 /* Setup MIU for NAND access on CS0...
96 *
97 * (it seems that we must also configure CS1 for reliable operation,
98 * otherwise the first read ID command will fail if it's read as 4 bytes
99 * but pass if it's read as 1 word.)
100 */
101
102 /* Setup MIU CS0 & CS1 timing */
103 PNX833X_MIU_SEL0 = 0;
104 PNX833X_MIU_SEL1 = 0;
105 PNX833X_MIU_SEL0_TIMING = 0x50003081;
106 PNX833X_MIU_SEL1_TIMING = 0x50003081;
107
108 /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
109 pnx833x_gpio_select_function_alt(0);
110
111 /* Setup GPIO 04 to input NAND read/busy signal */
112 pnx833x_gpio_select_function_io(4);
113 pnx833x_gpio_select_input(4);
114
115 /* Setup GPIO 05 to disable NAND write protect */
116 pnx833x_gpio_select_function_io(5);
117 pnx833x_gpio_select_output(5);
118 pnx833x_gpio_write(1, 5);
119
120#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE)
121
122 /* Set up MIU for 16-bit NOR access on CS0 and CS1... */
123
124 /* Setup MIU CS0 & CS1 timing */
125 PNX833X_MIU_SEL0 = 1;
126 PNX833X_MIU_SEL1 = 1;
127 PNX833X_MIU_SEL0_TIMING = 0x6A08D082;
128 PNX833X_MIU_SEL1_TIMING = 0x6A08D082;
129
130 /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
131 pnx833x_gpio_select_function_alt(0);
132#endif
133}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index b1886244cedf..e8a97f59e066 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_MIPS_MSC) += ops-msc.o
13obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o 13obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
14obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o 14obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o
15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
16obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o 16obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
17obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o 17obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o 18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
19 19
diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
index 846eae9cdd05..fba5aad00d51 100644
--- a/arch/mips/pci/fixup-emma2rh.c
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -30,7 +30,7 @@
30 30
31#include <asm/bootinfo.h> 31#include <asm/bootinfo.h>
32 32
33#include <asm/emma2rh/emma2rh.h> 33#include <asm/emma/emma2rh.h>
34 34
35#define EMMA2RH_PCI_HOST_SLOT 0x09 35#define EMMA2RH_PCI_HOST_SLOT 0x09
36#define EMMA2RH_USB_SLOT 0x03 36#define EMMA2RH_USB_SLOT 0x03
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index 75b90dcb7a09..3d86823d03a0 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -30,6 +30,7 @@
30#include <linux/init.h> 30#include <linux/init.h>
31 31
32#include <asm/mach-rc32434/rc32434.h> 32#include <asm/mach-rc32434/rc32434.h>
33#include <asm/mach-rc32434/irq.h>
33 34
34static int __devinitdata irq_map[2][12] = { 35static int __devinitdata irq_map[2][12] = {
35 {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1}, 36 {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c
index d31bfc6d4150..5947a70b0b7f 100644
--- a/arch/mips/pci/ops-emma2rh.c
+++ b/arch/mips/pci/ops-emma2rh.c
@@ -30,7 +30,7 @@
30#include <asm/addrspace.h> 30#include <asm/addrspace.h>
31#include <asm/debug.h> 31#include <asm/debug.h>
32 32
33#include <asm/emma2rh/emma2rh.h> 33#include <asm/emma/emma2rh.h>
34 34
35#define RTABORT (0x1<<9) 35#define RTABORT (0x1<<9)
36#define RMABORT (0x1<<10) 36#define RMABORT (0x1<<10)
diff --git a/arch/mips/pci/pci-emma2rh.c b/arch/mips/pci/pci-emma2rh.c
index 772e283daa63..2df4190232cd 100644
--- a/arch/mips/pci/pci-emma2rh.c
+++ b/arch/mips/pci/pci-emma2rh.c
@@ -30,7 +30,7 @@
30 30
31#include <asm/bootinfo.h> 31#include <asm/bootinfo.h>
32 32
33#include <asm/emma2rh/emma2rh.h> 33#include <asm/emma/emma2rh.h>
34 34
35static struct resource pci_io_resource = { 35static struct resource pci_io_resource = {
36 .name = "pci IO space", 36 .name = "pci IO space",
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 31619c601b11..2f22d714d5b0 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -280,7 +280,7 @@ static int __init plat_setup_devices(void)
280{ 280{
281 /* Look for the CF card reader */ 281 /* Look for the CF card reader */
282 if (!readl(IDT434_REG_BASE + DEV1MASK)) 282 if (!readl(IDT434_REG_BASE + DEV1MASK))
283 rb532_devs[1] = NULL; 283 rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
284 else { 284 else {
285 cf_slot0_res[0].start = 285 cf_slot0_res[0].start =
286 readl(IDT434_REG_BASE + DEV1BASE); 286 readl(IDT434_REG_BASE + DEV1BASE);
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 76a7fd96d564..70c4a6726377 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -310,6 +310,10 @@ int __init rb532_gpio_init(void)
310 return -ENXIO; 310 return -ENXIO;
311 } 311 }
312 312
313 /* Set the interrupt status and level for the CF pin */
314 rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1);
315 rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0);
316
313 return 0; 317 return 0;
314} 318}
315arch_initcall(rb532_gpio_init); 319arch_initcall(rb532_gpio_init);
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index f6d9bf4b26e7..f8b18af141a1 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -12,20 +12,11 @@
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel_stat.h> 14#include <linux/kernel_stat.h>
15#include <linux/signal.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h> 15#include <linux/interrupt.h>
18#include <linux/irq.h>
19 16
20#include <asm/mipsregs.h>
21#include <asm/addrspace.h>
22#include <asm/irq_cpu.h> 17#include <asm/irq_cpu.h>
23#include <asm/sgi/ioc.h>
24#include <asm/sgi/hpc3.h> 18#include <asm/sgi/hpc3.h>
25#include <asm/sgi/ip22.h> 19#include <asm/sgi/ip22.h>
26#include <asm/time.h>
27
28/* #define DEBUG_SGINT */
29 20
30/* So far nothing hangs here */ 21/* So far nothing hangs here */
31#undef USE_LIO3_IRQ 22#undef USE_LIO3_IRQ
@@ -68,7 +59,7 @@ static void enable_local1_irq(unsigned int irq)
68 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); 59 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
69} 60}
70 61
71void disable_local1_irq(unsigned int irq) 62static void disable_local1_irq(unsigned int irq)
72{ 63{
73 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); 64 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
74} 65}
@@ -87,7 +78,7 @@ static void enable_local2_irq(unsigned int irq)
87 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); 78 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
88} 79}
89 80
90void disable_local2_irq(unsigned int irq) 81static void disable_local2_irq(unsigned int irq)
91{ 82{
92 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); 83 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
93 if (!sgint->cmeimask0) 84 if (!sgint->cmeimask0)
@@ -108,7 +99,7 @@ static void enable_local3_irq(unsigned int irq)
108 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); 99 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
109} 100}
110 101
111void disable_local3_irq(unsigned int irq) 102static void disable_local3_irq(unsigned int irq)
112{ 103{
113 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); 104 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
114 if (!sgint->cmeimask1) 105 if (!sgint->cmeimask1)
@@ -344,6 +335,6 @@ void __init arch_init_irq(void)
344 335
345#ifdef CONFIG_EISA 336#ifdef CONFIG_EISA
346 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */ 337 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
347 ip22_eisa_init(); 338 ip22_eisa_init();
348#endif 339#endif
349} 340}
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 17052db4161d..226e8bb2f0a1 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -46,9 +46,10 @@ config TOSHIBA_RBTX4938
46 support this machine type 46 support this machine type
47 47
48config TOSHIBA_RBTX4939 48config TOSHIBA_RBTX4939
49 bool "Toshiba RBTX4939 bobard" 49 bool "Toshiba RBTX4939 board"
50 depends on MACH_TX49XX 50 depends on MACH_TX49XX
51 select SOC_TX4939 51 select SOC_TX4939
52 select TXX9_7SEGLED
52 help 53 help
53 This Toshiba board is based on the TX4939 processor. Say Y here to 54 This Toshiba board is based on the TX4939 processor. Say Y here to
54 support this machine type 55 support this machine type
@@ -86,6 +87,9 @@ config SOC_TX4939
86 select HW_HAS_PCI 87 select HW_HAS_PCI
87 select PCI_TX4927 88 select PCI_TX4927
88 89
90config TXX9_7SEGLED
91 bool
92
89config TOSHIBA_FPCIB0 93config TOSHIBA_FPCIB0
90 bool "FPCIB0 Backplane Support" 94 bool "FPCIB0 Backplane Support"
91 depends on PCI && MACH_TXX9 95 depends on PCI && MACH_TXX9
diff --git a/arch/mips/txx9/generic/7segled.c b/arch/mips/txx9/generic/7segled.c
new file mode 100644
index 000000000000..727ab21b6618
--- /dev/null
+++ b/arch/mips/txx9/generic/7segled.c
@@ -0,0 +1,112 @@
1/*
2 * 7 Segment LED routines
3 * Based on RBTX49xx patch from CELF patch archive.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * (C) Copyright TOSHIBA CORPORATION 2005-2007
10 * All Rights Reserved.
11 */
12#include <linux/sysdev.h>
13#include <linux/slab.h>
14#include <linux/map_to_7segment.h>
15#include <asm/txx9/generic.h>
16
17static unsigned int tx_7segled_num;
18static void (*tx_7segled_putc)(unsigned int pos, unsigned char val);
19
20void __init txx9_7segled_init(unsigned int num,
21 void (*putc)(unsigned int pos, unsigned char val))
22{
23 tx_7segled_num = num;
24 tx_7segled_putc = putc;
25}
26
27static SEG7_CONVERSION_MAP(txx9_seg7map, MAP_ASCII7SEG_ALPHANUM_LC);
28
29int txx9_7segled_putc(unsigned int pos, char c)
30{
31 if (pos >= tx_7segled_num)
32 return -EINVAL;
33 c = map_to_seg7(&txx9_seg7map, c);
34 if (c < 0)
35 return c;
36 tx_7segled_putc(pos, c);
37 return 0;
38}
39
40static ssize_t ascii_store(struct sys_device *dev,
41 struct sysdev_attribute *attr,
42 const char *buf, size_t size)
43{
44 unsigned int ch = dev->id;
45 txx9_7segled_putc(ch, buf[0]);
46 return size;
47}
48
49static ssize_t raw_store(struct sys_device *dev,
50 struct sysdev_attribute *attr,
51 const char *buf, size_t size)
52{
53 unsigned int ch = dev->id;
54 tx_7segled_putc(ch, buf[0]);
55 return size;
56}
57
58static SYSDEV_ATTR(ascii, 0200, NULL, ascii_store);
59static SYSDEV_ATTR(raw, 0200, NULL, raw_store);
60
61static ssize_t map_seg7_show(struct sysdev_class *class, char *buf)
62{
63 memcpy(buf, &txx9_seg7map, sizeof(txx9_seg7map));
64 return sizeof(txx9_seg7map);
65}
66
67static ssize_t map_seg7_store(struct sysdev_class *class,
68 const char *buf, size_t size)
69{
70 if (size != sizeof(txx9_seg7map))
71 return -EINVAL;
72 memcpy(&txx9_seg7map, buf, size);
73 return size;
74}
75
76static SYSDEV_CLASS_ATTR(map_seg7, 0600, map_seg7_show, map_seg7_store);
77
78static struct sysdev_class tx_7segled_sysdev_class = {
79 .name = "7segled",
80};
81
82static int __init tx_7segled_init_sysfs(void)
83{
84 int error, i;
85 if (!tx_7segled_num)
86 return -ENODEV;
87 error = sysdev_class_register(&tx_7segled_sysdev_class);
88 if (error)
89 return error;
90 error = sysdev_class_create_file(&tx_7segled_sysdev_class,
91 &attr_map_seg7);
92 if (error)
93 return error;
94 for (i = 0; i < tx_7segled_num; i++) {
95 struct sys_device *dev;
96 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
97 if (!dev) {
98 error = -ENODEV;
99 break;
100 }
101 dev->id = i;
102 dev->cls = &tx_7segled_sysdev_class;
103 error = sysdev_register(dev);
104 if (!error) {
105 sysdev_create_file(dev, &attr_ascii);
106 sysdev_create_file(dev, &attr_raw);
107 }
108 }
109 return error;
110}
111
112device_initcall(tx_7segled_init_sysfs);
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 0030d23bef5b..f2579ce054a1 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
10obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o 10obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
12obj-$(CONFIG_SPI) += spi_eeprom.o 12obj-$(CONFIG_SPI) += spi_eeprom.o
13obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o
13 14
14EXTRA_CFLAGS += -Werror 15EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 5526375010f8..a13a08b8c9ec 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -156,11 +156,23 @@ static struct txx9_board_vec *__init find_board_byname(const char *name)
156 156
157static void __init prom_init_cmdline(void) 157static void __init prom_init_cmdline(void)
158{ 158{
159 int argc = (int)fw_arg0; 159 int argc;
160 int *argv32 = (int *)fw_arg1; 160 int *argv32;
161 int i; /* Always ignore the "-c" at argv[0] */ 161 int i; /* Always ignore the "-c" at argv[0] */
162 char builtin[CL_SIZE]; 162 char builtin[CL_SIZE];
163 163
164 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
165 /*
166 * argc is not a valid number, or argv32 is not a valid
167 * pointer
168 */
169 argc = 0;
170 argv32 = NULL;
171 } else {
172 argc = (int)fw_arg0;
173 argv32 = (int *)fw_arg1;
174 }
175
164 /* ignore all built-in args if any f/w args given */ 176 /* ignore all built-in args if any f/w args given */
165 /* 177 /*
166 * But if built-in strings was started with '+', append them 178 * But if built-in strings was started with '+', append them
@@ -414,10 +426,12 @@ char * __init prom_getcmdline(void)
414 426
415const char *__init prom_getenv(const char *name) 427const char *__init prom_getenv(const char *name)
416{ 428{
417 const s32 *str = (const s32 *)fw_arg2; 429 const s32 *str;
418 430
419 if (!str) 431 if (fw_arg2 < CKSEG0)
420 return NULL; 432 return NULL;
433
434 str = (const s32 *)fw_arg2;
421 /* YAMON style ("name", "value" pairs) */ 435 /* YAMON style ("name", "value" pairs) */
422 while (str[0] && str[1]) { 436 while (str[0] && str[1]) {
423 if (!strcmp((const char *)(unsigned long)str[0], name)) 437 if (!strcmp((const char *)(unsigned long)str[0], name))
@@ -622,6 +636,21 @@ unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
622EXPORT_SYMBOL(__swizzle_addr_b); 636EXPORT_SYMBOL(__swizzle_addr_b);
623#endif 637#endif
624 638
639#ifdef NEEDS_TXX9_IOSWABW
640static u16 ioswabw_default(volatile u16 *a, u16 x)
641{
642 return le16_to_cpu(x);
643}
644static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
645{
646 return x;
647}
648u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
649EXPORT_SYMBOL(ioswabw);
650u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
651EXPORT_SYMBOL(__mem_ioswabw);
652#endif
653
625void __init txx9_physmap_flash_init(int no, unsigned long addr, 654void __init txx9_physmap_flash_init(int no, unsigned long addr,
626 unsigned long size, 655 unsigned long size,
627 const struct physmap_flash_data *pdata) 656 const struct physmap_flash_data *pdata)
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 4a74423b2ba8..01129a9d50fa 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -49,6 +49,7 @@
49#include <linux/platform_device.h> 49#include <linux/platform_device.h>
50#include <linux/delay.h> 50#include <linux/delay.h>
51#include <linux/gpio.h> 51#include <linux/gpio.h>
52#include <linux/leds.h>
52#include <asm/io.h> 53#include <asm/io.h>
53#include <asm/reboot.h> 54#include <asm/reboot.h>
54#include <asm/txx9/generic.h> 55#include <asm/txx9/generic.h>
@@ -210,10 +211,6 @@ static void __init rbtx4927_mem_setup(void)
210 /* TX4927-SIO DTR on (PIO[15]) */ 211 /* TX4927-SIO DTR on (PIO[15]) */
211 gpio_request(15, "sio-dtr"); 212 gpio_request(15, "sio-dtr");
212 gpio_direction_output(15, 1); 213 gpio_direction_output(15, 1);
213 gpio_request(0, "led");
214 gpio_direction_output(0, 1);
215 gpio_request(1, "led");
216 gpio_direction_output(1, 1);
217 214
218 tx4927_sio_init(0, 0); 215 tx4927_sio_init(0, 0);
219#ifdef CONFIG_SERIAL_TXX9_CONSOLE 216#ifdef CONFIG_SERIAL_TXX9_CONSOLE
@@ -315,6 +312,25 @@ static void __init rbtx4927_mtd_init(void)
315 tx4927_mtd_init(i); 312 tx4927_mtd_init(i);
316} 313}
317 314
315static void __init rbtx4927_gpioled_init(void)
316{
317 static struct gpio_led leds[] = {
318 { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
319 { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
320 };
321 static struct gpio_led_platform_data pdata = {
322 .num_leds = ARRAY_SIZE(leds),
323 .leds = leds,
324 };
325 struct platform_device *pdev = platform_device_alloc("leds-gpio", 0);
326
327 if (!pdev)
328 return;
329 pdev->dev.platform_data = &pdata;
330 if (platform_device_add(pdev))
331 platform_device_put(pdev);
332}
333
318static void __init rbtx4927_device_init(void) 334static void __init rbtx4927_device_init(void)
319{ 335{
320 toshiba_rbtx4927_rtc_init(); 336 toshiba_rbtx4927_rtc_init();
@@ -322,6 +338,7 @@ static void __init rbtx4927_device_init(void)
322 tx4927_wdt_init(); 338 tx4927_wdt_init();
323 rbtx4927_mtd_init(); 339 rbtx4927_mtd_init();
324 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); 340 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
341 rbtx4927_gpioled_init();
325} 342}
326 343
327struct txx9_board_vec rbtx4927_vec __initdata = { 344struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 9855d7bccc20..98fbd9391bf8 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -14,6 +14,8 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/leds.h> 16#include <linux/leds.h>
17#include <linux/interrupt.h>
18#include <linux/smc91x.h>
17#include <asm/reboot.h> 19#include <asm/reboot.h>
18#include <asm/txx9/generic.h> 20#include <asm/txx9/generic.h>
19#include <asm/txx9/pci.h> 21#include <asm/txx9/pci.h>
@@ -33,6 +35,21 @@ static void __init rbtx4939_time_init(void)
33 tx4939_time_init(0); 35 tx4939_time_init(0);
34} 36}
35 37
38#if defined(__BIG_ENDIAN) && \
39 (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE))
40#define HAVE_RBTX4939_IOSWAB
41#define IS_CE1_ADDR(addr) \
42 ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
43static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
44{
45 return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
46}
47static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
48{
49 return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
50}
51#endif /* __BIG_ENDIAN && CONFIG_SMC91X */
52
36static void __init rbtx4939_pci_setup(void) 53static void __init rbtx4939_pci_setup(void)
37{ 54{
38#ifdef CONFIG_PCI 55#ifdef CONFIG_PCI
@@ -239,6 +256,32 @@ static inline void rbtx4939_led_setup(void)
239} 256}
240#endif 257#endif
241 258
259static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
260{
261#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
262 unsigned long flags;
263 local_irq_save(flags);
264 /* bit7: reserved for LED class */
265 led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f);
266 val = led_val[pos];
267 local_irq_restore(flags);
268#endif
269 writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
270}
271
272static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
273{
274 /* convert from map_to_seg7() notation */
275 val = (val & 0x88) |
276 ((val & 0x40) >> 6) |
277 ((val & 0x20) >> 4) |
278 ((val & 0x10) >> 2) |
279 ((val & 0x04) << 2) |
280 ((val & 0x02) << 4) |
281 ((val & 0x01) << 6);
282 __rbtx4939_7segled_putc(pos, val);
283}
284
242static void __init rbtx4939_arch_init(void) 285static void __init rbtx4939_arch_init(void)
243{ 286{
244 rbtx4939_pci_setup(); 287 rbtx4939_pci_setup();
@@ -246,22 +289,50 @@ static void __init rbtx4939_arch_init(void)
246 289
247static void __init rbtx4939_device_init(void) 290static void __init rbtx4939_device_init(void)
248{ 291{
292 unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
293 struct resource smc_res[] = {
294 {
295 .start = smc_addr,
296 .end = smc_addr + 0x10 - 1,
297 .flags = IORESOURCE_MEM,
298 }, {
299 .start = RBTX4939_IRQ_ETHER,
300 /* override default irq flag defined in smc91x.h */
301 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
302 },
303 };
304 struct smc91x_platdata smc_pdata = {
305 .flags = SMC91X_USE_16BIT,
306 };
307 struct platform_device *pdev;
249#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) 308#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
250 int i, j; 309 int i, j;
251 unsigned char ethaddr[2][6]; 310 unsigned char ethaddr[2][6];
311 u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
312
252 for (i = 0; i < 2; i++) { 313 for (i = 0; i < 2; i++) {
253 unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10); 314 unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
254 if (readb(rbtx4939_bdipsw_addr) & 8) { 315 if (bdipsw == 0)
316 memcpy(ethaddr[i], (void *)area, 6);
317 else {
255 u16 buf[3]; 318 u16 buf[3];
256 area -= 0x03000000; 319 if (bdipsw & 8)
320 area -= 0x03000000;
321 else
322 area -= 0x01000000;
257 for (j = 0; j < 3; j++) 323 for (j = 0; j < 3; j++)
258 buf[j] = le16_to_cpup((u16 *)(area + j * 2)); 324 buf[j] = le16_to_cpup((u16 *)(area + j * 2));
259 memcpy(ethaddr[i], buf, 6); 325 memcpy(ethaddr[i], buf, 6);
260 } else 326 }
261 memcpy(ethaddr[i], (void *)area, 6);
262 } 327 }
263 tx4939_ethaddr_init(ethaddr[0], ethaddr[1]); 328 tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
264#endif 329#endif
330 pdev = platform_device_alloc("smc91x", -1);
331 if (!pdev ||
332 platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) ||
333 platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
334 platform_device_add(pdev))
335 platform_device_put(pdev);
265 rbtx4939_led_setup(); 336 rbtx4939_led_setup();
266 tx4939_wdt_init(); 337 tx4939_wdt_init();
267 tx4939_ata_init(); 338 tx4939_ata_init();
@@ -269,6 +340,8 @@ static void __init rbtx4939_device_init(void)
269 340
270static void __init rbtx4939_setup(void) 341static void __init rbtx4939_setup(void)
271{ 342{
343 int i;
344
272 rbtx4939_ebusc_setup(); 345 rbtx4939_ebusc_setup();
273 /* always enable ATA0 */ 346 /* always enable ATA0 */
274 txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE); 347 txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
@@ -276,9 +349,16 @@ static void __init rbtx4939_setup(void)
276 if (txx9_master_clock == 0) 349 if (txx9_master_clock == 0)
277 txx9_master_clock = 20000000; 350 txx9_master_clock = 20000000;
278 tx4939_setup(); 351 tx4939_setup();
352#ifdef HAVE_RBTX4939_IOSWAB
353 ioswabw = rbtx4939_ioswabw;
354 __mem_ioswabw = rbtx4939_mem_ioswabw;
355#endif
279 356
280 _machine_restart = rbtx4939_machine_restart; 357 _machine_restart = rbtx4939_machine_restart;
281 358
359 txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
360 for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
361 txx9_7segled_putc(i, '-');
282 pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", 362 pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
283 readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr), 363 readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
284 readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr)); 364 readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 18:52:45 -0500