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-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h4
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h12
2 files changed, 14 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
index 358cf28ce2af..a5bbff31c898 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
@@ -11,6 +11,7 @@ struct bcm_enet_desc {
11 u32 address; 11 u32 address;
12}; 12};
13 13
14/* control */
14#define DMADESC_LENGTH_SHIFT 16 15#define DMADESC_LENGTH_SHIFT 16
15#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) 16#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT)
16#define DMADESC_OWNER_MASK (1 << 15) 17#define DMADESC_OWNER_MASK (1 << 15)
@@ -18,7 +19,10 @@ struct bcm_enet_desc {
18#define DMADESC_SOP_MASK (1 << 13) 19#define DMADESC_SOP_MASK (1 << 13)
19#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) 20#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
20#define DMADESC_WRAP_MASK (1 << 12) 21#define DMADESC_WRAP_MASK (1 << 12)
22#define DMADESC_USB_NOZERO_MASK (1 << 1)
23#define DMADESC_USB_ZERO_MASK (1 << 0)
21 24
25/* status */
22#define DMADESC_UNDER_MASK (1 << 9) 26#define DMADESC_UNDER_MASK (1 << 9)
23#define DMADESC_APPEND_CRC (1 << 8) 27#define DMADESC_APPEND_CRC (1 << 8)
24#define DMADESC_OVSIZE_MASK (1 << 4) 28#define DMADESC_OVSIZE_MASK (1 << 4)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 4ccc2a748aff..7a101125e482 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -670,6 +670,12 @@
670#define ENETDMA_BUFALLOC_FORCE_SHIFT 31 670#define ENETDMA_BUFALLOC_FORCE_SHIFT 31
671#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) 671#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
672 672
673/* Global interrupt status */
674#define ENETDMA_GLB_IRQSTAT_REG (0x40)
675
676/* Global interrupt mask */
677#define ENETDMA_GLB_IRQMASK_REG (0x44)
678
673/* Channel Configuration register */ 679/* Channel Configuration register */
674#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) 680#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
675#define ENETDMA_CHANCFG_EN_SHIFT 0 681#define ENETDMA_CHANCFG_EN_SHIFT 0
@@ -709,9 +715,11 @@
709/* Channel Configuration register */ 715/* Channel Configuration register */
710#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) 716#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
711#define ENETDMAC_CHANCFG_EN_SHIFT 0 717#define ENETDMAC_CHANCFG_EN_SHIFT 0
712#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) 718#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
713#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 719#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
714#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) 720#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
721#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
722#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
715 723
716/* Interrupt Control/Status register */ 724/* Interrupt Control/Status register */
717#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) 725#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)