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-rw-r--r--arch/mips/Kconfig9
-rw-r--r--arch/mips/dec/ecc-berr.c1
-rw-r--r--arch/mips/dec/ioasic-irq.c4
-rw-r--r--arch/mips/dec/kn01-berr.c2
-rw-r--r--arch/mips/dec/kn02-irq.c7
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c7
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c7
-rw-r--r--arch/mips/jazz/irq.c7
-rw-r--r--arch/mips/kernel/i8259.c162
-rw-r--r--arch/mips/kernel/irq-mv6434x.c10
-rw-r--r--arch/mips/kernel/irq-rm7000.c7
-rw-r--r--arch/mips/kernel/irq-rm9000.c8
-rw-r--r--arch/mips/kernel/irq.c2
-rw-r--r--arch/mips/kernel/irq_cpu.c10
-rw-r--r--arch/mips/lasat/interrupt.c7
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c10
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c10
-rw-r--r--arch/mips/philips/pnx8550/common/int.c8
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c28
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c8
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c5
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c26
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c21
-rw-r--r--arch/mips/tx4938/common/irq.c20
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c10
-rw-r--r--arch/mips/vr41xx/Kconfig5
-rw-r--r--arch/mips/vr41xx/common/icu.c14
27 files changed, 105 insertions, 310 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4d64960be035..d8af858fe3f5 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -242,6 +242,7 @@ config LASAT
242 select SYS_SUPPORTS_32BIT_KERNEL 242 select SYS_SUPPORTS_32BIT_KERNEL
243 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 243 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
244 select SYS_SUPPORTS_LITTLE_ENDIAN 244 select SYS_SUPPORTS_LITTLE_ENDIAN
245 select GENERIC_HARDIRQS_NO__DO_IRQ
245 246
246config MIPS_ATLAS 247config MIPS_ATLAS
247 bool "MIPS Atlas board" 248 bool "MIPS Atlas board"
@@ -265,6 +266,7 @@ config MIPS_ATLAS
265 select SYS_SUPPORTS_BIG_ENDIAN 266 select SYS_SUPPORTS_BIG_ENDIAN
266 select SYS_SUPPORTS_LITTLE_ENDIAN 267 select SYS_SUPPORTS_LITTLE_ENDIAN
267 select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL 268 select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
269 select GENERIC_HARDIRQS_NO__DO_IRQ
268 help 270 help
269 This enables support for the MIPS Technologies Atlas evaluation 271 This enables support for the MIPS Technologies Atlas evaluation
270 board. 272 board.
@@ -419,6 +421,7 @@ config MOMENCO_OCELOT_C
419 select SYS_SUPPORTS_32BIT_KERNEL 421 select SYS_SUPPORTS_32BIT_KERNEL
420 select SYS_SUPPORTS_64BIT_KERNEL 422 select SYS_SUPPORTS_64BIT_KERNEL
421 select SYS_SUPPORTS_BIG_ENDIAN 423 select SYS_SUPPORTS_BIG_ENDIAN
424 select GENERIC_HARDIRQS_NO__DO_IRQ
422 help 425 help
423 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 426 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
424 Momentum Computer <http://www.momenco.com/>. 427 Momentum Computer <http://www.momenco.com/>.
@@ -569,6 +572,7 @@ config SGI_IP27
569 select SYS_SUPPORTS_BIG_ENDIAN 572 select SYS_SUPPORTS_BIG_ENDIAN
570 select SYS_SUPPORTS_NUMA 573 select SYS_SUPPORTS_NUMA
571 select SYS_SUPPORTS_SMP 574 select SYS_SUPPORTS_SMP
575 select GENERIC_HARDIRQS_NO__DO_IRQ
572 help 576 help
573 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 577 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
574 workstations. To compile a Linux kernel that runs on these, say Y 578 workstations. To compile a Linux kernel that runs on these, say Y
@@ -835,6 +839,10 @@ config SCHED_NO_NO_OMIT_FRAME_POINTER
835 bool 839 bool
836 default y 840 default y
837 841
842config GENERIC_HARDIRQS_NO__DO_IRQ
843 bool
844 default n
845
838# 846#
839# Select some configuration options automatically based on user selections. 847# Select some configuration options automatically based on user selections.
840# 848#
@@ -996,6 +1004,7 @@ config SOC_PNX8550
996 select HW_HAS_PCI 1004 select HW_HAS_PCI
997 select SYS_HAS_CPU_MIPS32_R1 1005 select SYS_HAS_CPU_MIPS32_R1
998 select SYS_SUPPORTS_32BIT_KERNEL 1006 select SYS_SUPPORTS_32BIT_KERNEL
1007 select GENERIC_HARDIRQS_NO__DO_IRQ
999 1008
1000config SWAP_IO_SPACE 1009config SWAP_IO_SPACE
1001 bool 1010 bool
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index c8430c07355e..6d55e8aab668 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -25,6 +25,7 @@
25#include <asm/cpu.h> 25#include <asm/cpu.h>
26#include <asm/irq_regs.h> 26#include <asm/irq_regs.h>
27#include <asm/processor.h> 27#include <asm/processor.h>
28#include <asm/ptrace.h>
28#include <asm/system.h> 29#include <asm/system.h>
29#include <asm/traps.h> 30#include <asm/traps.h>
30 31
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 269b22b34313..4c7cb4048d35 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -67,7 +67,6 @@ static struct irq_chip ioasic_irq_type = {
67 .mask = mask_ioasic_irq, 67 .mask = mask_ioasic_irq,
68 .mask_ack = ack_ioasic_irq, 68 .mask_ack = ack_ioasic_irq,
69 .unmask = unmask_ioasic_irq, 69 .unmask = unmask_ioasic_irq,
70 .end = end_ioasic_irq,
71}; 70};
72 71
73 72
@@ -106,8 +105,7 @@ void __init init_ioasic_irqs(int base)
106 set_irq_chip_and_handler(i, &ioasic_irq_type, 105 set_irq_chip_and_handler(i, &ioasic_irq_type,
107 handle_level_irq); 106 handle_level_irq);
108 for (; i < base + IO_IRQ_LINES; i++) 107 for (; i < base + IO_IRQ_LINES; i++)
109 set_irq_chip_and_handler(i, &ioasic_dma_irq_type, 108 set_irq_chip(i, &ioasic_dma_irq_type);
110 handle_level_irq);
111 109
112 ioasic_irq_base = base; 110 ioasic_irq_base = base;
113} 111}
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
index f19b4617a0a6..d3b8002bf1e7 100644
--- a/arch/mips/dec/kn01-berr.c
+++ b/arch/mips/dec/kn01-berr.c
@@ -20,8 +20,10 @@
20#include <linux/types.h> 20#include <linux/types.h>
21 21
22#include <asm/inst.h> 22#include <asm/inst.h>
23#include <asm/irq_regs.h>
23#include <asm/mipsregs.h> 24#include <asm/mipsregs.h>
24#include <asm/page.h> 25#include <asm/page.h>
26#include <asm/ptrace.h>
25#include <asm/system.h> 27#include <asm/system.h>
26#include <asm/traps.h> 28#include <asm/traps.h>
27#include <asm/uaccess.h> 29#include <asm/uaccess.h>
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 5a9be4c93584..916e46b8ccd8 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -57,19 +57,12 @@ static void ack_kn02_irq(unsigned int irq)
57 iob(); 57 iob();
58} 58}
59 59
60static void end_kn02_irq(unsigned int irq)
61{
62 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
63 unmask_kn02_irq(irq);
64}
65
66static struct irq_chip kn02_irq_type = { 60static struct irq_chip kn02_irq_type = {
67 .typename = "KN02-CSR", 61 .typename = "KN02-CSR",
68 .ack = ack_kn02_irq, 62 .ack = ack_kn02_irq,
69 .mask = mask_kn02_irq, 63 .mask = mask_kn02_irq,
70 .mask_ack = ack_kn02_irq, 64 .mask_ack = ack_kn02_irq,
71 .unmask = unmask_kn02_irq, 65 .unmask = unmask_kn02_irq,
72 .end = end_kn02_irq,
73}; 66};
74 67
75 68
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
index 59b98299c896..8d880f0b06ec 100644
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -56,19 +56,12 @@ static void emma2rh_irq_disable(unsigned int irq)
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base); 56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57} 57}
58 58
59static void emma2rh_irq_end(unsigned int irq)
60{
61 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
62 ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
63}
64
65struct irq_chip emma2rh_irq_controller = { 59struct irq_chip emma2rh_irq_controller = {
66 .typename = "emma2rh_irq", 60 .typename = "emma2rh_irq",
67 .ack = emma2rh_irq_disable, 61 .ack = emma2rh_irq_disable,
68 .mask = emma2rh_irq_disable, 62 .mask = emma2rh_irq_disable,
69 .mask_ack = emma2rh_irq_disable, 63 .mask_ack = emma2rh_irq_disable,
70 .unmask = emma2rh_irq_enable, 64 .unmask = emma2rh_irq_enable,
71 .end = emma2rh_irq_end,
72}; 65};
73 66
74void emma2rh_irq_init(u32 irq_base) 67void emma2rh_irq_init(u32 irq_base)
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
index 3ac4e405ecdc..2116d9be5fa9 100644
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -48,19 +48,12 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); 48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49} 49}
50 50
51static void emma2rh_sw_irq_end(unsigned int irq)
52{
53 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
54 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
55}
56
57struct irq_chip emma2rh_sw_irq_controller = { 51struct irq_chip emma2rh_sw_irq_controller = {
58 .typename = "emma2rh_sw_irq", 52 .typename = "emma2rh_sw_irq",
59 .ack = emma2rh_sw_irq_disable, 53 .ack = emma2rh_sw_irq_disable,
60 .mask = emma2rh_sw_irq_disable, 54 .mask = emma2rh_sw_irq_disable,
61 .mask_ack = emma2rh_sw_irq_disable, 55 .mask_ack = emma2rh_sw_irq_disable,
62 .unmask = emma2rh_sw_irq_enable, 56 .unmask = emma2rh_sw_irq_enable,
63 .end = emma2rh_sw_irq_end,
64}; 57};
65 58
66void emma2rh_sw_irq_init(u32 irq_base) 59void emma2rh_sw_irq_init(u32 irq_base)
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 5c4f50cdf157..f8d417b5c2bb 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -39,19 +39,12 @@ void disable_r4030_irq(unsigned int irq)
39 spin_unlock_irqrestore(&r4030_lock, flags); 39 spin_unlock_irqrestore(&r4030_lock, flags);
40} 40}
41 41
42static void end_r4030_irq(unsigned int irq)
43{
44 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
45 enable_r4030_irq(irq);
46}
47
48static struct irq_chip r4030_irq_type = { 42static struct irq_chip r4030_irq_type = {
49 .typename = "R4030", 43 .typename = "R4030",
50 .ack = disable_r4030_irq, 44 .ack = disable_r4030_irq,
51 .mask = disable_r4030_irq, 45 .mask = disable_r4030_irq,
52 .mask_ack = disable_r4030_irq, 46 .mask_ack = disable_r4030_irq,
53 .unmask = enable_r4030_irq, 47 .unmask = enable_r4030_irq,
54 .end = end_r4030_irq,
55}; 48};
56 49
57void __init init_r4030_ints(void) 50void __init init_r4030_ints(void)
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 2526c0ca4d81..b59a676c6d0e 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -19,9 +19,6 @@
19#include <asm/i8259.h> 19#include <asm/i8259.h>
20#include <asm/io.h> 20#include <asm/io.h>
21 21
22void enable_8259A_irq(unsigned int irq);
23void disable_8259A_irq(unsigned int irq);
24
25/* 22/*
26 * This is the 'legacy' 8259A Programmable Interrupt Controller, 23 * This is the 'legacy' 8259A Programmable Interrupt Controller,
27 * present in the majority of PC/AT boxes. 24 * present in the majority of PC/AT boxes.
@@ -31,23 +28,16 @@ void disable_8259A_irq(unsigned int irq);
31 * moves to arch independent land 28 * moves to arch independent land
32 */ 29 */
33 30
31static int i8259A_auto_eoi;
34DEFINE_SPINLOCK(i8259A_lock); 32DEFINE_SPINLOCK(i8259A_lock);
35 33/* some platforms call this... */
36static void end_8259A_irq (unsigned int irq)
37{
38 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
39 irq_desc[irq].action)
40 enable_8259A_irq(irq);
41}
42
43void mask_and_ack_8259A(unsigned int); 34void mask_and_ack_8259A(unsigned int);
44 35
45static struct irq_chip i8259A_irq_type = { 36static struct irq_chip i8259A_chip = {
46 .typename = "XT-PIC", 37 .name = "XT-PIC",
47 .enable = enable_8259A_irq, 38 .mask = disable_8259A_irq,
48 .disable = disable_8259A_irq, 39 .unmask = enable_8259A_irq,
49 .ack = mask_and_ack_8259A, 40 .mask_ack = mask_and_ack_8259A,
50 .end = end_8259A_irq,
51}; 41};
52 42
53/* 43/*
@@ -59,8 +49,8 @@ static struct irq_chip i8259A_irq_type = {
59 */ 49 */
60static unsigned int cached_irq_mask = 0xffff; 50static unsigned int cached_irq_mask = 0xffff;
61 51
62#define cached_21 (cached_irq_mask) 52#define cached_master_mask (cached_irq_mask)
63#define cached_A1 (cached_irq_mask >> 8) 53#define cached_slave_mask (cached_irq_mask >> 8)
64 54
65void disable_8259A_irq(unsigned int irq) 55void disable_8259A_irq(unsigned int irq)
66{ 56{
@@ -70,9 +60,9 @@ void disable_8259A_irq(unsigned int irq)
70 spin_lock_irqsave(&i8259A_lock, flags); 60 spin_lock_irqsave(&i8259A_lock, flags);
71 cached_irq_mask |= mask; 61 cached_irq_mask |= mask;
72 if (irq & 8) 62 if (irq & 8)
73 outb(cached_A1,0xA1); 63 outb(cached_slave_mask, PIC_SLAVE_IMR);
74 else 64 else
75 outb(cached_21,0x21); 65 outb(cached_master_mask, PIC_MASTER_IMR);
76 spin_unlock_irqrestore(&i8259A_lock, flags); 66 spin_unlock_irqrestore(&i8259A_lock, flags);
77} 67}
78 68
@@ -84,9 +74,9 @@ void enable_8259A_irq(unsigned int irq)
84 spin_lock_irqsave(&i8259A_lock, flags); 74 spin_lock_irqsave(&i8259A_lock, flags);
85 cached_irq_mask &= mask; 75 cached_irq_mask &= mask;
86 if (irq & 8) 76 if (irq & 8)
87 outb(cached_A1,0xA1); 77 outb(cached_slave_mask, PIC_SLAVE_IMR);
88 else 78 else
89 outb(cached_21,0x21); 79 outb(cached_master_mask, PIC_MASTER_IMR);
90 spin_unlock_irqrestore(&i8259A_lock, flags); 80 spin_unlock_irqrestore(&i8259A_lock, flags);
91} 81}
92 82
@@ -98,9 +88,9 @@ int i8259A_irq_pending(unsigned int irq)
98 88
99 spin_lock_irqsave(&i8259A_lock, flags); 89 spin_lock_irqsave(&i8259A_lock, flags);
100 if (irq < 8) 90 if (irq < 8)
101 ret = inb(0x20) & mask; 91 ret = inb(PIC_MASTER_CMD) & mask;
102 else 92 else
103 ret = inb(0xA0) & (mask >> 8); 93 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
104 spin_unlock_irqrestore(&i8259A_lock, flags); 94 spin_unlock_irqrestore(&i8259A_lock, flags);
105 95
106 return ret; 96 return ret;
@@ -109,7 +99,7 @@ int i8259A_irq_pending(unsigned int irq)
109void make_8259A_irq(unsigned int irq) 99void make_8259A_irq(unsigned int irq)
110{ 100{
111 disable_irq_nosync(irq); 101 disable_irq_nosync(irq);
112 set_irq_chip(irq, &i8259A_irq_type); 102 set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
113 enable_irq(irq); 103 enable_irq(irq);
114} 104}
115 105
@@ -125,14 +115,14 @@ static inline int i8259A_irq_real(unsigned int irq)
125 int irqmask = 1 << irq; 115 int irqmask = 1 << irq;
126 116
127 if (irq < 8) { 117 if (irq < 8) {
128 outb(0x0B,0x20); /* ISR register */ 118 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
129 value = inb(0x20) & irqmask; 119 value = inb(PIC_MASTER_CMD) & irqmask;
130 outb(0x0A,0x20); /* back to the IRR register */ 120 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
131 return value; 121 return value;
132 } 122 }
133 outb(0x0B,0xA0); /* ISR register */ 123 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
134 value = inb(0xA0) & (irqmask >> 8); 124 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
135 outb(0x0A,0xA0); /* back to the IRR register */ 125 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
136 return value; 126 return value;
137} 127}
138 128
@@ -149,17 +139,19 @@ void mask_and_ack_8259A(unsigned int irq)
149 139
150 spin_lock_irqsave(&i8259A_lock, flags); 140 spin_lock_irqsave(&i8259A_lock, flags);
151 /* 141 /*
152 * Lightweight spurious IRQ detection. We do not want to overdo 142 * Lightweight spurious IRQ detection. We do not want
153 * spurious IRQ handling - it's usually a sign of hardware problems, so 143 * to overdo spurious IRQ handling - it's usually a sign
154 * we only do the checks we can do without slowing down good hardware 144 * of hardware problems, so we only do the checks we can
155 * nnecesserily. 145 * do without slowing down good hardware unnecessarily.
156 * 146 *
157 * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting 147 * Note that IRQ7 and IRQ15 (the two spurious IRQs
158 * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A. 148 * usually resulting from the 8259A-1|2 PICs) occur
159 * Thus we can check spurious 8259A IRQs without doing the quite slow 149 * even if the IRQ is masked in the 8259A. Thus we
160 * i8259A_irq_real() call for every IRQ. This does not cover 100% of 150 * can check spurious 8259A IRQs without doing the
161 * spurious interrupts, but should be enough to warn the user that 151 * quite slow i8259A_irq_real() call for every IRQ.
162 * there is something bad going on ... 152 * This does not cover 100% of spurious interrupts,
153 * but should be enough to warn the user that there
154 * is something bad going on ...
163 */ 155 */
164 if (cached_irq_mask & irqmask) 156 if (cached_irq_mask & irqmask)
165 goto spurious_8259A_irq; 157 goto spurious_8259A_irq;
@@ -167,14 +159,14 @@ void mask_and_ack_8259A(unsigned int irq)
167 159
168handle_real_irq: 160handle_real_irq:
169 if (irq & 8) { 161 if (irq & 8) {
170 inb(0xA1); /* DUMMY - (do we need this?) */ 162 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
171 outb(cached_A1,0xA1); 163 outb(cached_slave_mask, PIC_SLAVE_IMR);
172 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */ 164 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
173 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ 165 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
174 } else { 166 } else {
175 inb(0x21); /* DUMMY - (do we need this?) */ 167 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
176 outb(cached_21,0x21); 168 outb(cached_master_mask, PIC_MASTER_IMR);
177 outb(0x60+irq,0x20); /* 'Specific EOI' to master */ 169 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
178 } 170 }
179#ifdef CONFIG_MIPS_MT_SMTC 171#ifdef CONFIG_MIPS_MT_SMTC
180 if (irq_hwmask[irq] & ST0_IM) 172 if (irq_hwmask[irq] & ST0_IM)
@@ -195,7 +187,7 @@ spurious_8259A_irq:
195 goto handle_real_irq; 187 goto handle_real_irq;
196 188
197 { 189 {
198 static int spurious_irq_mask = 0; 190 static int spurious_irq_mask;
199 /* 191 /*
200 * At this point we can be sure the IRQ is spurious, 192 * At this point we can be sure the IRQ is spurious,
201 * lets ACK and report it. [once per IRQ] 193 * lets ACK and report it. [once per IRQ]
@@ -216,13 +208,25 @@ spurious_8259A_irq:
216 208
217static int i8259A_resume(struct sys_device *dev) 209static int i8259A_resume(struct sys_device *dev)
218{ 210{
219 init_8259A(0); 211 init_8259A(i8259A_auto_eoi);
212 return 0;
213}
214
215static int i8259A_shutdown(struct sys_device *dev)
216{
217 /* Put the i8259A into a quiescent state that
218 * the kernel initialization code can get it
219 * out of.
220 */
221 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
222 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
220 return 0; 223 return 0;
221} 224}
222 225
223static struct sysdev_class i8259_sysdev_class = { 226static struct sysdev_class i8259_sysdev_class = {
224 set_kset_name("i8259"), 227 set_kset_name("i8259"),
225 .resume = i8259A_resume, 228 .resume = i8259A_resume,
229 .shutdown = i8259A_shutdown,
226}; 230};
227 231
228static struct sys_device device_i8259A = { 232static struct sys_device device_i8259A = {
@@ -244,41 +248,41 @@ void __init init_8259A(int auto_eoi)
244{ 248{
245 unsigned long flags; 249 unsigned long flags;
246 250
251 i8259A_auto_eoi = auto_eoi;
252
247 spin_lock_irqsave(&i8259A_lock, flags); 253 spin_lock_irqsave(&i8259A_lock, flags);
248 254
249 outb(0xff, 0x21); /* mask all of 8259A-1 */ 255 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
250 outb(0xff, 0xA1); /* mask all of 8259A-2 */ 256 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
251 257
252 /* 258 /*
253 * outb_p - this has to work on a wide range of PC hardware. 259 * outb_p - this has to work on a wide range of PC hardware.
254 */ 260 */
255 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ 261 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
256 outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */ 262 outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
257 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ 263 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
258 if (auto_eoi) 264 if (auto_eoi) /* master does Auto EOI */
259 outb_p(0x03, 0x21); /* master does Auto EOI */ 265 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
260 else 266 else /* master expects normal EOI */
261 outb_p(0x01, 0x21); /* master expects normal EOI */ 267 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
262 268
263 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ 269 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
264 outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */ 270 outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
265 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ 271 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
266 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode 272 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
267 is to be investigated) */
268
269 if (auto_eoi) 273 if (auto_eoi)
270 /* 274 /*
271 * in AEOI mode we just have to mask the interrupt 275 * In AEOI mode we just have to mask the interrupt
272 * when acking. 276 * when acking.
273 */ 277 */
274 i8259A_irq_type.ack = disable_8259A_irq; 278 i8259A_chip.mask_ack = disable_8259A_irq;
275 else 279 else
276 i8259A_irq_type.ack = mask_and_ack_8259A; 280 i8259A_chip.mask_ack = mask_and_ack_8259A;
277 281
278 udelay(100); /* wait for 8259A to initialize */ 282 udelay(100); /* wait for 8259A to initialize */
279 283
280 outb(cached_21, 0x21); /* restore master IRQ mask */ 284 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
281 outb(cached_A1, 0xA1); /* restore slave IRQ mask */ 285 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
282 286
283 spin_unlock_irqrestore(&i8259A_lock, flags); 287 spin_unlock_irqrestore(&i8259A_lock, flags);
284} 288}
@@ -291,11 +295,17 @@ static struct irqaction irq2 = {
291}; 295};
292 296
293static struct resource pic1_io_resource = { 297static struct resource pic1_io_resource = {
294 .name = "pic1", .start = 0x20, .end = 0x21, .flags = IORESOURCE_BUSY 298 .name = "pic1",
299 .start = PIC_MASTER_CMD,
300 .end = PIC_MASTER_IMR,
301 .flags = IORESOURCE_BUSY
295}; 302};
296 303
297static struct resource pic2_io_resource = { 304static struct resource pic2_io_resource = {
298 .name = "pic2", .start = 0xa0, .end = 0xa1, .flags = IORESOURCE_BUSY 305 .name = "pic2",
306 .start = PIC_SLAVE_CMD,
307 .end = PIC_SLAVE_IMR,
308 .flags = IORESOURCE_BUSY
299}; 309};
300 310
301/* 311/*
@@ -313,7 +323,7 @@ void __init init_i8259_irqs (void)
313 init_8259A(0); 323 init_8259A(0);
314 324
315 for (i = 0; i < 16; i++) 325 for (i = 0; i < 16; i++)
316 set_irq_chip(i, &i8259A_irq_type); 326 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
317 327
318 setup_irq(2, &irq2); 328 setup_irq(PIC_CASCADE_IR, &irq2);
319} 329}
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 6cfb31cafde2..efbd219845b5 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -67,15 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq)
67} 67}
68 68
69/* 69/*
70 * End IRQ processing
71 */
72static void end_mv64340_irq(unsigned int irq)
73{
74 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
75 unmask_mv64340_irq(irq);
76}
77
78/*
79 * Interrupt handler for interrupts coming from the Marvell chip. 70 * Interrupt handler for interrupts coming from the Marvell chip.
80 * It could be built in ethernet ports etc... 71 * It could be built in ethernet ports etc...
81 */ 72 */
@@ -106,7 +97,6 @@ struct irq_chip mv64340_irq_type = {
106 .mask = mask_mv64340_irq, 97 .mask = mask_mv64340_irq,
107 .mask_ack = mask_mv64340_irq, 98 .mask_ack = mask_mv64340_irq,
108 .unmask = unmask_mv64340_irq, 99 .unmask = unmask_mv64340_irq,
109 .end = end_mv64340_irq,
110}; 100};
111 101
112void __init mv64340_irq_init(unsigned int base) 102void __init mv64340_irq_init(unsigned int base)
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index ddcc2a5f8a06..123324ba8c14 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -29,19 +29,12 @@ static inline void mask_rm7k_irq(unsigned int irq)
29 clear_c0_intcontrol(0x100 << (irq - irq_base)); 29 clear_c0_intcontrol(0x100 << (irq - irq_base));
30} 30}
31 31
32static void rm7k_cpu_irq_end(unsigned int irq)
33{
34 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
35 unmask_rm7k_irq(irq);
36}
37
38static struct irq_chip rm7k_irq_controller = { 32static struct irq_chip rm7k_irq_controller = {
39 .typename = "RM7000", 33 .typename = "RM7000",
40 .ack = mask_rm7k_irq, 34 .ack = mask_rm7k_irq,
41 .mask = mask_rm7k_irq, 35 .mask = mask_rm7k_irq,
42 .mask_ack = mask_rm7k_irq, 36 .mask_ack = mask_rm7k_irq,
43 .unmask = unmask_rm7k_irq, 37 .unmask = unmask_rm7k_irq,
44 .end = rm7k_cpu_irq_end,
45}; 38};
46 39
47void __init rm7k_cpu_irq_init(int base) 40void __init rm7k_cpu_irq_init(int base)
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index ba6440c88abd..0e6f4c5349d2 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -80,19 +80,12 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
80 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); 80 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
81} 81}
82 82
83static void rm9k_cpu_irq_end(unsigned int irq)
84{
85 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
86 unmask_rm9k_irq(irq);
87}
88
89static struct irq_chip rm9k_irq_controller = { 83static struct irq_chip rm9k_irq_controller = {
90 .typename = "RM9000", 84 .typename = "RM9000",
91 .ack = mask_rm9k_irq, 85 .ack = mask_rm9k_irq,
92 .mask = mask_rm9k_irq, 86 .mask = mask_rm9k_irq,
93 .mask_ack = mask_rm9k_irq, 87 .mask_ack = mask_rm9k_irq,
94 .unmask = unmask_rm9k_irq, 88 .unmask = unmask_rm9k_irq,
95 .end = rm9k_cpu_irq_end,
96}; 89};
97 90
98static struct irq_chip rm9k_perfcounter_irq = { 91static struct irq_chip rm9k_perfcounter_irq = {
@@ -103,7 +96,6 @@ static struct irq_chip rm9k_perfcounter_irq = {
103 .mask = mask_rm9k_irq, 96 .mask = mask_rm9k_irq,
104 .mask_ack = mask_rm9k_irq, 97 .mask_ack = mask_rm9k_irq,
105 .unmask = unmask_rm9k_irq, 98 .unmask = unmask_rm9k_irq,
106 .end = rm9k_cpu_irq_end,
107}; 99};
108 100
109unsigned int rm9000_perfcount_irq; 101unsigned int rm9000_perfcount_irq;
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index b339798b3172..2fe4c868a801 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -117,7 +117,7 @@ int show_interrupts(struct seq_file *p, void *v)
117 for_each_online_cpu(j) 117 for_each_online_cpu(j)
118 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 118 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
119#endif 119#endif
120 seq_printf(p, " %14s", irq_desc[i].chip->typename); 120 seq_printf(p, " %14s", irq_desc[i].chip->name);
121 seq_printf(p, " %s", action->name); 121 seq_printf(p, " %s", action->name);
122 122
123 for (action=action->next; action; action = action->next) 123 for (action=action->next; action; action = action->next)
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index be5ac23d3812..fcc86b96ccf6 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -50,12 +50,6 @@ static inline void mask_mips_irq(unsigned int irq)
50 irq_disable_hazard(); 50 irq_disable_hazard();
51} 51}
52 52
53static void mips_cpu_irq_end(unsigned int irq)
54{
55 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
56 unmask_mips_irq(irq);
57}
58
59static struct irq_chip mips_cpu_irq_controller = { 53static struct irq_chip mips_cpu_irq_controller = {
60 .typename = "MIPS", 54 .typename = "MIPS",
61 .ack = mask_mips_irq, 55 .ack = mask_mips_irq,
@@ -63,7 +57,6 @@ static struct irq_chip mips_cpu_irq_controller = {
63 .mask_ack = mask_mips_irq, 57 .mask_ack = mask_mips_irq,
64 .unmask = unmask_mips_irq, 58 .unmask = unmask_mips_irq,
65 .eoi = unmask_mips_irq, 59 .eoi = unmask_mips_irq,
66 .end = mips_cpu_irq_end,
67}; 60};
68 61
69/* 62/*
@@ -96,8 +89,6 @@ static void mips_mt_cpu_irq_ack(unsigned int irq)
96 mask_mips_mt_irq(irq); 89 mask_mips_mt_irq(irq);
97} 90}
98 91
99#define mips_mt_cpu_irq_end mips_cpu_irq_end
100
101static struct irq_chip mips_mt_cpu_irq_controller = { 92static struct irq_chip mips_mt_cpu_irq_controller = {
102 .typename = "MIPS", 93 .typename = "MIPS",
103 .startup = mips_mt_cpu_irq_startup, 94 .startup = mips_mt_cpu_irq_startup,
@@ -106,7 +97,6 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
106 .mask_ack = mips_mt_cpu_irq_ack, 97 .mask_ack = mips_mt_cpu_irq_ack,
107 .unmask = unmask_mips_mt_irq, 98 .unmask = unmask_mips_mt_irq,
108 .eoi = unmask_mips_mt_irq, 99 .eoi = unmask_mips_mt_irq,
109 .end = mips_mt_cpu_irq_end,
110}; 100};
111 101
112void __init mips_cpu_irq_init(int irq_base) 102void __init mips_cpu_irq_init(int irq_base)
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 4a84a7beac53..2affa5ff171c 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -44,19 +44,12 @@ void enable_lasat_irq(unsigned int irq_nr)
44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; 44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
45} 45}
46 46
47static void end_lasat_irq(unsigned int irq)
48{
49 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
50 enable_lasat_irq(irq);
51}
52
53static struct irq_chip lasat_irq_type = { 47static struct irq_chip lasat_irq_type = {
54 .typename = "Lasat", 48 .typename = "Lasat",
55 .ack = disable_lasat_irq, 49 .ack = disable_lasat_irq,
56 .mask = disable_lasat_irq, 50 .mask = disable_lasat_irq,
57 .mask_ack = disable_lasat_irq, 51 .mask_ack = disable_lasat_irq,
58 .unmask = enable_lasat_irq, 52 .unmask = enable_lasat_irq,
59 .end = end_lasat_irq,
60}; 53};
61 54
62static inline int ls1bit32(unsigned int x) 55static inline int ls1bit32(unsigned int x)
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index e5a4a0a8a7f0..bb11fef08472 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -66,15 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
66} 66}
67 67
68/* 68/*
69 * End IRQ processing
70 */
71static void end_cpci_irq(unsigned int irq)
72{
73 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
74 unmask_cpci_irq(irq);
75}
76
77/*
78 * Interrupt handler for interrupts coming from the FPGA chip. 69 * Interrupt handler for interrupts coming from the FPGA chip.
79 * It could be built in ethernet ports etc... 70 * It could be built in ethernet ports etc...
80 */ 71 */
@@ -98,7 +89,6 @@ struct irq_chip cpci_irq_type = {
98 .mask = mask_cpci_irq, 89 .mask = mask_cpci_irq,
99 .mask_ack = mask_cpci_irq, 90 .mask_ack = mask_cpci_irq,
100 .unmask = unmask_cpci_irq, 91 .unmask = unmask_cpci_irq,
101 .end = end_cpci_irq,
102}; 92};
103 93
104void cpci_irq_init(void) 94void cpci_irq_init(void)
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 0029f0008dea..a7a80c0da569 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -60,15 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq)
60} 60}
61 61
62/* 62/*
63 * End IRQ processing
64 */
65static void end_uart_irq(unsigned int irq)
66{
67 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
68 unmask_uart_irq(irq);
69}
70
71/*
72 * Interrupt handler for interrupts coming from the FPGA chip. 63 * Interrupt handler for interrupts coming from the FPGA chip.
73 */ 64 */
74void ll_uart_irq(void) 65void ll_uart_irq(void)
@@ -91,7 +82,6 @@ struct irq_chip uart_irq_type = {
91 .mask = mask_uart_irq, 82 .mask = mask_uart_irq,
92 .mask_ack = mask_uart_irq, 83 .mask_ack = mask_uart_irq,
93 .unmask = unmask_uart_irq, 84 .unmask = unmask_uart_irq,
94 .end = end_uart_irq,
95}; 85};
96 86
97void uart_irq_init(void) 87void uart_irq_init(void)
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 0dc23930edbd..2c36c108c4d6 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -158,20 +158,12 @@ int pnx8550_set_gic_priority(int irq, int priority)
158 return prev_priority; 158 return prev_priority;
159} 159}
160 160
161static void end_irq(unsigned int irq)
162{
163 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
164 unmask_irq(irq);
165 }
166}
167
168static struct irq_chip level_irq_type = { 161static struct irq_chip level_irq_type = {
169 .typename = "PNX Level IRQ", 162 .typename = "PNX Level IRQ",
170 .ack = mask_irq, 163 .ack = mask_irq,
171 .mask = mask_irq, 164 .mask = mask_irq,
172 .mask_ack = mask_irq, 165 .mask_ack = mask_irq,
173 .unmask = unmask_irq, 166 .unmask = unmask_irq,
174 .end = end_irq,
175}; 167};
176 168
177static struct irqaction gic_action = { 169static struct irqaction gic_action = {
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index c7b138053159..c44f8be0644f 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -51,19 +51,12 @@ static void disable_local0_irq(unsigned int irq)
51 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); 51 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
52} 52}
53 53
54static void end_local0_irq (unsigned int irq)
55{
56 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
57 enable_local0_irq(irq);
58}
59
60static struct irq_chip ip22_local0_irq_type = { 54static struct irq_chip ip22_local0_irq_type = {
61 .typename = "IP22 local 0", 55 .typename = "IP22 local 0",
62 .ack = disable_local0_irq, 56 .ack = disable_local0_irq,
63 .mask = disable_local0_irq, 57 .mask = disable_local0_irq,
64 .mask_ack = disable_local0_irq, 58 .mask_ack = disable_local0_irq,
65 .unmask = enable_local0_irq, 59 .unmask = enable_local0_irq,
66 .end = end_local0_irq,
67}; 60};
68 61
69static void enable_local1_irq(unsigned int irq) 62static void enable_local1_irq(unsigned int irq)
@@ -79,19 +72,12 @@ void disable_local1_irq(unsigned int irq)
79 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); 72 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
80} 73}
81 74
82static void end_local1_irq (unsigned int irq)
83{
84 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
85 enable_local1_irq(irq);
86}
87
88static struct irq_chip ip22_local1_irq_type = { 75static struct irq_chip ip22_local1_irq_type = {
89 .typename = "IP22 local 1", 76 .typename = "IP22 local 1",
90 .ack = disable_local1_irq, 77 .ack = disable_local1_irq,
91 .mask = disable_local1_irq, 78 .mask = disable_local1_irq,
92 .mask_ack = disable_local1_irq, 79 .mask_ack = disable_local1_irq,
93 .unmask = enable_local1_irq, 80 .unmask = enable_local1_irq,
94 .end = end_local1_irq,
95}; 81};
96 82
97static void enable_local2_irq(unsigned int irq) 83static void enable_local2_irq(unsigned int irq)
@@ -107,19 +93,12 @@ void disable_local2_irq(unsigned int irq)
107 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 93 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
108} 94}
109 95
110static void end_local2_irq (unsigned int irq)
111{
112 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
113 enable_local2_irq(irq);
114}
115
116static struct irq_chip ip22_local2_irq_type = { 96static struct irq_chip ip22_local2_irq_type = {
117 .typename = "IP22 local 2", 97 .typename = "IP22 local 2",
118 .ack = disable_local2_irq, 98 .ack = disable_local2_irq,
119 .mask = disable_local2_irq, 99 .mask = disable_local2_irq,
120 .mask_ack = disable_local2_irq, 100 .mask_ack = disable_local2_irq,
121 .unmask = enable_local2_irq, 101 .unmask = enable_local2_irq,
122 .end = end_local2_irq,
123}; 102};
124 103
125static void enable_local3_irq(unsigned int irq) 104static void enable_local3_irq(unsigned int irq)
@@ -135,19 +114,12 @@ void disable_local3_irq(unsigned int irq)
135 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 114 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
136} 115}
137 116
138static void end_local3_irq (unsigned int irq)
139{
140 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
141 enable_local3_irq(irq);
142}
143
144static struct irq_chip ip22_local3_irq_type = { 117static struct irq_chip ip22_local3_irq_type = {
145 .typename = "IP22 local 3", 118 .typename = "IP22 local 3",
146 .ack = disable_local3_irq, 119 .ack = disable_local3_irq,
147 .mask = disable_local3_irq, 120 .mask = disable_local3_irq,
148 .mask_ack = disable_local3_irq, 121 .mask_ack = disable_local3_irq,
149 .unmask = enable_local3_irq, 122 .unmask = enable_local3_irq,
150 .end = end_local3_irq,
151}; 123};
152 124
153static void indy_local0_irqdispatch(void) 125static void indy_local0_irqdispatch(void)
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 5f8835b4e84a..319f8803ef6f 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -332,13 +332,6 @@ static inline void disable_bridge_irq(unsigned int irq)
332 intr_disconnect_level(cpu, swlevel); 332 intr_disconnect_level(cpu, swlevel);
333} 333}
334 334
335static void end_bridge_irq(unsigned int irq)
336{
337 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
338 irq_desc[irq].action)
339 enable_bridge_irq(irq);
340}
341
342static struct irq_chip bridge_irq_type = { 335static struct irq_chip bridge_irq_type = {
343 .typename = "bridge", 336 .typename = "bridge",
344 .startup = startup_bridge_irq, 337 .startup = startup_bridge_irq,
@@ -347,7 +340,6 @@ static struct irq_chip bridge_irq_type = {
347 .mask = disable_bridge_irq, 340 .mask = disable_bridge_irq,
348 .mask_ack = disable_bridge_irq, 341 .mask_ack = disable_bridge_irq,
349 .unmask = enable_bridge_irq, 342 .unmask = enable_bridge_irq,
350 .end = end_bridge_irq,
351}; 343};
352 344
353void __devinit register_bridge_irq(unsigned int irq) 345void __devinit register_bridge_irq(unsigned int irq)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 7d361726bbfb..c20e9899b34b 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -180,10 +180,6 @@ static void disable_rt_irq(unsigned int irq)
180{ 180{
181} 181}
182 182
183static void end_rt_irq(unsigned int irq)
184{
185}
186
187static struct irq_chip rt_irq_type = { 183static struct irq_chip rt_irq_type = {
188 .typename = "SN HUB RT timer", 184 .typename = "SN HUB RT timer",
189 .ack = disable_rt_irq, 185 .ack = disable_rt_irq,
@@ -191,7 +187,6 @@ static struct irq_chip rt_irq_type = {
191 .mask_ack = disable_rt_irq, 187 .mask_ack = disable_rt_irq,
192 .unmask = enable_rt_irq, 188 .unmask = enable_rt_irq,
193 .eoi = enable_rt_irq, 189 .eoi = enable_rt_irq,
194 .end = end_rt_irq,
195}; 190};
196 191
197static struct irqaction rt_irqaction = { 192static struct irqaction rt_irqaction = {
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 21873de49aa8..ed4a19adf361 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -66,12 +66,10 @@
66#define TX4927_IRQ_CP0_INIT ( 1 << 10 ) 66#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
67#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) 67#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
68#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) 68#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
69#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
70 69
71#define TX4927_IRQ_PIC_INIT ( 1 << 20 ) 70#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
72#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) 71#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
73#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) 72#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
74#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
75 73
76#define TX4927_IRQ_ALL 0xffffffff 74#define TX4927_IRQ_ALL 0xffffffff
77#endif 75#endif
@@ -82,12 +80,10 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
82 | TX4927_IRQ_WARN | TX4927_IRQ_EROR 80 | TX4927_IRQ_WARN | TX4927_IRQ_EROR
83// | TX4927_IRQ_CP0_INIT 81// | TX4927_IRQ_CP0_INIT
84// | TX4927_IRQ_CP0_ENABLE 82// | TX4927_IRQ_CP0_ENABLE
85// | TX4927_IRQ_CP0_DISABLE
86// | TX4927_IRQ_CP0_ENDIRQ 83// | TX4927_IRQ_CP0_ENDIRQ
87// | TX4927_IRQ_PIC_INIT 84// | TX4927_IRQ_PIC_INIT
88// | TX4927_IRQ_PIC_ENABLE 85// | TX4927_IRQ_PIC_ENABLE
89// | TX4927_IRQ_PIC_DISABLE 86// | TX4927_IRQ_PIC_DISABLE
90// | TX4927_IRQ_PIC_ENDIRQ
91// | TX4927_IRQ_INIT 87// | TX4927_IRQ_INIT
92// | TX4927_IRQ_NEST1 88// | TX4927_IRQ_NEST1
93// | TX4927_IRQ_NEST2 89// | TX4927_IRQ_NEST2
@@ -114,11 +110,9 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
114 110
115static void tx4927_irq_cp0_enable(unsigned int irq); 111static void tx4927_irq_cp0_enable(unsigned int irq);
116static void tx4927_irq_cp0_disable(unsigned int irq); 112static void tx4927_irq_cp0_disable(unsigned int irq);
117static void tx4927_irq_cp0_end(unsigned int irq);
118 113
119static void tx4927_irq_pic_enable(unsigned int irq); 114static void tx4927_irq_pic_enable(unsigned int irq);
120static void tx4927_irq_pic_disable(unsigned int irq); 115static void tx4927_irq_pic_disable(unsigned int irq);
121static void tx4927_irq_pic_end(unsigned int irq);
122 116
123/* 117/*
124 * Kernel structs for all pic's 118 * Kernel structs for all pic's
@@ -131,7 +125,6 @@ static struct irq_chip tx4927_irq_cp0_type = {
131 .mask = tx4927_irq_cp0_disable, 125 .mask = tx4927_irq_cp0_disable,
132 .mask_ack = tx4927_irq_cp0_disable, 126 .mask_ack = tx4927_irq_cp0_disable,
133 .unmask = tx4927_irq_cp0_enable, 127 .unmask = tx4927_irq_cp0_enable,
134 .end = tx4927_irq_cp0_end,
135}; 128};
136 129
137#define TX4927_PIC_NAME "TX4927-PIC" 130#define TX4927_PIC_NAME "TX4927-PIC"
@@ -141,7 +134,6 @@ static struct irq_chip tx4927_irq_pic_type = {
141 .mask = tx4927_irq_pic_disable, 134 .mask = tx4927_irq_pic_disable,
142 .mask_ack = tx4927_irq_pic_disable, 135 .mask_ack = tx4927_irq_pic_disable,
143 .unmask = tx4927_irq_pic_enable, 136 .unmask = tx4927_irq_pic_enable,
144 .end = tx4927_irq_pic_end,
145}; 137};
146 138
147#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 139#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
@@ -214,15 +206,6 @@ static void tx4927_irq_cp0_disable(unsigned int irq)
214 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); 206 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
215} 207}
216 208
217static void tx4927_irq_cp0_end(unsigned int irq)
218{
219 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq);
220
221 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
222 tx4927_irq_cp0_enable(irq);
223 }
224}
225
226/* 209/*
227 * Functions for pic 210 * Functions for pic
228 */ 211 */
@@ -376,15 +359,6 @@ static void tx4927_irq_pic_disable(unsigned int irq)
376 tx4927_irq_pic_mask(irq), 0); 359 tx4927_irq_pic_mask(irq), 0);
377} 360}
378 361
379static void tx4927_irq_pic_end(unsigned int irq)
380{
381 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq);
382
383 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
384 tx4927_irq_pic_enable(irq);
385 }
386}
387
388/* 362/*
389 * Main init functions 363 * Main init functions
390 */ 364 */
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 34cdb2a240e9..5a5ea6c0b9f6 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -153,7 +153,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) 153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
154#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) 154#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
155#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) 155#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
156#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
157 156
158#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) 157#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
159#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) 158#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
@@ -172,7 +171,6 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
172// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 171// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
173// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 172// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
174// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 173// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
175// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
176// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 174// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
177// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 175// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
178// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 176// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
@@ -223,7 +221,6 @@ extern void mask_and_ack_8259A(unsigned int irq);
223 221
224static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 222static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
225static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 223static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
226static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
227 224
228#ifdef CONFIG_TOSHIBA_FPCIB0 225#ifdef CONFIG_TOSHIBA_FPCIB0
229static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); 226static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
@@ -239,7 +236,6 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
239 .mask = toshiba_rbtx4927_irq_ioc_disable, 236 .mask = toshiba_rbtx4927_irq_ioc_disable,
240 .mask_ack = toshiba_rbtx4927_irq_ioc_disable, 237 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
241 .unmask = toshiba_rbtx4927_irq_ioc_enable, 238 .unmask = toshiba_rbtx4927_irq_ioc_enable,
242 .end = toshiba_rbtx4927_irq_ioc_end,
243}; 239};
244#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 240#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
245#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 241#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
@@ -388,23 +384,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
388 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 384 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
389} 385}
390 386
391static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
392{
393 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
394 "irq=%d\n", irq);
395
396 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
397 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
398 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
399 "bad irq=%d\n", irq);
400 panic("\n");
401 }
402
403 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
404 toshiba_rbtx4927_irq_ioc_enable(irq);
405 }
406}
407
408 387
409/**********************************************************************************/ 388/**********************************************************************************/
410/* Functions for isa */ 389/* Functions for isa */
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 42e127683ae9..a347b424d91c 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -39,11 +39,9 @@
39 39
40static void tx4938_irq_cp0_enable(unsigned int irq); 40static void tx4938_irq_cp0_enable(unsigned int irq);
41static void tx4938_irq_cp0_disable(unsigned int irq); 41static void tx4938_irq_cp0_disable(unsigned int irq);
42static void tx4938_irq_cp0_end(unsigned int irq);
43 42
44static void tx4938_irq_pic_enable(unsigned int irq); 43static void tx4938_irq_pic_enable(unsigned int irq);
45static void tx4938_irq_pic_disable(unsigned int irq); 44static void tx4938_irq_pic_disable(unsigned int irq);
46static void tx4938_irq_pic_end(unsigned int irq);
47 45
48/**********************************************************************************/ 46/**********************************************************************************/
49/* Kernel structs for all pic's */ 47/* Kernel structs for all pic's */
@@ -56,7 +54,6 @@ static struct irq_chip tx4938_irq_cp0_type = {
56 .mask = tx4938_irq_cp0_disable, 54 .mask = tx4938_irq_cp0_disable,
57 .mask_ack = tx4938_irq_cp0_disable, 55 .mask_ack = tx4938_irq_cp0_disable,
58 .unmask = tx4938_irq_cp0_enable, 56 .unmask = tx4938_irq_cp0_enable,
59 .end = tx4938_irq_cp0_end,
60}; 57};
61 58
62#define TX4938_PIC_NAME "TX4938-PIC" 59#define TX4938_PIC_NAME "TX4938-PIC"
@@ -66,7 +63,6 @@ static struct irq_chip tx4938_irq_pic_type = {
66 .mask = tx4938_irq_pic_disable, 63 .mask = tx4938_irq_pic_disable,
67 .mask_ack = tx4938_irq_pic_disable, 64 .mask_ack = tx4938_irq_pic_disable,
68 .unmask = tx4938_irq_pic_enable, 65 .unmask = tx4938_irq_pic_enable,
69 .end = tx4938_irq_pic_end,
70}; 66};
71 67
72static struct irqaction tx4938_irq_pic_action = { 68static struct irqaction tx4938_irq_pic_action = {
@@ -104,14 +100,6 @@ tx4938_irq_cp0_disable(unsigned int irq)
104 clear_c0_status(tx4938_irq_cp0_mask(irq)); 100 clear_c0_status(tx4938_irq_cp0_mask(irq));
105} 101}
106 102
107static void
108tx4938_irq_cp0_end(unsigned int irq)
109{
110 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
111 tx4938_irq_cp0_enable(irq);
112 }
113}
114
115/**********************************************************************************/ 103/**********************************************************************************/
116/* Functions for pic */ 104/* Functions for pic */
117/**********************************************************************************/ 105/**********************************************************************************/
@@ -269,14 +257,6 @@ tx4938_irq_pic_disable(unsigned int irq)
269 tx4938_irq_pic_mask(irq), 0); 257 tx4938_irq_pic_mask(irq), 0);
270} 258}
271 259
272static void
273tx4938_irq_pic_end(unsigned int irq)
274{
275 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
276 tx4938_irq_pic_enable(irq);
277 }
278}
279
280/**********************************************************************************/ 260/**********************************************************************************/
281/* Main init functions */ 261/* Main init functions */
282/**********************************************************************************/ 262/**********************************************************************************/
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 8c87a35f3068..b6f363d08011 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -89,7 +89,6 @@ IRQ Device
89 89
90static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); 90static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
91static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); 91static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
92static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
93 92
94#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" 93#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
95static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { 94static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
@@ -98,7 +97,6 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
98 .mask = toshiba_rbtx4938_irq_ioc_disable, 97 .mask = toshiba_rbtx4938_irq_ioc_disable,
99 .mask_ack = toshiba_rbtx4938_irq_ioc_disable, 98 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
100 .unmask = toshiba_rbtx4938_irq_ioc_enable, 99 .unmask = toshiba_rbtx4938_irq_ioc_enable,
101 .end = toshiba_rbtx4938_irq_ioc_end,
102}; 100};
103 101
104#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 102#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
@@ -167,14 +165,6 @@ toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
167 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 165 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
168} 166}
169 167
170static void
171toshiba_rbtx4938_irq_ioc_end(unsigned int irq)
172{
173 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
174 toshiba_rbtx4938_irq_ioc_enable(irq);
175 }
176}
177
178extern void __init txx9_spi_irqinit(int irc_irq); 168extern void __init txx9_spi_irqinit(int irc_irq);
179 169
180void __init arch_init_irq(void) 170void __init arch_init_irq(void)
diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig
index 92f41f6f934a..c8dfd8092cab 100644
--- a/arch/mips/vr41xx/Kconfig
+++ b/arch/mips/vr41xx/Kconfig
@@ -6,6 +6,7 @@ config CASIO_E55
6 select ISA 6 select ISA
7 select SYS_SUPPORTS_32BIT_KERNEL 7 select SYS_SUPPORTS_32BIT_KERNEL
8 select SYS_SUPPORTS_LITTLE_ENDIAN 8 select SYS_SUPPORTS_LITTLE_ENDIAN
9 select GENERIC_HARDIRQS_NO__DO_IRQ
9 10
10config IBM_WORKPAD 11config IBM_WORKPAD
11 bool "Support for IBM WorkPad z50" 12 bool "Support for IBM WorkPad z50"
@@ -15,6 +16,7 @@ config IBM_WORKPAD
15 select ISA 16 select ISA
16 select SYS_SUPPORTS_32BIT_KERNEL 17 select SYS_SUPPORTS_32BIT_KERNEL
17 select SYS_SUPPORTS_LITTLE_ENDIAN 18 select SYS_SUPPORTS_LITTLE_ENDIAN
19 select GENERIC_HARDIRQS_NO__DO_IRQ
18 20
19config NEC_CMBVR4133 21config NEC_CMBVR4133
20 bool "Support for NEC CMB-VR4133" 22 bool "Support for NEC CMB-VR4133"
@@ -39,6 +41,7 @@ config TANBAC_TB022X
39 select IRQ_CPU 41 select IRQ_CPU
40 select SYS_SUPPORTS_32BIT_KERNEL 42 select SYS_SUPPORTS_32BIT_KERNEL
41 select SYS_SUPPORTS_LITTLE_ENDIAN 43 select SYS_SUPPORTS_LITTLE_ENDIAN
44 select GENERIC_HARDIRQS_NO__DO_IRQ
42 help 45 help
43 The TANBAC VR4131 multichip module(TB0225) and 46 The TANBAC VR4131 multichip module(TB0225) and
44 the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms 47 the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
@@ -71,6 +74,7 @@ config VICTOR_MPC30X
71 select IRQ_CPU 74 select IRQ_CPU
72 select SYS_SUPPORTS_32BIT_KERNEL 75 select SYS_SUPPORTS_32BIT_KERNEL
73 select SYS_SUPPORTS_LITTLE_ENDIAN 76 select SYS_SUPPORTS_LITTLE_ENDIAN
77 select GENERIC_HARDIRQS_NO__DO_IRQ
74 78
75config ZAO_CAPCELLA 79config ZAO_CAPCELLA
76 bool "Support for ZAO Networks Capcella" 80 bool "Support for ZAO Networks Capcella"
@@ -80,6 +84,7 @@ config ZAO_CAPCELLA
80 select IRQ_CPU 84 select IRQ_CPU
81 select SYS_SUPPORTS_32BIT_KERNEL 85 select SYS_SUPPORTS_32BIT_KERNEL
82 select SYS_SUPPORTS_LITTLE_ENDIAN 86 select SYS_SUPPORTS_LITTLE_ENDIAN
87 select GENERIC_HARDIRQS_NO__DO_IRQ
83 88
84config PCI_VR41XX 89config PCI_VR41XX
85 bool "Add PCI control unit support of NEC VR4100 series" 90 bool "Add PCI control unit support of NEC VR4100 series"
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 54b92a74c7ac..c075261976c5 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -427,19 +427,12 @@ static void enable_sysint1_irq(unsigned int irq)
427 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 427 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
428} 428}
429 429
430static void end_sysint1_irq(unsigned int irq)
431{
432 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
433 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
434}
435
436static struct irq_chip sysint1_irq_type = { 430static struct irq_chip sysint1_irq_type = {
437 .typename = "SYSINT1", 431 .typename = "SYSINT1",
438 .ack = disable_sysint1_irq, 432 .ack = disable_sysint1_irq,
439 .mask = disable_sysint1_irq, 433 .mask = disable_sysint1_irq,
440 .mask_ack = disable_sysint1_irq, 434 .mask_ack = disable_sysint1_irq,
441 .unmask = enable_sysint1_irq, 435 .unmask = enable_sysint1_irq,
442 .end = end_sysint1_irq,
443}; 436};
444 437
445static void disable_sysint2_irq(unsigned int irq) 438static void disable_sysint2_irq(unsigned int irq)
@@ -452,19 +445,12 @@ static void enable_sysint2_irq(unsigned int irq)
452 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 445 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
453} 446}
454 447
455static void end_sysint2_irq(unsigned int irq)
456{
457 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
458 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
459}
460
461static struct irq_chip sysint2_irq_type = { 448static struct irq_chip sysint2_irq_type = {
462 .typename = "SYSINT2", 449 .typename = "SYSINT2",
463 .ack = disable_sysint2_irq, 450 .ack = disable_sysint2_irq,
464 .mask = disable_sysint2_irq, 451 .mask = disable_sysint2_irq,
465 .mask_ack = disable_sysint2_irq, 452 .mask_ack = disable_sysint2_irq,
466 .unmask = enable_sysint2_irq, 453 .unmask = enable_sysint2_irq,
467 .end = end_sysint2_irq,
468}; 454};
469 455
470static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) 456static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)