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-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig66
-rw-r--r--arch/mips/Makefile12
-rw-r--r--arch/mips/alchemy/common/dbdma.c123
-rw-r--r--arch/mips/alchemy/common/dma.c46
-rw-r--r--arch/mips/alchemy/common/irq.c345
-rw-r--r--arch/mips/alchemy/common/platform.c250
-rw-r--r--arch/mips/alchemy/common/setup.c4
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c7
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c61
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c2
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c2
-rw-r--r--arch/mips/alchemy/devboards/prom.c2
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c14
-rw-r--r--arch/mips/alchemy/gpr/init.c2
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c2
-rw-r--r--arch/mips/alchemy/mtx-1/init.c2
-rw-r--r--arch/mips/alchemy/mtx-1/platform.c4
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c11
-rw-r--r--arch/mips/alchemy/xxs1500/init.c7
-rw-r--r--arch/mips/ar7/gpio.c4
-rw-r--r--arch/mips/bcm47xx/nvram.c3
-rw-r--r--arch/mips/bcm47xx/setup.c130
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c16
-rw-r--r--arch/mips/boot/compressed/calc_vmlinuz_load_addr.c2
-rw-r--r--arch/mips/boot/compressed/uart-alchemy.c2
-rw-r--r--arch/mips/cavium-octeon/Kconfig15
-rw-r--r--arch/mips/cavium-octeon/setup.c7
-rw-r--r--arch/mips/cavium-octeon/smp.c17
-rw-r--r--arch/mips/configs/lemote2f_defconfig6
-rw-r--r--arch/mips/configs/malta_defconfig2
-rw-r--r--arch/mips/configs/mtx1_defconfig4
-rw-r--r--arch/mips/configs/nlm_xlr_defconfig574
-rw-r--r--arch/mips/include/asm/cache.h2
-rw-r--r--arch/mips/include/asm/cevt-r4k.h3
-rw-r--r--arch/mips/include/asm/cpu.h27
-rw-r--r--arch/mips/include/asm/dma-mapping.h2
-rw-r--r--arch/mips/include/asm/hugetlb.h1
-rw-r--r--arch/mips/include/asm/jump_label.h22
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h334
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000_dma.h4
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h8
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h122
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/nvram.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h5
-rw-r--r--arch/mips/include/asm/mach-lantiq/lantiq.h63
-rw-r--r--arch/mips/include/asm/mach-lantiq/lantiq_platform.h53
-rw-r--r--arch/mips/include/asm/mach-lantiq/war.h24
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/irq.h18
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h66
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h141
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/xway_dma.h60
-rw-r--r--arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h47
-rw-r--r--arch/mips/include/asm/mach-netlogic/irq.h14
-rw-r--r--arch/mips/include/asm/mach-netlogic/war.h26
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/netlogic/interrupt.h45
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h76
-rw-r--r--arch/mips/include/asm/netlogic/psb-bootinfo.h109
-rw-r--r--arch/mips/include/asm/netlogic/xlr/gpio.h73
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h131
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h231
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h75
-rw-r--r--arch/mips/include/asm/ptrace.h3
-rw-r--r--arch/mips/include/asm/thread_info.h3
-rw-r--r--arch/mips/jazz/jazzdma.c5
-rw-r--r--arch/mips/jz4740/dma.c4
-rw-r--r--arch/mips/jz4740/setup.c32
-rw-r--r--arch/mips/jz4740/time.c2
-rw-r--r--arch/mips/jz4740/timer.c2
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/cpu-probe.c83
-rw-r--r--arch/mips/kernel/entry.S7
-rw-r--r--arch/mips/kernel/ftrace.c5
-rw-r--r--arch/mips/kernel/ptrace.c43
-rw-r--r--arch/mips/kernel/scall32-o32.S5
-rw-r--r--arch/mips/kernel/scall64-64.S5
-rw-r--r--arch/mips/kernel/scall64-n32.S5
-rw-r--r--arch/mips/kernel/scall64-o32.S5
-rw-r--r--arch/mips/kernel/smtc.c2
-rw-r--r--arch/mips/kernel/syscall.c120
-rw-r--r--arch/mips/kernel/traps.c6
-rw-r--r--arch/mips/kernel/vmlinux.lds.S2
-rw-r--r--arch/mips/lantiq/Kconfig23
-rw-r--r--arch/mips/lantiq/Makefile11
-rw-r--r--arch/mips/lantiq/Platform8
-rw-r--r--arch/mips/lantiq/clk.c140
-rw-r--r--arch/mips/lantiq/clk.h18
-rw-r--r--arch/mips/lantiq/devices.c122
-rw-r--r--arch/mips/lantiq/devices.h23
-rw-r--r--arch/mips/lantiq/early_printk.c33
-rw-r--r--arch/mips/lantiq/irq.c326
-rw-r--r--arch/mips/lantiq/machtypes.h20
-rw-r--r--arch/mips/lantiq/prom.c71
-rw-r--r--arch/mips/lantiq/prom.h25
-rw-r--r--arch/mips/lantiq/setup.c66
-rw-r--r--arch/mips/lantiq/xway/Kconfig23
-rw-r--r--arch/mips/lantiq/xway/Makefile7
-rw-r--r--arch/mips/lantiq/xway/clk-ase.c48
-rw-r--r--arch/mips/lantiq/xway/clk-xway.c223
-rw-r--r--arch/mips/lantiq/xway/devices.c121
-rw-r--r--arch/mips/lantiq/xway/devices.h20
-rw-r--r--arch/mips/lantiq/xway/dma.c253
-rw-r--r--arch/mips/lantiq/xway/ebu.c53
-rw-r--r--arch/mips/lantiq/xway/gpio.c195
-rw-r--r--arch/mips/lantiq/xway/gpio_ebu.c126
-rw-r--r--arch/mips/lantiq/xway/gpio_stp.c157
-rw-r--r--arch/mips/lantiq/xway/mach-easy50601.c57
-rw-r--r--arch/mips/lantiq/xway/mach-easy50712.c74
-rw-r--r--arch/mips/lantiq/xway/pmu.c70
-rw-r--r--arch/mips/lantiq/xway/prom-ase.c39
-rw-r--r--arch/mips/lantiq/xway/prom-xway.c54
-rw-r--r--arch/mips/lantiq/xway/reset.c91
-rw-r--r--arch/mips/lantiq/xway/setup-ase.c19
-rw-r--r--arch/mips/lantiq/xway/setup-xway.c20
-rw-r--r--arch/mips/lib/Makefile1
-rw-r--r--arch/mips/loongson/common/env.c5
-rw-r--r--arch/mips/mm/Makefile4
-rw-r--r--arch/mips/mm/c-r4k.c3
-rw-r--r--arch/mips/mm/mmap.c122
-rw-r--r--arch/mips/mm/tlbex.c5
-rw-r--r--arch/mips/mti-malta/malta-init.c14
-rw-r--r--arch/mips/mti-malta/malta-int.c5
-rw-r--r--arch/mips/netlogic/Kconfig5
-rw-r--r--arch/mips/netlogic/xlr/Makefile5
-rw-r--r--arch/mips/netlogic/xlr/irq.c300
-rw-r--r--arch/mips/netlogic/xlr/platform.c98
-rw-r--r--arch/mips/netlogic/xlr/setup.c188
-rw-r--r--arch/mips/netlogic/xlr/smp.c225
-rw-r--r--arch/mips/netlogic/xlr/smpboot.S94
-rw-r--r--arch/mips/netlogic/xlr/time.c51
-rw-r--r--arch/mips/netlogic/xlr/xlr_console.c46
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/ops-lantiq.c116
-rw-r--r--arch/mips/pci/pci-lantiq.c297
-rw-r--r--arch/mips/pci/pci-lantiq.h18
-rw-r--r--arch/mips/pci/pci-xlr.c214
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_per.c2
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c4
-rw-r--r--arch/mips/power/hibernate.S2
-rw-r--r--arch/mips/rb532/gpio.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-platform.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c4
-rw-r--r--arch/mips/sgi-ip27/ip27-hubio.c3
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-klnuma.c3
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c13
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c7
-rw-r--r--arch/mips/sibyte/sb1250/smp.c7
-rw-r--r--arch/mips/sni/time.c4
151 files changed, 7283 insertions, 1011 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 7ff9b5492041..aef6c917b45a 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -11,6 +11,7 @@ platforms += dec
11platforms += emma 11platforms += emma
12platforms += jazz 12platforms += jazz
13platforms += jz4740 13platforms += jz4740
14platforms += lantiq
14platforms += lasat 15platforms += lasat
15platforms += loongson 16platforms += loongson
16platforms += mipssim 17platforms += mipssim
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f7f6419e4c84..cef1a854487d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -212,6 +212,24 @@ config MACH_JZ4740
212 select HAVE_PWM 212 select HAVE_PWM
213 select HAVE_CLK 213 select HAVE_CLK
214 214
215config LANTIQ
216 bool "Lantiq based platforms"
217 select DMA_NONCOHERENT
218 select IRQ_CPU
219 select CEVT_R4K
220 select CSRC_R4K
221 select SYS_HAS_CPU_MIPS32_R1
222 select SYS_HAS_CPU_MIPS32_R2
223 select SYS_SUPPORTS_BIG_ENDIAN
224 select SYS_SUPPORTS_32BIT_KERNEL
225 select SYS_SUPPORTS_MULTITHREADING
226 select SYS_HAS_EARLY_PRINTK
227 select ARCH_REQUIRE_GPIOLIB
228 select SWAP_IO_SPACE
229 select BOOT_RAW
230 select HAVE_CLK
231 select MIPS_MACHINE
232
215config LASAT 233config LASAT
216 bool "LASAT Networks platforms" 234 bool "LASAT Networks platforms"
217 select CEVT_R4K 235 select CEVT_R4K
@@ -736,6 +754,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
736 Hikari 754 Hikari
737 Say Y here for most Octeon reference boards. 755 Say Y here for most Octeon reference boards.
738 756
757config NLM_XLR_BOARD
758 bool "Netlogic XLR/XLS based systems"
759 depends on EXPERIMENTAL
760 select BOOT_ELF32
761 select NLM_COMMON
762 select NLM_XLR
763 select SYS_HAS_CPU_XLR
764 select SYS_SUPPORTS_SMP
765 select HW_HAS_PCI
766 select SWAP_IO_SPACE
767 select SYS_SUPPORTS_32BIT_KERNEL
768 select SYS_SUPPORTS_64BIT_KERNEL
769 select 64BIT_PHYS_ADDR
770 select SYS_SUPPORTS_BIG_ENDIAN
771 select SYS_SUPPORTS_HIGHMEM
772 select DMA_COHERENT
773 select NR_CPUS_DEFAULT_32
774 select CEVT_R4K
775 select CSRC_R4K
776 select IRQ_CPU
777 select ZONE_DMA if 64BIT
778 select SYNC_R4K
779 select SYS_HAS_EARLY_PRINTK
780 help
781 Support for systems based on Netlogic XLR and XLS processors.
782 Say Y here if you have a XLR or XLS based board.
783
739endchoice 784endchoice
740 785
741source "arch/mips/alchemy/Kconfig" 786source "arch/mips/alchemy/Kconfig"
@@ -743,6 +788,7 @@ source "arch/mips/ath79/Kconfig"
743source "arch/mips/bcm63xx/Kconfig" 788source "arch/mips/bcm63xx/Kconfig"
744source "arch/mips/jazz/Kconfig" 789source "arch/mips/jazz/Kconfig"
745source "arch/mips/jz4740/Kconfig" 790source "arch/mips/jz4740/Kconfig"
791source "arch/mips/lantiq/Kconfig"
746source "arch/mips/lasat/Kconfig" 792source "arch/mips/lasat/Kconfig"
747source "arch/mips/pmc-sierra/Kconfig" 793source "arch/mips/pmc-sierra/Kconfig"
748source "arch/mips/powertv/Kconfig" 794source "arch/mips/powertv/Kconfig"
@@ -752,6 +798,7 @@ source "arch/mips/txx9/Kconfig"
752source "arch/mips/vr41xx/Kconfig" 798source "arch/mips/vr41xx/Kconfig"
753source "arch/mips/cavium-octeon/Kconfig" 799source "arch/mips/cavium-octeon/Kconfig"
754source "arch/mips/loongson/Kconfig" 800source "arch/mips/loongson/Kconfig"
801source "arch/mips/netlogic/Kconfig"
755 802
756endmenu 803endmenu
757 804
@@ -997,9 +1044,6 @@ config IRQ_GT641XX
997config IRQ_GIC 1044config IRQ_GIC
998 bool 1045 bool
999 1046
1000config IRQ_CPU_OCTEON
1001 bool
1002
1003config MIPS_BOARDS_GEN 1047config MIPS_BOARDS_GEN
1004 bool 1048 bool
1005 1049
@@ -1359,8 +1403,6 @@ config CPU_SB1
1359config CPU_CAVIUM_OCTEON 1403config CPU_CAVIUM_OCTEON
1360 bool "Cavium Octeon processor" 1404 bool "Cavium Octeon processor"
1361 depends on SYS_HAS_CPU_CAVIUM_OCTEON 1405 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1362 select IRQ_CPU
1363 select IRQ_CPU_OCTEON
1364 select CPU_HAS_PREFETCH 1406 select CPU_HAS_PREFETCH
1365 select CPU_SUPPORTS_64BIT_KERNEL 1407 select CPU_SUPPORTS_64BIT_KERNEL
1366 select SYS_SUPPORTS_SMP 1408 select SYS_SUPPORTS_SMP
@@ -1425,6 +1467,17 @@ config CPU_BMIPS5000
1425 help 1467 help
1426 Broadcom BMIPS5000 processors. 1468 Broadcom BMIPS5000 processors.
1427 1469
1470config CPU_XLR
1471 bool "Netlogic XLR SoC"
1472 depends on SYS_HAS_CPU_XLR
1473 select CPU_SUPPORTS_32BIT_KERNEL
1474 select CPU_SUPPORTS_64BIT_KERNEL
1475 select CPU_SUPPORTS_HIGHMEM
1476 select WEAK_ORDERING
1477 select WEAK_REORDERING_BEYOND_LLSC
1478 select CPU_SUPPORTS_HUGEPAGES
1479 help
1480 Netlogic Microsystems XLR/XLS processors.
1428endchoice 1481endchoice
1429 1482
1430if CPU_LOONGSON2F 1483if CPU_LOONGSON2F
@@ -1555,6 +1608,9 @@ config SYS_HAS_CPU_BMIPS4380
1555config SYS_HAS_CPU_BMIPS5000 1608config SYS_HAS_CPU_BMIPS5000
1556 bool 1609 bool
1557 1610
1611config SYS_HAS_CPU_XLR
1612 bool
1613
1558# 1614#
1559# CPU may reorder R->R, R->W, W->R, W->W 1615# CPU may reorder R->R, R->W, W->R, W->W
1560# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC 1616# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 53e3514ba10e..884819cd0607 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -191,6 +191,18 @@ endif
191# 191#
192include $(srctree)/arch/mips/Kbuild.platforms 192include $(srctree)/arch/mips/Kbuild.platforms
193 193
194#
195# NETLOGIC SOC Common (common)
196#
197cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic
198cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic
199
200#
201# NETLOGIC XLR/XLS SoC, Simulator and boards
202#
203core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/
204load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000
205
194cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 206cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
195drivers-$(CONFIG_PCI) += arch/mips/pci/ 207drivers-$(CONFIG_PCI) += arch/mips/pci/
196 208
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index ca0506a8585a..3a5abb54d505 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -36,7 +36,7 @@
36#include <linux/spinlock.h> 36#include <linux/spinlock.h>
37#include <linux/interrupt.h> 37#include <linux/interrupt.h>
38#include <linux/module.h> 38#include <linux/module.h>
39#include <linux/sysdev.h> 39#include <linux/syscore_ops.h>
40#include <asm/mach-au1x00/au1000.h> 40#include <asm/mach-au1x00/au1000.h>
41#include <asm/mach-au1x00/au1xxx_dbdma.h> 41#include <asm/mach-au1x00/au1xxx_dbdma.h>
42 42
@@ -58,7 +58,8 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
58/* I couldn't find a macro that did this... */ 58/* I couldn't find a macro that did this... */
59#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) 59#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
60 60
61static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; 61static dbdma_global_t *dbdma_gptr =
62 (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
62static int dbdma_initialized; 63static int dbdma_initialized;
63 64
64static dbdev_tab_t dbdev_tab[] = { 65static dbdev_tab_t dbdev_tab[] = {
@@ -299,7 +300,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
299 if (ctp != NULL) { 300 if (ctp != NULL) {
300 memset(ctp, 0, sizeof(chan_tab_t)); 301 memset(ctp, 0, sizeof(chan_tab_t));
301 ctp->chan_index = chan = i; 302 ctp->chan_index = chan = i;
302 dcp = DDMA_CHANNEL_BASE; 303 dcp = KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
303 dcp += (0x0100 * chan); 304 dcp += (0x0100 * chan);
304 ctp->chan_ptr = (au1x_dma_chan_t *)dcp; 305 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
305 cp = (au1x_dma_chan_t *)dcp; 306 cp = (au1x_dma_chan_t *)dcp;
@@ -958,105 +959,75 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
958} 959}
959 960
960 961
961struct alchemy_dbdma_sysdev { 962static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6];
962 struct sys_device sysdev;
963 u32 pm_regs[NUM_DBDMA_CHANS + 1][6];
964};
965 963
966static int alchemy_dbdma_suspend(struct sys_device *dev, 964static int alchemy_dbdma_suspend(void)
967 pm_message_t state)
968{ 965{
969 struct alchemy_dbdma_sysdev *sdev =
970 container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
971 int i; 966 int i;
972 u32 addr; 967 void __iomem *addr;
973 968
974 addr = DDMA_GLOBAL_BASE; 969 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
975 sdev->pm_regs[0][0] = au_readl(addr + 0x00); 970 alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);
976 sdev->pm_regs[0][1] = au_readl(addr + 0x04); 971 alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);
977 sdev->pm_regs[0][2] = au_readl(addr + 0x08); 972 alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);
978 sdev->pm_regs[0][3] = au_readl(addr + 0x0c); 973 alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);
979 974
980 /* save channel configurations */ 975 /* save channel configurations */
981 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { 976 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
982 sdev->pm_regs[i][0] = au_readl(addr + 0x00); 977 for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
983 sdev->pm_regs[i][1] = au_readl(addr + 0x04); 978 alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);
984 sdev->pm_regs[i][2] = au_readl(addr + 0x08); 979 alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);
985 sdev->pm_regs[i][3] = au_readl(addr + 0x0c); 980 alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);
986 sdev->pm_regs[i][4] = au_readl(addr + 0x10); 981 alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);
987 sdev->pm_regs[i][5] = au_readl(addr + 0x14); 982 alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);
983 alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);
988 984
989 /* halt channel */ 985 /* halt channel */
990 au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00); 986 __raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);
991 au_sync(); 987 wmb();
992 while (!(au_readl(addr + 0x14) & 1)) 988 while (!(__raw_readl(addr + 0x14) & 1))
993 au_sync(); 989 wmb();
994 990
995 addr += 0x100; /* next channel base */ 991 addr += 0x100; /* next channel base */
996 } 992 }
997 /* disable channel interrupts */ 993 /* disable channel interrupts */
998 au_writel(0, DDMA_GLOBAL_BASE + 0x0c); 994 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
999 au_sync(); 995 __raw_writel(0, addr + 0x0c);
996 wmb();
1000 997
1001 return 0; 998 return 0;
1002} 999}
1003 1000
1004static int alchemy_dbdma_resume(struct sys_device *dev) 1001static void alchemy_dbdma_resume(void)
1005{ 1002{
1006 struct alchemy_dbdma_sysdev *sdev =
1007 container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
1008 int i; 1003 int i;
1009 u32 addr; 1004 void __iomem *addr;
1010 1005
1011 addr = DDMA_GLOBAL_BASE; 1006 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
1012 au_writel(sdev->pm_regs[0][0], addr + 0x00); 1007 __raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);
1013 au_writel(sdev->pm_regs[0][1], addr + 0x04); 1008 __raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);
1014 au_writel(sdev->pm_regs[0][2], addr + 0x08); 1009 __raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);
1015 au_writel(sdev->pm_regs[0][3], addr + 0x0c); 1010 __raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);
1016 1011
1017 /* restore channel configurations */ 1012 /* restore channel configurations */
1018 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { 1013 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
1019 au_writel(sdev->pm_regs[i][0], addr + 0x00); 1014 for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
1020 au_writel(sdev->pm_regs[i][1], addr + 0x04); 1015 __raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);
1021 au_writel(sdev->pm_regs[i][2], addr + 0x08); 1016 __raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);
1022 au_writel(sdev->pm_regs[i][3], addr + 0x0c); 1017 __raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);
1023 au_writel(sdev->pm_regs[i][4], addr + 0x10); 1018 __raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);
1024 au_writel(sdev->pm_regs[i][5], addr + 0x14); 1019 __raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);
1025 au_sync(); 1020 __raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);
1021 wmb();
1026 addr += 0x100; /* next channel base */ 1022 addr += 0x100; /* next channel base */
1027 } 1023 }
1028
1029 return 0;
1030} 1024}
1031 1025
1032static struct sysdev_class alchemy_dbdma_sysdev_class = { 1026static struct syscore_ops alchemy_dbdma_syscore_ops = {
1033 .name = "dbdma",
1034 .suspend = alchemy_dbdma_suspend, 1027 .suspend = alchemy_dbdma_suspend,
1035 .resume = alchemy_dbdma_resume, 1028 .resume = alchemy_dbdma_resume,
1036}; 1029};
1037 1030
1038static int __init alchemy_dbdma_sysdev_init(void)
1039{
1040 struct alchemy_dbdma_sysdev *sdev;
1041 int ret;
1042
1043 ret = sysdev_class_register(&alchemy_dbdma_sysdev_class);
1044 if (ret)
1045 return ret;
1046
1047 sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL);
1048 if (!sdev)
1049 return -ENOMEM;
1050
1051 sdev->sysdev.id = -1;
1052 sdev->sysdev.cls = &alchemy_dbdma_sysdev_class;
1053 ret = sysdev_register(&sdev->sysdev);
1054 if (ret)
1055 kfree(sdev);
1056
1057 return ret;
1058}
1059
1060static int __init au1xxx_dbdma_init(void) 1031static int __init au1xxx_dbdma_init(void)
1061{ 1032{
1062 int irq_nr, ret; 1033 int irq_nr, ret;
@@ -1084,11 +1055,7 @@ static int __init au1xxx_dbdma_init(void)
1084 else { 1055 else {
1085 dbdma_initialized = 1; 1056 dbdma_initialized = 1;
1086 printk(KERN_INFO "Alchemy DBDMA initialized\n"); 1057 printk(KERN_INFO "Alchemy DBDMA initialized\n");
1087 ret = alchemy_dbdma_sysdev_init(); 1058 register_syscore_ops(&alchemy_dbdma_syscore_ops);
1088 if (ret) {
1089 printk(KERN_ERR "DBDMA PM init failed\n");
1090 ret = 0;
1091 }
1092 } 1059 }
1093 1060
1094 return ret; 1061 return ret;
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index d5278877891d..347980e79a89 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -58,6 +58,9 @@
58 * returned from request_dma. 58 * returned from request_dma.
59 */ 59 */
60 60
61/* DMA Channel register block spacing */
62#define DMA_CHANNEL_LEN 0x00000100
63
61DEFINE_SPINLOCK(au1000_dma_spin_lock); 64DEFINE_SPINLOCK(au1000_dma_spin_lock);
62 65
63struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = { 66struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
@@ -77,22 +80,23 @@ static const struct dma_dev {
77 unsigned int fifo_addr; 80 unsigned int fifo_addr;
78 unsigned int dma_mode; 81 unsigned int dma_mode;
79} dma_dev_table[DMA_NUM_DEV] = { 82} dma_dev_table[DMA_NUM_DEV] = {
80 {UART0_ADDR + UART_TX, 0}, 83 { AU1000_UART0_PHYS_ADDR + 0x04, DMA_DW8 }, /* UART0_TX */
81 {UART0_ADDR + UART_RX, 0}, 84 { AU1000_UART0_PHYS_ADDR + 0x00, DMA_DW8 | DMA_DR }, /* UART0_RX */
82 {0, 0}, 85 { 0, 0 }, /* DMA_REQ0 */
83 {0, 0}, 86 { 0, 0 }, /* DMA_REQ1 */
84 {AC97C_DATA, DMA_DW16 }, /* coherent */ 87 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 }, /* AC97 TX c */
85 {AC97C_DATA, DMA_DR | DMA_DW16 }, /* coherent */ 88 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
86 {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, 89 { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
87 {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, 90 { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
88 {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, 91 { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
89 {USBD_EP0WR, DMA_DW8 | DMA_NC}, 92 { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
90 {USBD_EP2WR, DMA_DW8 | DMA_NC}, 93 { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
91 {USBD_EP3WR, DMA_DW8 | DMA_NC}, 94 { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
92 {USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC}, 95 { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
93 {USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC}, 96 { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
94 {I2S_DATA, DMA_DW32 | DMA_NC}, 97 /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
95 {I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC} 98 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
99 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
96}; 100};
97 101
98int au1000_dma_read_proc(char *buf, char **start, off_t fpos, 102int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
@@ -123,10 +127,10 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
123 127
124/* Device FIFO addresses and default DMA modes - 2nd bank */ 128/* Device FIFO addresses and default DMA modes - 2nd bank */
125static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = { 129static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
126 { SD0_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ 130 { AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
127 { SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 }, /* coherent */ 131 { AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }, /* coherent */
128 { SD1_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ 132 { AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
129 { SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 } /* coherent */ 133 { AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR } /* coherent */
130}; 134};
131 135
132void dump_au1000_dma_channel(unsigned int dmanr) 136void dump_au1000_dma_channel(unsigned int dmanr)
@@ -202,7 +206,7 @@ int request_au1000_dma(int dev_id, const char *dev_str,
202 } 206 }
203 207
204 /* fill it in */ 208 /* fill it in */
205 chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN; 209 chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN;
206 chan->dev_id = dev_id; 210 chan->dev_id = dev_id;
207 chan->dev_str = dev_str; 211 chan->dev_str = dev_str;
208 chan->fifo_addr = dev->fifo_addr; 212 chan->fifo_addr = dev->fifo_addr;
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 55dd7c888517..8b60ba0675e2 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -30,7 +30,7 @@
30#include <linux/interrupt.h> 30#include <linux/interrupt.h>
31#include <linux/irq.h> 31#include <linux/irq.h>
32#include <linux/slab.h> 32#include <linux/slab.h>
33#include <linux/sysdev.h> 33#include <linux/syscore_ops.h>
34 34
35#include <asm/irq_cpu.h> 35#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h> 36#include <asm/mipsregs.h>
@@ -39,6 +39,36 @@
39#include <asm/mach-pb1x00/pb1000.h> 39#include <asm/mach-pb1x00/pb1000.h>
40#endif 40#endif
41 41
42/* Interrupt Controller register offsets */
43#define IC_CFG0RD 0x40
44#define IC_CFG0SET 0x40
45#define IC_CFG0CLR 0x44
46#define IC_CFG1RD 0x48
47#define IC_CFG1SET 0x48
48#define IC_CFG1CLR 0x4C
49#define IC_CFG2RD 0x50
50#define IC_CFG2SET 0x50
51#define IC_CFG2CLR 0x54
52#define IC_REQ0INT 0x54
53#define IC_SRCRD 0x58
54#define IC_SRCSET 0x58
55#define IC_SRCCLR 0x5C
56#define IC_REQ1INT 0x5C
57#define IC_ASSIGNRD 0x60
58#define IC_ASSIGNSET 0x60
59#define IC_ASSIGNCLR 0x64
60#define IC_WAKERD 0x68
61#define IC_WAKESET 0x68
62#define IC_WAKECLR 0x6C
63#define IC_MASKRD 0x70
64#define IC_MASKSET 0x70
65#define IC_MASKCLR 0x74
66#define IC_RISINGRD 0x78
67#define IC_RISINGCLR 0x78
68#define IC_FALLINGRD 0x7C
69#define IC_FALLINGCLR 0x7C
70#define IC_TESTBIT 0x80
71
42static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); 72static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);
43 73
44/* NOTE on interrupt priorities: The original writers of this code said: 74/* NOTE on interrupt priorities: The original writers of this code said:
@@ -221,89 +251,101 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = {
221static void au1x_ic0_unmask(struct irq_data *d) 251static void au1x_ic0_unmask(struct irq_data *d)
222{ 252{
223 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; 253 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
224 au_writel(1 << bit, IC0_MASKSET); 254 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
225 au_writel(1 << bit, IC0_WAKESET); 255
226 au_sync(); 256 __raw_writel(1 << bit, base + IC_MASKSET);
257 __raw_writel(1 << bit, base + IC_WAKESET);
258 wmb();
227} 259}
228 260
229static void au1x_ic1_unmask(struct irq_data *d) 261static void au1x_ic1_unmask(struct irq_data *d)
230{ 262{
231 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; 263 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
232 au_writel(1 << bit, IC1_MASKSET); 264 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
233 au_writel(1 << bit, IC1_WAKESET); 265
266 __raw_writel(1 << bit, base + IC_MASKSET);
267 __raw_writel(1 << bit, base + IC_WAKESET);
234 268
235/* very hacky. does the pb1000 cpld auto-disable this int? 269/* very hacky. does the pb1000 cpld auto-disable this int?
236 * nowhere in the current kernel sources is it disabled. --mlau 270 * nowhere in the current kernel sources is it disabled. --mlau
237 */ 271 */
238#if defined(CONFIG_MIPS_PB1000) 272#if defined(CONFIG_MIPS_PB1000)
239 if (d->irq == AU1000_GPIO15_INT) 273 if (d->irq == AU1000_GPIO15_INT)
240 au_writel(0x4000, PB1000_MDR); /* enable int */ 274 __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
241#endif 275#endif
242 au_sync(); 276 wmb();
243} 277}
244 278
245static void au1x_ic0_mask(struct irq_data *d) 279static void au1x_ic0_mask(struct irq_data *d)
246{ 280{
247 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; 281 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
248 au_writel(1 << bit, IC0_MASKCLR); 282 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
249 au_writel(1 << bit, IC0_WAKECLR); 283
250 au_sync(); 284 __raw_writel(1 << bit, base + IC_MASKCLR);
285 __raw_writel(1 << bit, base + IC_WAKECLR);
286 wmb();
251} 287}
252 288
253static void au1x_ic1_mask(struct irq_data *d) 289static void au1x_ic1_mask(struct irq_data *d)
254{ 290{
255 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; 291 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
256 au_writel(1 << bit, IC1_MASKCLR); 292 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
257 au_writel(1 << bit, IC1_WAKECLR); 293
258 au_sync(); 294 __raw_writel(1 << bit, base + IC_MASKCLR);
295 __raw_writel(1 << bit, base + IC_WAKECLR);
296 wmb();
259} 297}
260 298
261static void au1x_ic0_ack(struct irq_data *d) 299static void au1x_ic0_ack(struct irq_data *d)
262{ 300{
263 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; 301 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
302 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
264 303
265 /* 304 /*
266 * This may assume that we don't get interrupts from 305 * This may assume that we don't get interrupts from
267 * both edges at once, or if we do, that we don't care. 306 * both edges at once, or if we do, that we don't care.
268 */ 307 */
269 au_writel(1 << bit, IC0_FALLINGCLR); 308 __raw_writel(1 << bit, base + IC_FALLINGCLR);
270 au_writel(1 << bit, IC0_RISINGCLR); 309 __raw_writel(1 << bit, base + IC_RISINGCLR);
271 au_sync(); 310 wmb();
272} 311}
273 312
274static void au1x_ic1_ack(struct irq_data *d) 313static void au1x_ic1_ack(struct irq_data *d)
275{ 314{
276 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; 315 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
316 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
277 317
278 /* 318 /*
279 * This may assume that we don't get interrupts from 319 * This may assume that we don't get interrupts from
280 * both edges at once, or if we do, that we don't care. 320 * both edges at once, or if we do, that we don't care.
281 */ 321 */
282 au_writel(1 << bit, IC1_FALLINGCLR); 322 __raw_writel(1 << bit, base + IC_FALLINGCLR);
283 au_writel(1 << bit, IC1_RISINGCLR); 323 __raw_writel(1 << bit, base + IC_RISINGCLR);
284 au_sync(); 324 wmb();
285} 325}
286 326
287static void au1x_ic0_maskack(struct irq_data *d) 327static void au1x_ic0_maskack(struct irq_data *d)
288{ 328{
289 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; 329 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
330 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
290 331
291 au_writel(1 << bit, IC0_WAKECLR); 332 __raw_writel(1 << bit, base + IC_WAKECLR);
292 au_writel(1 << bit, IC0_MASKCLR); 333 __raw_writel(1 << bit, base + IC_MASKCLR);
293 au_writel(1 << bit, IC0_RISINGCLR); 334 __raw_writel(1 << bit, base + IC_RISINGCLR);
294 au_writel(1 << bit, IC0_FALLINGCLR); 335 __raw_writel(1 << bit, base + IC_FALLINGCLR);
295 au_sync(); 336 wmb();
296} 337}
297 338
298static void au1x_ic1_maskack(struct irq_data *d) 339static void au1x_ic1_maskack(struct irq_data *d)
299{ 340{
300 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; 341 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
342 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
301 343
302 au_writel(1 << bit, IC1_WAKECLR); 344 __raw_writel(1 << bit, base + IC_WAKECLR);
303 au_writel(1 << bit, IC1_MASKCLR); 345 __raw_writel(1 << bit, base + IC_MASKCLR);
304 au_writel(1 << bit, IC1_RISINGCLR); 346 __raw_writel(1 << bit, base + IC_RISINGCLR);
305 au_writel(1 << bit, IC1_FALLINGCLR); 347 __raw_writel(1 << bit, base + IC_FALLINGCLR);
306 au_sync(); 348 wmb();
307} 349}
308 350
309static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) 351static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)
@@ -318,13 +360,13 @@ static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)
318 return -EINVAL; 360 return -EINVAL;
319 361
320 local_irq_save(flags); 362 local_irq_save(flags);
321 wakemsk = au_readl(SYS_WAKEMSK); 363 wakemsk = __raw_readl((void __iomem *)SYS_WAKEMSK);
322 if (on) 364 if (on)
323 wakemsk |= 1 << bit; 365 wakemsk |= 1 << bit;
324 else 366 else
325 wakemsk &= ~(1 << bit); 367 wakemsk &= ~(1 << bit);
326 au_writel(wakemsk, SYS_WAKEMSK); 368 __raw_writel(wakemsk, (void __iomem *)SYS_WAKEMSK);
327 au_sync(); 369 wmb();
328 local_irq_restore(flags); 370 local_irq_restore(flags);
329 371
330 return 0; 372 return 0;
@@ -356,81 +398,74 @@ static struct irq_chip au1x_ic1_chip = {
356static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type) 398static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
357{ 399{
358 struct irq_chip *chip; 400 struct irq_chip *chip;
359 unsigned long icr[6]; 401 unsigned int bit, irq = d->irq;
360 unsigned int bit, ic, irq = d->irq;
361 irq_flow_handler_t handler = NULL; 402 irq_flow_handler_t handler = NULL;
362 unsigned char *name = NULL; 403 unsigned char *name = NULL;
404 void __iomem *base;
363 int ret; 405 int ret;
364 406
365 if (irq >= AU1000_INTC1_INT_BASE) { 407 if (irq >= AU1000_INTC1_INT_BASE) {
366 bit = irq - AU1000_INTC1_INT_BASE; 408 bit = irq - AU1000_INTC1_INT_BASE;
367 chip = &au1x_ic1_chip; 409 chip = &au1x_ic1_chip;
368 ic = 1; 410 base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
369 } else { 411 } else {
370 bit = irq - AU1000_INTC0_INT_BASE; 412 bit = irq - AU1000_INTC0_INT_BASE;
371 chip = &au1x_ic0_chip; 413 chip = &au1x_ic0_chip;
372 ic = 0; 414 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
373 } 415 }
374 416
375 if (bit > 31) 417 if (bit > 31)
376 return -EINVAL; 418 return -EINVAL;
377 419
378 icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
379 icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
380 icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
381 icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
382 icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
383 icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
384
385 ret = 0; 420 ret = 0;
386 421
387 switch (flow_type) { /* cfgregs 2:1:0 */ 422 switch (flow_type) { /* cfgregs 2:1:0 */
388 case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */ 423 case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */
389 au_writel(1 << bit, icr[5]); 424 __raw_writel(1 << bit, base + IC_CFG2CLR);
390 au_writel(1 << bit, icr[4]); 425 __raw_writel(1 << bit, base + IC_CFG1CLR);
391 au_writel(1 << bit, icr[0]); 426 __raw_writel(1 << bit, base + IC_CFG0SET);
392 handler = handle_edge_irq; 427 handler = handle_edge_irq;
393 name = "riseedge"; 428 name = "riseedge";
394 break; 429 break;
395 case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ 430 case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */
396 au_writel(1 << bit, icr[5]); 431 __raw_writel(1 << bit, base + IC_CFG2CLR);
397 au_writel(1 << bit, icr[1]); 432 __raw_writel(1 << bit, base + IC_CFG1SET);
398 au_writel(1 << bit, icr[3]); 433 __raw_writel(1 << bit, base + IC_CFG0CLR);
399 handler = handle_edge_irq; 434 handler = handle_edge_irq;
400 name = "falledge"; 435 name = "falledge";
401 break; 436 break;
402 case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ 437 case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */
403 au_writel(1 << bit, icr[5]); 438 __raw_writel(1 << bit, base + IC_CFG2CLR);
404 au_writel(1 << bit, icr[1]); 439 __raw_writel(1 << bit, base + IC_CFG1SET);
405 au_writel(1 << bit, icr[0]); 440 __raw_writel(1 << bit, base + IC_CFG0SET);
406 handler = handle_edge_irq; 441 handler = handle_edge_irq;
407 name = "bothedge"; 442 name = "bothedge";
408 break; 443 break;
409 case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ 444 case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */
410 au_writel(1 << bit, icr[2]); 445 __raw_writel(1 << bit, base + IC_CFG2SET);
411 au_writel(1 << bit, icr[4]); 446 __raw_writel(1 << bit, base + IC_CFG1CLR);
412 au_writel(1 << bit, icr[0]); 447 __raw_writel(1 << bit, base + IC_CFG0SET);
413 handler = handle_level_irq; 448 handler = handle_level_irq;
414 name = "hilevel"; 449 name = "hilevel";
415 break; 450 break;
416 case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ 451 case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */
417 au_writel(1 << bit, icr[2]); 452 __raw_writel(1 << bit, base + IC_CFG2SET);
418 au_writel(1 << bit, icr[1]); 453 __raw_writel(1 << bit, base + IC_CFG1SET);
419 au_writel(1 << bit, icr[3]); 454 __raw_writel(1 << bit, base + IC_CFG0CLR);
420 handler = handle_level_irq; 455 handler = handle_level_irq;
421 name = "lowlevel"; 456 name = "lowlevel";
422 break; 457 break;
423 case IRQ_TYPE_NONE: /* 0:0:0 */ 458 case IRQ_TYPE_NONE: /* 0:0:0 */
424 au_writel(1 << bit, icr[5]); 459 __raw_writel(1 << bit, base + IC_CFG2CLR);
425 au_writel(1 << bit, icr[4]); 460 __raw_writel(1 << bit, base + IC_CFG1CLR);
426 au_writel(1 << bit, icr[3]); 461 __raw_writel(1 << bit, base + IC_CFG0CLR);
427 break; 462 break;
428 default: 463 default:
429 ret = -EINVAL; 464 ret = -EINVAL;
430 } 465 }
431 __irq_set_chip_handler_name_locked(d->irq, chip, handler, name); 466 __irq_set_chip_handler_name_locked(d->irq, chip, handler, name);
432 467
433 au_sync(); 468 wmb();
434 469
435 return ret; 470 return ret;
436} 471}
@@ -444,21 +479,21 @@ asmlinkage void plat_irq_dispatch(void)
444 off = MIPS_CPU_IRQ_BASE + 7; 479 off = MIPS_CPU_IRQ_BASE + 7;
445 goto handle; 480 goto handle;
446 } else if (pending & CAUSEF_IP2) { 481 } else if (pending & CAUSEF_IP2) {
447 s = IC0_REQ0INT; 482 s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT;
448 off = AU1000_INTC0_INT_BASE; 483 off = AU1000_INTC0_INT_BASE;
449 } else if (pending & CAUSEF_IP3) { 484 } else if (pending & CAUSEF_IP3) {
450 s = IC0_REQ1INT; 485 s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT;
451 off = AU1000_INTC0_INT_BASE; 486 off = AU1000_INTC0_INT_BASE;
452 } else if (pending & CAUSEF_IP4) { 487 } else if (pending & CAUSEF_IP4) {
453 s = IC1_REQ0INT; 488 s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT;
454 off = AU1000_INTC1_INT_BASE; 489 off = AU1000_INTC1_INT_BASE;
455 } else if (pending & CAUSEF_IP5) { 490 } else if (pending & CAUSEF_IP5) {
456 s = IC1_REQ1INT; 491 s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT;
457 off = AU1000_INTC1_INT_BASE; 492 off = AU1000_INTC1_INT_BASE;
458 } else 493 } else
459 goto spurious; 494 goto spurious;
460 495
461 s = au_readl(s); 496 s = __raw_readl((void __iomem *)s);
462 if (unlikely(!s)) { 497 if (unlikely(!s)) {
463spurious: 498spurious:
464 spurious_interrupt(); 499 spurious_interrupt();
@@ -469,48 +504,42 @@ handle:
469 do_IRQ(off); 504 do_IRQ(off);
470} 505}
471 506
507
508static inline void ic_init(void __iomem *base)
509{
510 /* initialize interrupt controller to a safe state */
511 __raw_writel(0xffffffff, base + IC_CFG0CLR);
512 __raw_writel(0xffffffff, base + IC_CFG1CLR);
513 __raw_writel(0xffffffff, base + IC_CFG2CLR);
514 __raw_writel(0xffffffff, base + IC_MASKCLR);
515 __raw_writel(0xffffffff, base + IC_ASSIGNCLR);
516 __raw_writel(0xffffffff, base + IC_WAKECLR);
517 __raw_writel(0xffffffff, base + IC_SRCSET);
518 __raw_writel(0xffffffff, base + IC_FALLINGCLR);
519 __raw_writel(0xffffffff, base + IC_RISINGCLR);
520 __raw_writel(0x00000000, base + IC_TESTBIT);
521 wmb();
522}
523
472static void __init au1000_init_irq(struct au1xxx_irqmap *map) 524static void __init au1000_init_irq(struct au1xxx_irqmap *map)
473{ 525{
474 unsigned int bit, irq_nr; 526 unsigned int bit, irq_nr;
475 int i; 527 void __iomem *base;
476
477 /*
478 * Initialize interrupt controllers to a safe state.
479 */
480 au_writel(0xffffffff, IC0_CFG0CLR);
481 au_writel(0xffffffff, IC0_CFG1CLR);
482 au_writel(0xffffffff, IC0_CFG2CLR);
483 au_writel(0xffffffff, IC0_MASKCLR);
484 au_writel(0xffffffff, IC0_ASSIGNCLR);
485 au_writel(0xffffffff, IC0_WAKECLR);
486 au_writel(0xffffffff, IC0_SRCSET);
487 au_writel(0xffffffff, IC0_FALLINGCLR);
488 au_writel(0xffffffff, IC0_RISINGCLR);
489 au_writel(0x00000000, IC0_TESTBIT);
490
491 au_writel(0xffffffff, IC1_CFG0CLR);
492 au_writel(0xffffffff, IC1_CFG1CLR);
493 au_writel(0xffffffff, IC1_CFG2CLR);
494 au_writel(0xffffffff, IC1_MASKCLR);
495 au_writel(0xffffffff, IC1_ASSIGNCLR);
496 au_writel(0xffffffff, IC1_WAKECLR);
497 au_writel(0xffffffff, IC1_SRCSET);
498 au_writel(0xffffffff, IC1_FALLINGCLR);
499 au_writel(0xffffffff, IC1_RISINGCLR);
500 au_writel(0x00000000, IC1_TESTBIT);
501 528
529 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));
530 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));
502 mips_cpu_irq_init(); 531 mips_cpu_irq_init();
503 532
504 /* register all 64 possible IC0+IC1 irq sources as type "none". 533 /* register all 64 possible IC0+IC1 irq sources as type "none".
505 * Use set_irq_type() to set edge/level behaviour at runtime. 534 * Use set_irq_type() to set edge/level behaviour at runtime.
506 */ 535 */
507 for (i = AU1000_INTC0_INT_BASE; 536 for (irq_nr = AU1000_INTC0_INT_BASE;
508 (i < AU1000_INTC0_INT_BASE + 32); i++) 537 (irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++)
509 au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); 538 au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE);
510 539
511 for (i = AU1000_INTC1_INT_BASE; 540 for (irq_nr = AU1000_INTC1_INT_BASE;
512 (i < AU1000_INTC1_INT_BASE + 32); i++) 541 (irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++)
513 au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); 542 au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE);
514 543
515 /* 544 /*
516 * Initialize IC0, which is fixed per processor. 545 * Initialize IC0, which is fixed per processor.
@@ -520,13 +549,13 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
520 549
521 if (irq_nr >= AU1000_INTC1_INT_BASE) { 550 if (irq_nr >= AU1000_INTC1_INT_BASE) {
522 bit = irq_nr - AU1000_INTC1_INT_BASE; 551 bit = irq_nr - AU1000_INTC1_INT_BASE;
523 if (map->im_request) 552 base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
524 au_writel(1 << bit, IC1_ASSIGNSET);
525 } else { 553 } else {
526 bit = irq_nr - AU1000_INTC0_INT_BASE; 554 bit = irq_nr - AU1000_INTC0_INT_BASE;
527 if (map->im_request) 555 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
528 au_writel(1 << bit, IC0_ASSIGNSET);
529 } 556 }
557 if (map->im_request)
558 __raw_writel(1 << bit, base + IC_ASSIGNSET);
530 559
531 au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); 560 au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type);
532 ++map; 561 ++map;
@@ -556,90 +585,62 @@ void __init arch_init_irq(void)
556 } 585 }
557} 586}
558 587
559struct alchemy_ic_sysdev {
560 struct sys_device sysdev;
561 void __iomem *base;
562 unsigned long pmdata[7];
563};
564 588
565static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state) 589static unsigned long alchemy_ic_pmdata[7 * 2];
566{
567 struct alchemy_ic_sysdev *icdev =
568 container_of(dev, struct alchemy_ic_sysdev, sysdev);
569 590
570 icdev->pmdata[0] = __raw_readl(icdev->base + IC_CFG0RD); 591static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
571 icdev->pmdata[1] = __raw_readl(icdev->base + IC_CFG1RD); 592{
572 icdev->pmdata[2] = __raw_readl(icdev->base + IC_CFG2RD); 593 d[0] = __raw_readl(base + IC_CFG0RD);
573 icdev->pmdata[3] = __raw_readl(icdev->base + IC_SRCRD); 594 d[1] = __raw_readl(base + IC_CFG1RD);
574 icdev->pmdata[4] = __raw_readl(icdev->base + IC_ASSIGNRD); 595 d[2] = __raw_readl(base + IC_CFG2RD);
575 icdev->pmdata[5] = __raw_readl(icdev->base + IC_WAKERD); 596 d[3] = __raw_readl(base + IC_SRCRD);
576 icdev->pmdata[6] = __raw_readl(icdev->base + IC_MASKRD); 597 d[4] = __raw_readl(base + IC_ASSIGNRD);
577 598 d[5] = __raw_readl(base + IC_WAKERD);
578 return 0; 599 d[6] = __raw_readl(base + IC_MASKRD);
600 ic_init(base); /* shut it up too while at it */
579} 601}
580 602
581static int alchemy_ic_resume(struct sys_device *dev) 603static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
582{ 604{
583 struct alchemy_ic_sysdev *icdev = 605 ic_init(base);
584 container_of(dev, struct alchemy_ic_sysdev, sysdev); 606
585 607 __raw_writel(d[0], base + IC_CFG0SET);
586 __raw_writel(0xffffffff, icdev->base + IC_MASKCLR); 608 __raw_writel(d[1], base + IC_CFG1SET);
587 __raw_writel(0xffffffff, icdev->base + IC_CFG0CLR); 609 __raw_writel(d[2], base + IC_CFG2SET);
588 __raw_writel(0xffffffff, icdev->base + IC_CFG1CLR); 610 __raw_writel(d[3], base + IC_SRCSET);
589 __raw_writel(0xffffffff, icdev->base + IC_CFG2CLR); 611 __raw_writel(d[4], base + IC_ASSIGNSET);
590 __raw_writel(0xffffffff, icdev->base + IC_SRCCLR); 612 __raw_writel(d[5], base + IC_WAKESET);
591 __raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR);
592 __raw_writel(0xffffffff, icdev->base + IC_WAKECLR);
593 __raw_writel(0xffffffff, icdev->base + IC_RISINGCLR);
594 __raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR);
595 __raw_writel(0x00000000, icdev->base + IC_TESTBIT);
596 wmb();
597 __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET);
598 __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET);
599 __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET);
600 __raw_writel(icdev->pmdata[3], icdev->base + IC_SRCSET);
601 __raw_writel(icdev->pmdata[4], icdev->base + IC_ASSIGNSET);
602 __raw_writel(icdev->pmdata[5], icdev->base + IC_WAKESET);
603 wmb(); 613 wmb();
604 614
605 __raw_writel(icdev->pmdata[6], icdev->base + IC_MASKSET); 615 __raw_writel(d[6], base + IC_MASKSET);
606 wmb(); 616 wmb();
617}
607 618
619static int alchemy_ic_suspend(void)
620{
621 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
622 alchemy_ic_pmdata);
623 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
624 &alchemy_ic_pmdata[7]);
608 return 0; 625 return 0;
609} 626}
610 627
611static struct sysdev_class alchemy_ic_sysdev_class = { 628static void alchemy_ic_resume(void)
612 .name = "ic", 629{
630 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
631 &alchemy_ic_pmdata[7]);
632 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
633 alchemy_ic_pmdata);
634}
635
636static struct syscore_ops alchemy_ic_syscore_ops = {
613 .suspend = alchemy_ic_suspend, 637 .suspend = alchemy_ic_suspend,
614 .resume = alchemy_ic_resume, 638 .resume = alchemy_ic_resume,
615}; 639};
616 640
617static int __init alchemy_ic_sysdev_init(void) 641static int __init alchemy_ic_pm_init(void)
618{ 642{
619 struct alchemy_ic_sysdev *icdev; 643 register_syscore_ops(&alchemy_ic_syscore_ops);
620 unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR };
621 int err, i;
622
623 err = sysdev_class_register(&alchemy_ic_sysdev_class);
624 if (err)
625 return err;
626
627 for (i = 0; i < 2; i++) {
628 icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL);
629 if (!icdev)
630 return -ENOMEM;
631
632 icdev->base = ioremap(icbase[i], 0x1000);
633
634 icdev->sysdev.id = i;
635 icdev->sysdev.cls = &alchemy_ic_sysdev_class;
636 err = sysdev_register(&icdev->sysdev);
637 if (err) {
638 kfree(icdev);
639 return err;
640 }
641 }
642
643 return 0; 644 return 0;
644} 645}
645device_initcall(alchemy_ic_sysdev_init); 646device_initcall(alchemy_ic_pm_init);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 9e7814db3d03..3b2c18b14341 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -13,9 +13,10 @@
13 13
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/etherdevice.h> 15#include <linux/etherdevice.h>
16#include <linux/init.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
17#include <linux/serial_8250.h> 18#include <linux/serial_8250.h>
18#include <linux/init.h> 19#include <linux/slab.h>
19 20
20#include <asm/mach-au1x00/au1xxx.h> 21#include <asm/mach-au1x00/au1xxx.h>
21#include <asm/mach-au1x00/au1xxx_dbdma.h> 22#include <asm/mach-au1x00/au1xxx_dbdma.h>
@@ -30,21 +31,12 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
30#ifdef CONFIG_SERIAL_8250 31#ifdef CONFIG_SERIAL_8250
31 switch (state) { 32 switch (state) {
32 case 0: 33 case 0:
33 if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { 34 alchemy_uart_enable(CPHYSADDR(port->membase));
34 /* power-on sequence as suggested in the databooks */
35 __raw_writel(0, port->membase + UART_MOD_CNTRL);
36 wmb();
37 __raw_writel(1, port->membase + UART_MOD_CNTRL);
38 wmb();
39 }
40 __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */
41 wmb();
42 serial8250_do_pm(port, state, old_state); 35 serial8250_do_pm(port, state, old_state);
43 break; 36 break;
44 case 3: /* power off */ 37 case 3: /* power off */
45 serial8250_do_pm(port, state, old_state); 38 serial8250_do_pm(port, state, old_state);
46 __raw_writel(0, port->membase + UART_MOD_CNTRL); 39 alchemy_uart_disable(CPHYSADDR(port->membase));
47 wmb();
48 break; 40 break;
49 default: 41 default:
50 serial8250_do_pm(port, state, old_state); 42 serial8250_do_pm(port, state, old_state);
@@ -65,38 +57,60 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
65 .pm = alchemy_8250_pm, \ 57 .pm = alchemy_8250_pm, \
66 } 58 }
67 59
68static struct plat_serial8250_port au1x00_uart_data[] = { 60static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
69#if defined(CONFIG_SOC_AU1000) 61 [ALCHEMY_CPU_AU1000] = {
70 PORT(UART0_PHYS_ADDR, AU1000_UART0_INT), 62 PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
71 PORT(UART1_PHYS_ADDR, AU1000_UART1_INT), 63 PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
72 PORT(UART2_PHYS_ADDR, AU1000_UART2_INT), 64 PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
73 PORT(UART3_PHYS_ADDR, AU1000_UART3_INT), 65 PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
74#elif defined(CONFIG_SOC_AU1500) 66 },
75 PORT(UART0_PHYS_ADDR, AU1500_UART0_INT), 67 [ALCHEMY_CPU_AU1500] = {
76 PORT(UART3_PHYS_ADDR, AU1500_UART3_INT), 68 PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
77#elif defined(CONFIG_SOC_AU1100) 69 PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
78 PORT(UART0_PHYS_ADDR, AU1100_UART0_INT), 70 },
79 PORT(UART1_PHYS_ADDR, AU1100_UART1_INT), 71 [ALCHEMY_CPU_AU1100] = {
80 PORT(UART3_PHYS_ADDR, AU1100_UART3_INT), 72 PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
81#elif defined(CONFIG_SOC_AU1550) 73 PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
82 PORT(UART0_PHYS_ADDR, AU1550_UART0_INT), 74 PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
83 PORT(UART1_PHYS_ADDR, AU1550_UART1_INT), 75 },
84 PORT(UART3_PHYS_ADDR, AU1550_UART3_INT), 76 [ALCHEMY_CPU_AU1550] = {
85#elif defined(CONFIG_SOC_AU1200) 77 PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
86 PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), 78 PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
87 PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), 79 PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
88#endif 80 },
89 { }, 81 [ALCHEMY_CPU_AU1200] = {
82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
84 },
90}; 85};
91 86
92static struct platform_device au1xx0_uart_device = { 87static struct platform_device au1xx0_uart_device = {
93 .name = "serial8250", 88 .name = "serial8250",
94 .id = PLAT8250_DEV_AU1X00, 89 .id = PLAT8250_DEV_AU1X00,
95 .dev = {
96 .platform_data = au1x00_uart_data,
97 },
98}; 90};
99 91
92static void __init alchemy_setup_uarts(int ctype)
93{
94 unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
95 int s = sizeof(struct plat_serial8250_port);
96 int c = alchemy_get_uarts(ctype);
97 struct plat_serial8250_port *ports;
98
99 ports = kzalloc(s * (c + 1), GFP_KERNEL);
100 if (!ports) {
101 printk(KERN_INFO "Alchemy: no memory for UART data\n");
102 return;
103 }
104 memcpy(ports, au1x00_uart_data[ctype], s * c);
105 au1xx0_uart_device.dev.platform_data = ports;
106
107 /* Fill up uartclk. */
108 for (s = 0; s < c; s++)
109 ports[s].uartclk = uartclk;
110 if (platform_device_register(&au1xx0_uart_device))
111 printk(KERN_INFO "Alchemy: failed to register UARTs\n");
112}
113
100/* OHCI (USB full speed host controller) */ 114/* OHCI (USB full speed host controller) */
101static struct resource au1xxx_usb_ohci_resources[] = { 115static struct resource au1xxx_usb_ohci_resources[] = {
102 [0] = { 116 [0] = {
@@ -269,8 +283,8 @@ extern struct au1xmmc_platform_data au1xmmc_platdata[2];
269 283
270static struct resource au1200_mmc0_resources[] = { 284static struct resource au1200_mmc0_resources[] = {
271 [0] = { 285 [0] = {
272 .start = SD0_PHYS_ADDR, 286 .start = AU1100_SD0_PHYS_ADDR,
273 .end = SD0_PHYS_ADDR + 0x7ffff, 287 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
274 .flags = IORESOURCE_MEM, 288 .flags = IORESOURCE_MEM,
275 }, 289 },
276 [1] = { 290 [1] = {
@@ -305,8 +319,8 @@ static struct platform_device au1200_mmc0_device = {
305#ifndef CONFIG_MIPS_DB1200 319#ifndef CONFIG_MIPS_DB1200
306static struct resource au1200_mmc1_resources[] = { 320static struct resource au1200_mmc1_resources[] = {
307 [0] = { 321 [0] = {
308 .start = SD1_PHYS_ADDR, 322 .start = AU1100_SD1_PHYS_ADDR,
309 .end = SD1_PHYS_ADDR + 0x7ffff, 323 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
310 .flags = IORESOURCE_MEM, 324 .flags = IORESOURCE_MEM,
311 }, 325 },
312 [1] = { 326 [1] = {
@@ -359,15 +373,16 @@ static struct platform_device pbdb_smbus_device = {
359#endif 373#endif
360 374
361/* Macro to help defining the Ethernet MAC resources */ 375/* Macro to help defining the Ethernet MAC resources */
376#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */
362#define MAC_RES(_base, _enable, _irq) \ 377#define MAC_RES(_base, _enable, _irq) \
363 { \ 378 { \
364 .start = CPHYSADDR(_base), \ 379 .start = _base, \
365 .end = CPHYSADDR(_base + 0xffff), \ 380 .end = _base + 0xffff, \
366 .flags = IORESOURCE_MEM, \ 381 .flags = IORESOURCE_MEM, \
367 }, \ 382 }, \
368 { \ 383 { \
369 .start = CPHYSADDR(_enable), \ 384 .start = _enable, \
370 .end = CPHYSADDR(_enable + 0x3), \ 385 .end = _enable + 0x3, \
371 .flags = IORESOURCE_MEM, \ 386 .flags = IORESOURCE_MEM, \
372 }, \ 387 }, \
373 { \ 388 { \
@@ -376,19 +391,29 @@ static struct platform_device pbdb_smbus_device = {
376 .flags = IORESOURCE_IRQ \ 391 .flags = IORESOURCE_IRQ \
377 } 392 }
378 393
379static struct resource au1xxx_eth0_resources[] = { 394static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
380#if defined(CONFIG_SOC_AU1000) 395 [ALCHEMY_CPU_AU1000] = {
381 MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), 396 MAC_RES(AU1000_MAC0_PHYS_ADDR,
382#elif defined(CONFIG_SOC_AU1100) 397 AU1000_MACEN_PHYS_ADDR,
383 MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), 398 AU1000_MAC0_DMA_INT)
384#elif defined(CONFIG_SOC_AU1550) 399 },
385 MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), 400 [ALCHEMY_CPU_AU1500] = {
386#elif defined(CONFIG_SOC_AU1500) 401 MAC_RES(AU1500_MAC0_PHYS_ADDR,
387 MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), 402 AU1500_MACEN_PHYS_ADDR,
388#endif 403 AU1500_MAC0_DMA_INT)
404 },
405 [ALCHEMY_CPU_AU1100] = {
406 MAC_RES(AU1000_MAC0_PHYS_ADDR,
407 AU1000_MACEN_PHYS_ADDR,
408 AU1100_MAC0_DMA_INT)
409 },
410 [ALCHEMY_CPU_AU1550] = {
411 MAC_RES(AU1000_MAC0_PHYS_ADDR,
412 AU1000_MACEN_PHYS_ADDR,
413 AU1550_MAC0_DMA_INT)
414 },
389}; 415};
390 416
391
392static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { 417static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
393 .phy1_search_mac0 = 1, 418 .phy1_search_mac0 = 1,
394}; 419};
@@ -396,20 +421,26 @@ static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
396static struct platform_device au1xxx_eth0_device = { 421static struct platform_device au1xxx_eth0_device = {
397 .name = "au1000-eth", 422 .name = "au1000-eth",
398 .id = 0, 423 .id = 0,
399 .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), 424 .num_resources = MAC_RES_COUNT,
400 .resource = au1xxx_eth0_resources,
401 .dev.platform_data = &au1xxx_eth0_platform_data, 425 .dev.platform_data = &au1xxx_eth0_platform_data,
402}; 426};
403 427
404#ifndef CONFIG_SOC_AU1100 428static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
405static struct resource au1xxx_eth1_resources[] = { 429 [ALCHEMY_CPU_AU1000] = {
406#if defined(CONFIG_SOC_AU1000) 430 MAC_RES(AU1000_MAC1_PHYS_ADDR,
407 MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), 431 AU1000_MACEN_PHYS_ADDR + 4,
408#elif defined(CONFIG_SOC_AU1550) 432 AU1000_MAC1_DMA_INT)
409 MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), 433 },
410#elif defined(CONFIG_SOC_AU1500) 434 [ALCHEMY_CPU_AU1500] = {
411 MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), 435 MAC_RES(AU1500_MAC1_PHYS_ADDR,
412#endif 436 AU1500_MACEN_PHYS_ADDR + 4,
437 AU1500_MAC1_DMA_INT)
438 },
439 [ALCHEMY_CPU_AU1550] = {
440 MAC_RES(AU1000_MAC1_PHYS_ADDR,
441 AU1000_MACEN_PHYS_ADDR + 4,
442 AU1550_MAC1_DMA_INT)
443 },
413}; 444};
414 445
415static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { 446static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
@@ -419,11 +450,9 @@ static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
419static struct platform_device au1xxx_eth1_device = { 450static struct platform_device au1xxx_eth1_device = {
420 .name = "au1000-eth", 451 .name = "au1000-eth",
421 .id = 1, 452 .id = 1,
422 .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), 453 .num_resources = MAC_RES_COUNT,
423 .resource = au1xxx_eth1_resources,
424 .dev.platform_data = &au1xxx_eth1_platform_data, 454 .dev.platform_data = &au1xxx_eth1_platform_data,
425}; 455};
426#endif
427 456
428void __init au1xxx_override_eth_cfg(unsigned int port, 457void __init au1xxx_override_eth_cfg(unsigned int port,
429 struct au1000_eth_platform_data *eth_data) 458 struct au1000_eth_platform_data *eth_data)
@@ -434,15 +463,65 @@ void __init au1xxx_override_eth_cfg(unsigned int port,
434 if (port == 0) 463 if (port == 0)
435 memcpy(&au1xxx_eth0_platform_data, eth_data, 464 memcpy(&au1xxx_eth0_platform_data, eth_data,
436 sizeof(struct au1000_eth_platform_data)); 465 sizeof(struct au1000_eth_platform_data));
437#ifndef CONFIG_SOC_AU1100
438 else 466 else
439 memcpy(&au1xxx_eth1_platform_data, eth_data, 467 memcpy(&au1xxx_eth1_platform_data, eth_data,
440 sizeof(struct au1000_eth_platform_data)); 468 sizeof(struct au1000_eth_platform_data));
441#endif 469}
470
471static void __init alchemy_setup_macs(int ctype)
472{
473 int ret, i;
474 unsigned char ethaddr[6];
475 struct resource *macres;
476
477 /* Handle 1st MAC */
478 if (alchemy_get_macs(ctype) < 1)
479 return;
480
481 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
482 if (!macres) {
483 printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
484 return;
485 }
486 memcpy(macres, au1xxx_eth0_resources[ctype],
487 sizeof(struct resource) * MAC_RES_COUNT);
488 au1xxx_eth0_device.resource = macres;
489
490 i = prom_get_ethernet_addr(ethaddr);
491 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
492 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
493
494 ret = platform_device_register(&au1xxx_eth0_device);
495 if (!ret)
496 printk(KERN_INFO "Alchemy: failed to register MAC0\n");
497
498
499 /* Handle 2nd MAC */
500 if (alchemy_get_macs(ctype) < 2)
501 return;
502
503 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
504 if (!macres) {
505 printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
506 return;
507 }
508 memcpy(macres, au1xxx_eth1_resources[ctype],
509 sizeof(struct resource) * MAC_RES_COUNT);
510 au1xxx_eth1_device.resource = macres;
511
512 ethaddr[5] += 1; /* next addr for 2nd MAC */
513 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
514 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
515
516 /* Register second MAC if enabled in pinfunc */
517 if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) {
518 ret = platform_device_register(&au1xxx_eth1_device);
519 if (ret)
520 printk(KERN_INFO "Alchemy: failed to register MAC1\n");
521 }
442} 522}
443 523
444static struct platform_device *au1xxx_platform_devices[] __initdata = { 524static struct platform_device *au1xxx_platform_devices[] __initdata = {
445 &au1xx0_uart_device,
446 &au1xxx_usb_ohci_device, 525 &au1xxx_usb_ohci_device,
447#ifdef CONFIG_FB_AU1100 526#ifdef CONFIG_FB_AU1100
448 &au1100_lcd_device, 527 &au1100_lcd_device,
@@ -460,36 +539,17 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
460#ifdef SMBUS_PSC_BASE 539#ifdef SMBUS_PSC_BASE
461 &pbdb_smbus_device, 540 &pbdb_smbus_device,
462#endif 541#endif
463 &au1xxx_eth0_device,
464}; 542};
465 543
466static int __init au1xxx_platform_init(void) 544static int __init au1xxx_platform_init(void)
467{ 545{
468 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 546 int err, ctype = alchemy_get_cputype();
469 int err, i;
470 unsigned char ethaddr[6];
471 547
472 /* Fill up uartclk. */ 548 alchemy_setup_uarts(ctype);
473 for (i = 0; au1x00_uart_data[i].flags; i++) 549 alchemy_setup_macs(ctype);
474 au1x00_uart_data[i].uartclk = uartclk;
475
476 /* use firmware-provided mac addr if available and necessary */
477 i = prom_get_ethernet_addr(ethaddr);
478 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
479 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
480 550
481 err = platform_add_devices(au1xxx_platform_devices, 551 err = platform_add_devices(au1xxx_platform_devices,
482 ARRAY_SIZE(au1xxx_platform_devices)); 552 ARRAY_SIZE(au1xxx_platform_devices));
483#ifndef CONFIG_SOC_AU1100
484 ethaddr[5] += 1; /* next addr for 2nd MAC */
485 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
486 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
487
488 /* Register second MAC if enabled in pinfunc */
489 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
490 err = platform_device_register(&au1xxx_eth1_device);
491#endif
492
493 return err; 553 return err;
494} 554}
495 555
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 561e5da2658b..1b887c868417 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -52,8 +52,6 @@ void __init plat_mem_setup(void)
52 /* this is faster than wasting cycles trying to approximate it */ 52 /* this is faster than wasting cycles trying to approximate it */
53 preset_lpj = (est_freq >> 1) / HZ; 53 preset_lpj = (est_freq >> 1) / HZ;
54 54
55 board_setup(); /* board specific setup */
56
57 if (au1xxx_cpu_needs_config_od()) 55 if (au1xxx_cpu_needs_config_od())
58 /* Various early Au1xx0 errata corrected by this */ 56 /* Various early Au1xx0 errata corrected by this */
59 set_c0_config(1 << 19); /* Set Config[OD] */ 57 set_c0_config(1 << 19); /* Set Config[OD] */
@@ -61,6 +59,8 @@ void __init plat_mem_setup(void)
61 /* Clear to obtain best system bus performance */ 59 /* Clear to obtain best system bus performance */
62 clear_c0_config(1 << 19); /* Clear Config[OD] */ 60 clear_c0_config(1 << 19); /* Clear Config[OD] */
63 61
62 board_setup(); /* board specific setup */
63
64 /* IO/MEM resources. */ 64 /* IO/MEM resources. */
65 set_io_port_base(0); 65 set_io_port_base(0);
66 ioport_resource.start = IOPORT_RESOURCE_START; 66 ioport_resource.start = IOPORT_RESOURCE_START;
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
index 4a8980027ecf..1dac4f27d334 100644
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -23,6 +23,13 @@ void __init board_setup(void)
23 unsigned long freq0, clksrc, div, pfc; 23 unsigned long freq0, clksrc, div, pfc;
24 unsigned short whoami; 24 unsigned short whoami;
25 25
26 /* Set Config[OD] (disable overlapping bus transaction):
27 * This gets rid of a _lot_ of spurious interrupts (especially
28 * wrt. IDE); but incurs ~10% performance hit in some
29 * cpu-bound applications.
30 */
31 set_c0_config(1 << 19);
32
26 bcsr_init(DB1200_BCSR_PHYS_ADDR, 33 bcsr_init(DB1200_BCSR_PHYS_ADDR,
27 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 34 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
28 35
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 05f120ff90f9..5c956fe8760f 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -127,13 +127,10 @@ const char *get_system_type(void)
127void __init board_setup(void) 127void __init board_setup(void)
128{ 128{
129 unsigned long bcsr1, bcsr2; 129 unsigned long bcsr1, bcsr2;
130 u32 pin_func;
131 130
132 bcsr1 = DB1000_BCSR_PHYS_ADDR; 131 bcsr1 = DB1000_BCSR_PHYS_ADDR;
133 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS; 132 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
134 133
135 pin_func = 0;
136
137#ifdef CONFIG_MIPS_DB1000 134#ifdef CONFIG_MIPS_DB1000
138 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); 135 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
139#endif 136#endif
@@ -164,12 +161,16 @@ void __init board_setup(void)
164 /* Not valid for Au1550 */ 161 /* Not valid for Au1550 */
165#if defined(CONFIG_IRDA) && \ 162#if defined(CONFIG_IRDA) && \
166 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100)) 163 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
167 /* Set IRFIRSEL instead of GPIO15 */ 164 {
168 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; 165 u32 pin_func;
169 au_writel(pin_func, SYS_PINFUNC); 166
170 /* Power off until the driver is in use */ 167 /* Set IRFIRSEL instead of GPIO15 */
171 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, 168 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
172 BCSR_RESETS_IRDA_MODE_OFF); 169 au_writel(pin_func, SYS_PINFUNC);
170 /* Power off until the driver is in use */
171 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
172 BCSR_RESETS_IRDA_MODE_OFF);
173 }
173#endif 174#endif
174 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ 175 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
175 176
@@ -177,31 +178,35 @@ void __init board_setup(void)
177 alchemy_gpio1_input_enable(); 178 alchemy_gpio1_input_enable();
178 179
179#ifdef CONFIG_MIPS_MIRAGE 180#ifdef CONFIG_MIPS_MIRAGE
180 /* GPIO[20] is output */ 181 {
181 alchemy_gpio_direction_output(20, 0); 182 u32 pin_func;
182 183
183 /* Set GPIO[210:208] instead of SSI_0 */ 184 /* GPIO[20] is output */
184 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; 185 alchemy_gpio_direction_output(20, 0);
185 186
186 /* Set GPIO[215:211] for LEDs */ 187 /* Set GPIO[210:208] instead of SSI_0 */
187 pin_func |= 5 << 2; 188 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
188 189
189 /* Set GPIO[214:213] for more LEDs */ 190 /* Set GPIO[215:211] for LEDs */
190 pin_func |= 5 << 12; 191 pin_func |= 5 << 2;
191 192
192 /* Set GPIO[207:200] instead of PCMCIA/LCD */ 193 /* Set GPIO[214:213] for more LEDs */
193 pin_func |= SYS_PF_LCD | SYS_PF_PC; 194 pin_func |= 5 << 12;
194 au_writel(pin_func, SYS_PINFUNC);
195 195
196 /* 196 /* Set GPIO[207:200] instead of PCMCIA/LCD */
197 * Enable speaker amplifier. This should 197 pin_func |= SYS_PF_LCD | SYS_PF_PC;
198 * be part of the audio driver. 198 au_writel(pin_func, SYS_PINFUNC);
199 */
200 alchemy_gpio_direction_output(209, 1);
201 199
202 pm_power_off = mirage_power_off; 200 /*
203 _machine_halt = mirage_power_off; 201 * Enable speaker amplifier. This should
204 _machine_restart = (void(*)(char *))mips_softreset; 202 * be part of the audio driver.
203 */
204 alchemy_gpio_direction_output(209, 1);
205
206 pm_power_off = mirage_power_off;
207 _machine_halt = mirage_power_off;
208 _machine_restart = (void(*)(char *))mips_softreset;
209 }
205#endif 210#endif
206 211
207#ifdef CONFIG_MIPS_BOSPORUS 212#ifdef CONFIG_MIPS_BOSPORUS
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index 2d85c4b5be09..e64fdcbf75d0 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -65,7 +65,7 @@ void __init board_setup(void)
65 65
66 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 66 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
67 au_writel(8, SYS_AUXPLL); 67 au_writel(8, SYS_AUXPLL);
68 au_writel(0, SYS_PINSTATERD); 68 alchemy_gpio1_input_enable();
69 udelay(100); 69 udelay(100);
70 70
71#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 71#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 83f46215eb0c..3b4fa3206969 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -56,7 +56,7 @@ void __init board_setup(void)
56 sys_clksrc = sys_freqctrl = pin_func = 0; 56 sys_clksrc = sys_freqctrl = pin_func = 0;
57 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 57 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
58 au_writel(8, SYS_AUXPLL); 58 au_writel(8, SYS_AUXPLL);
59 au_writel(0, SYS_PINSTATERD); 59 alchemy_gpio1_input_enable();
60 udelay(100); 60 udelay(100);
61 61
62 /* GPIO201 is input for PCMCIA card detect */ 62 /* GPIO201 is input for PCMCIA card detect */
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index baeb21385058..e5306b56da6d 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -62,5 +62,5 @@ void __init prom_init(void)
62 62
63void prom_putchar(unsigned char c) 63void prom_putchar(unsigned char c)
64{ 64{
65 alchemy_uart_putchar(UART0_PHYS_ADDR, c); 65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
66} 66}
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
index ad2e3f137933..5f8f0691ed2d 100644
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -36,9 +36,6 @@
36 36
37#include <prom.h> 37#include <prom.h>
38 38
39#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR)
40#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR)
41
42char irq_tab_alchemy[][5] __initdata = { 39char irq_tab_alchemy[][5] __initdata = {
43 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, 40 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
44}; 41};
@@ -67,18 +64,15 @@ static void gpr_power_off(void)
67 64
68void __init board_setup(void) 65void __init board_setup(void)
69{ 66{
70 printk(KERN_INFO "Tarpeze ITS GPR board\n"); 67 printk(KERN_INFO "Trapeze ITS GPR board\n");
71 68
72 pm_power_off = gpr_power_off; 69 pm_power_off = gpr_power_off;
73 _machine_halt = gpr_power_off; 70 _machine_halt = gpr_power_off;
74 _machine_restart = gpr_reset; 71 _machine_restart = gpr_reset;
75 72
76 /* Enable UART3 */ 73 /* Enable UART1/3 */
77 au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */ 74 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
78 au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ 75 alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
79 /* Enable UART1 */
80 au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
81 au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
82 76
83 /* Take away Reset of UMTS-card */ 77 /* Take away Reset of UMTS-card */
84 alchemy_gpio_direction_output(215, 1); 78 alchemy_gpio_direction_output(215, 1);
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
index f044f4c541d7..229aafae680c 100644
--- a/arch/mips/alchemy/gpr/init.c
+++ b/arch/mips/alchemy/gpr/init.c
@@ -59,5 +59,5 @@ void __init prom_init(void)
59 59
60void prom_putchar(unsigned char c) 60void prom_putchar(unsigned char c)
61{ 61{
62 alchemy_uart_putchar(UART0_PHYS_ADDR, c); 62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
63} 63}
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index cf436ab679ae..3ae984cf98cf 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -87,7 +87,7 @@ void __init board_setup(void)
87 au_writel(SYS_PF_NI2, SYS_PINFUNC); 87 au_writel(SYS_PF_NI2, SYS_PINFUNC);
88 88
89 /* Initialize GPIO */ 89 /* Initialize GPIO */
90 au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); 90 au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
91 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ 91 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
92 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ 92 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
93 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ 93 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
index f8d25575fa05..2e81cc7f3422 100644
--- a/arch/mips/alchemy/mtx-1/init.c
+++ b/arch/mips/alchemy/mtx-1/init.c
@@ -62,5 +62,5 @@ void __init prom_init(void)
62 62
63void prom_putchar(unsigned char c) 63void prom_putchar(unsigned char c)
64{ 64{
65 alchemy_uart_putchar(UART0_PHYS_ADDR, c); 65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
66} 66}
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
index 956f946218c5..55628e390fd7 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/mtx-1/platform.c
@@ -53,8 +53,8 @@ static struct platform_device mtx1_button = {
53 53
54static struct resource mtx1_wdt_res[] = { 54static struct resource mtx1_wdt_res[] = {
55 [0] = { 55 [0] = {
56 .start = 15, 56 .start = 215,
57 .end = 15, 57 .end = 215,
58 .name = "mtx1-wdt-gpio", 58 .name = "mtx1-wdt-gpio",
59 .flags = IORESOURCE_IRQ, 59 .flags = IORESOURCE_IRQ,
60 } 60 }
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index febfb0fb0896..81e57fad07ab 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -66,13 +66,10 @@ void __init board_setup(void)
66 au_writel(pin_func, SYS_PINFUNC); 66 au_writel(pin_func, SYS_PINFUNC);
67 67
68 /* Enable UART */ 68 /* Enable UART */
69 au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ 69 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
70 mdelay(10); 70 /* Enable DTR (MCR bit 0) = USB power up */
71 au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ 71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
72 mdelay(10); 72 wmb();
73
74 /* Enable DTR = USB power up */
75 au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
76 73
77#ifdef CONFIG_PCI 74#ifdef CONFIG_PCI
78#if defined(__MIPSEB__) 75#if defined(__MIPSEB__)
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 15125c2fda7d..0ee02cfa989d 100644
--- a/arch/mips/alchemy/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -51,14 +51,13 @@ void __init prom_init(void)
51 prom_init_cmdline(); 51 prom_init_cmdline();
52 52
53 memsize_str = prom_getenv("memsize"); 53 memsize_str = prom_getenv("memsize");
54 if (!memsize_str) 54 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
55 memsize = 0x04000000; 55 memsize = 0x04000000;
56 else 56
57 strict_strtoul(memsize_str, 0, &memsize);
58 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
59} 58}
60 59
61void prom_putchar(unsigned char c) 60void prom_putchar(unsigned char c)
62{ 61{
63 alchemy_uart_putchar(UART0_PHYS_ADDR, c); 62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
64} 63}
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index 425dfa5d6e12..bb571bcdb8f2 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -325,9 +325,7 @@ int __init ar7_gpio_init(void)
325 size = 0x1f; 325 size = 0x1f;
326 } 326 }
327 327
328 gpch->regs = ioremap_nocache(AR7_REGS_GPIO, 328 gpch->regs = ioremap_nocache(AR7_REGS_GPIO, size);
329 AR7_REGS_GPIO + 0x10);
330
331 if (!gpch->regs) { 329 if (!gpch->regs) {
332 printk(KERN_ERR "%s: failed to ioremap regs\n", 330 printk(KERN_ERR "%s: failed to ioremap regs\n",
333 gpch->chip.label); 331 gpch->chip.label);
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index e5b6615731e5..54db815bc86c 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2005 Broadcom Corporation 4 * Copyright (C) 2005 Broadcom Corporation
5 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 5 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -23,7 +24,7 @@
23static char nvram_buf[NVRAM_SPACE]; 24static char nvram_buf[NVRAM_SPACE];
24 25
25/* Probe for NVRAM header */ 26/* Probe for NVRAM header */
26static void __init early_nvram_init(void) 27static void early_nvram_init(void)
27{ 28{
28 struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; 29 struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
29 struct nvram_header *header; 30 struct nvram_header *header;
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index c95f90bf734c..73b529b57433 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -3,6 +3,7 @@
3 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de> 4 * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
5 * Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org> 5 * Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org>
6 * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -57,10 +58,49 @@ static void bcm47xx_machine_halt(void)
57} 58}
58 59
59#define READ_FROM_NVRAM(_outvar, name, buf) \ 60#define READ_FROM_NVRAM(_outvar, name, buf) \
60 if (nvram_getenv(name, buf, sizeof(buf)) >= 0)\ 61 if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\
61 sprom->_outvar = simple_strtoul(buf, NULL, 0); 62 sprom->_outvar = simple_strtoul(buf, NULL, 0);
62 63
63static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) 64#define READ_FROM_NVRAM2(_outvar, name1, name2, buf) \
65 if (nvram_getprefix(prefix, name1, buf, sizeof(buf)) >= 0 || \
66 nvram_getprefix(prefix, name2, buf, sizeof(buf)) >= 0)\
67 sprom->_outvar = simple_strtoul(buf, NULL, 0);
68
69static inline int nvram_getprefix(const char *prefix, char *name,
70 char *buf, int len)
71{
72 if (prefix) {
73 char key[100];
74
75 snprintf(key, sizeof(key), "%s%s", prefix, name);
76 return nvram_getenv(key, buf, len);
77 }
78
79 return nvram_getenv(name, buf, len);
80}
81
82static u32 nvram_getu32(const char *name, char *buf, int len)
83{
84 int rv;
85 char key[100];
86 u16 var0, var1;
87
88 snprintf(key, sizeof(key), "%s0", name);
89 rv = nvram_getenv(key, buf, len);
90 /* return 0 here so this looks like unset */
91 if (rv < 0)
92 return 0;
93 var0 = simple_strtoul(buf, NULL, 0);
94
95 snprintf(key, sizeof(key), "%s1", name);
96 rv = nvram_getenv(key, buf, len);
97 if (rv < 0)
98 return 0;
99 var1 = simple_strtoul(buf, NULL, 0);
100 return var1 << 16 | var0;
101}
102
103static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix)
64{ 104{
65 char buf[100]; 105 char buf[100];
66 u32 boardflags; 106 u32 boardflags;
@@ -69,11 +109,12 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
69 109
70 sprom->revision = 1; /* Fallback: Old hardware does not define this. */ 110 sprom->revision = 1; /* Fallback: Old hardware does not define this. */
71 READ_FROM_NVRAM(revision, "sromrev", buf); 111 READ_FROM_NVRAM(revision, "sromrev", buf);
72 if (nvram_getenv("il0macaddr", buf, sizeof(buf)) >= 0) 112 if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0 ||
113 nvram_getprefix(prefix, "macaddr", buf, sizeof(buf)) >= 0)
73 nvram_parse_macaddr(buf, sprom->il0mac); 114 nvram_parse_macaddr(buf, sprom->il0mac);
74 if (nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0) 115 if (nvram_getprefix(prefix, "et0macaddr", buf, sizeof(buf)) >= 0)
75 nvram_parse_macaddr(buf, sprom->et0mac); 116 nvram_parse_macaddr(buf, sprom->et0mac);
76 if (nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0) 117 if (nvram_getprefix(prefix, "et1macaddr", buf, sizeof(buf)) >= 0)
77 nvram_parse_macaddr(buf, sprom->et1mac); 118 nvram_parse_macaddr(buf, sprom->et1mac);
78 READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf); 119 READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf);
79 READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf); 120 READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf);
@@ -95,20 +136,36 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
95 READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf); 136 READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf);
96 READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf); 137 READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf);
97 READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf); 138 READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf);
98 READ_FROM_NVRAM(gpio0, "wl0gpio0", buf); 139 READ_FROM_NVRAM2(gpio0, "ledbh0", "wl0gpio0", buf);
99 READ_FROM_NVRAM(gpio1, "wl0gpio1", buf); 140 READ_FROM_NVRAM2(gpio1, "ledbh1", "wl0gpio1", buf);
100 READ_FROM_NVRAM(gpio2, "wl0gpio2", buf); 141 READ_FROM_NVRAM2(gpio2, "ledbh2", "wl0gpio2", buf);
101 READ_FROM_NVRAM(gpio3, "wl0gpio3", buf); 142 READ_FROM_NVRAM2(gpio3, "ledbh3", "wl0gpio3", buf);
102 READ_FROM_NVRAM(maxpwr_bg, "pa0maxpwr", buf); 143 READ_FROM_NVRAM2(maxpwr_bg, "maxp2ga0", "pa0maxpwr", buf);
103 READ_FROM_NVRAM(maxpwr_al, "pa1lomaxpwr", buf); 144 READ_FROM_NVRAM2(maxpwr_al, "maxp5gla0", "pa1lomaxpwr", buf);
104 READ_FROM_NVRAM(maxpwr_a, "pa1maxpwr", buf); 145 READ_FROM_NVRAM2(maxpwr_a, "maxp5ga0", "pa1maxpwr", buf);
105 READ_FROM_NVRAM(maxpwr_ah, "pa1himaxpwr", buf); 146 READ_FROM_NVRAM2(maxpwr_ah, "maxp5gha0", "pa1himaxpwr", buf);
106 READ_FROM_NVRAM(itssi_a, "pa1itssit", buf); 147 READ_FROM_NVRAM2(itssi_bg, "itt5ga0", "pa0itssit", buf);
107 READ_FROM_NVRAM(itssi_bg, "pa0itssit", buf); 148 READ_FROM_NVRAM2(itssi_a, "itt2ga0", "pa1itssit", buf);
108 READ_FROM_NVRAM(tri2g, "tri2g", buf); 149 READ_FROM_NVRAM(tri2g, "tri2g", buf);
109 READ_FROM_NVRAM(tri5gl, "tri5gl", buf); 150 READ_FROM_NVRAM(tri5gl, "tri5gl", buf);
110 READ_FROM_NVRAM(tri5g, "tri5g", buf); 151 READ_FROM_NVRAM(tri5g, "tri5g", buf);
111 READ_FROM_NVRAM(tri5gh, "tri5gh", buf); 152 READ_FROM_NVRAM(tri5gh, "tri5gh", buf);
153 READ_FROM_NVRAM(txpid2g[0], "txpid2ga0", buf);
154 READ_FROM_NVRAM(txpid2g[1], "txpid2ga1", buf);
155 READ_FROM_NVRAM(txpid2g[2], "txpid2ga2", buf);
156 READ_FROM_NVRAM(txpid2g[3], "txpid2ga3", buf);
157 READ_FROM_NVRAM(txpid5g[0], "txpid5ga0", buf);
158 READ_FROM_NVRAM(txpid5g[1], "txpid5ga1", buf);
159 READ_FROM_NVRAM(txpid5g[2], "txpid5ga2", buf);
160 READ_FROM_NVRAM(txpid5g[3], "txpid5ga3", buf);
161 READ_FROM_NVRAM(txpid5gl[0], "txpid5gla0", buf);
162 READ_FROM_NVRAM(txpid5gl[1], "txpid5gla1", buf);
163 READ_FROM_NVRAM(txpid5gl[2], "txpid5gla2", buf);
164 READ_FROM_NVRAM(txpid5gl[3], "txpid5gla3", buf);
165 READ_FROM_NVRAM(txpid5gh[0], "txpid5gha0", buf);
166 READ_FROM_NVRAM(txpid5gh[1], "txpid5gha1", buf);
167 READ_FROM_NVRAM(txpid5gh[2], "txpid5gha2", buf);
168 READ_FROM_NVRAM(txpid5gh[3], "txpid5gha3", buf);
112 READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf); 169 READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf);
113 READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf); 170 READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf);
114 READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf); 171 READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf);
@@ -120,19 +177,27 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
120 READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf); 177 READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf);
121 READ_FROM_NVRAM(bxa5g, "bxa5g", buf); 178 READ_FROM_NVRAM(bxa5g, "bxa5g", buf);
122 READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf); 179 READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf);
123 READ_FROM_NVRAM(ofdm2gpo, "ofdm2gpo", buf);
124 READ_FROM_NVRAM(ofdm5glpo, "ofdm5glpo", buf);
125 READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf);
126 READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf);
127 180
128 if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0) { 181 sprom->ofdm2gpo = nvram_getu32("ofdm2gpo", buf, sizeof(buf));
182 sprom->ofdm5glpo = nvram_getu32("ofdm5glpo", buf, sizeof(buf));
183 sprom->ofdm5gpo = nvram_getu32("ofdm5gpo", buf, sizeof(buf));
184 sprom->ofdm5ghpo = nvram_getu32("ofdm5ghpo", buf, sizeof(buf));
185
186 READ_FROM_NVRAM(antenna_gain.ghz24.a0, "ag0", buf);
187 READ_FROM_NVRAM(antenna_gain.ghz24.a1, "ag1", buf);
188 READ_FROM_NVRAM(antenna_gain.ghz24.a2, "ag2", buf);
189 READ_FROM_NVRAM(antenna_gain.ghz24.a3, "ag3", buf);
190 memcpy(&sprom->antenna_gain.ghz5, &sprom->antenna_gain.ghz24,
191 sizeof(sprom->antenna_gain.ghz5));
192
193 if (nvram_getprefix(prefix, "boardflags", buf, sizeof(buf)) >= 0) {
129 boardflags = simple_strtoul(buf, NULL, 0); 194 boardflags = simple_strtoul(buf, NULL, 0);
130 if (boardflags) { 195 if (boardflags) {
131 sprom->boardflags_lo = (boardflags & 0x0000FFFFU); 196 sprom->boardflags_lo = (boardflags & 0x0000FFFFU);
132 sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16; 197 sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16;
133 } 198 }
134 } 199 }
135 if (nvram_getenv("boardflags2", buf, sizeof(buf)) >= 0) { 200 if (nvram_getprefix(prefix, "boardflags2", buf, sizeof(buf)) >= 0) {
136 boardflags = simple_strtoul(buf, NULL, 0); 201 boardflags = simple_strtoul(buf, NULL, 0);
137 if (boardflags) { 202 if (boardflags) {
138 sprom->boardflags2_lo = (boardflags & 0x0000FFFFU); 203 sprom->boardflags2_lo = (boardflags & 0x0000FFFFU);
@@ -141,6 +206,22 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
141 } 206 }
142} 207}
143 208
209int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
210{
211 char prefix[10];
212
213 if (bus->bustype == SSB_BUSTYPE_PCI) {
214 snprintf(prefix, sizeof(prefix), "pci/%u/%u/",
215 bus->host_pci->bus->number + 1,
216 PCI_SLOT(bus->host_pci->devfn));
217 bcm47xx_fill_sprom(out, prefix);
218 return 0;
219 } else {
220 printk(KERN_WARNING "bcm47xx: unable to fill SPROM for given bustype.\n");
221 return -EINVAL;
222 }
223}
224
144static int bcm47xx_get_invariants(struct ssb_bus *bus, 225static int bcm47xx_get_invariants(struct ssb_bus *bus,
145 struct ssb_init_invariants *iv) 226 struct ssb_init_invariants *iv)
146{ 227{
@@ -158,7 +239,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
158 if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0) 239 if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0)
159 iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0); 240 iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
160 241
161 bcm47xx_fill_sprom(&iv->sprom); 242 bcm47xx_fill_sprom(&iv->sprom, NULL);
162 243
163 if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0) 244 if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
164 iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10); 245 iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
@@ -172,6 +253,11 @@ void __init plat_mem_setup(void)
172 char buf[100]; 253 char buf[100];
173 struct ssb_mipscore *mcore; 254 struct ssb_mipscore *mcore;
174 255
256 err = ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom);
257 if (err)
258 printk(KERN_WARNING "bcm47xx: someone else already registered"
259 " a ssb SPROM callback handler (err %d)\n", err);
260
175 err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, 261 err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
176 bcm47xx_get_invariants); 262 bcm47xx_get_invariants);
177 if (err) 263 if (err)
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 8dba8cfb752f..40b223b603be 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -643,6 +643,17 @@ static struct ssb_sprom bcm63xx_sprom = {
643 .boardflags_lo = 0x2848, 643 .boardflags_lo = 0x2848,
644 .boardflags_hi = 0x0000, 644 .boardflags_hi = 0x0000,
645}; 645};
646
647int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
648{
649 if (bus->bustype == SSB_BUSTYPE_PCI) {
650 memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
651 return 0;
652 } else {
653 printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n");
654 return -EINVAL;
655 }
656}
646#endif 657#endif
647 658
648/* 659/*
@@ -793,8 +804,9 @@ void __init board_prom_init(void)
793 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { 804 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
794 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); 805 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
795 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); 806 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
796 if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0) 807 if (ssb_arch_register_fallback_sprom(
797 printk(KERN_ERR "failed to register fallback SPROM\n"); 808 &bcm63xx_get_fallback_sprom) < 0)
809 printk(KERN_ERR PFX "failed to register fallback SPROM\n");
798 } 810 }
799#endif 811#endif
800} 812}
diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
index 88c9d963be88..9a6243676e22 100644
--- a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
+++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
@@ -16,8 +16,8 @@
16 16
17int main(int argc, char *argv[]) 17int main(int argc, char *argv[])
18{ 18{
19 unsigned long long vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
19 struct stat sb; 20 struct stat sb;
20 uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
21 21
22 if (argc != 3) { 22 if (argc != 3) {
23 fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n", 23 fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c
index 1bff22fa089b..eb063e6dead9 100644
--- a/arch/mips/boot/compressed/uart-alchemy.c
+++ b/arch/mips/boot/compressed/uart-alchemy.c
@@ -3,5 +3,5 @@
3void putc(char c) 3void putc(char c)
4{ 4{
5 /* all current (Jan. 2010) in-kernel boards */ 5 /* all current (Jan. 2010) in-kernel boards */
6 alchemy_uart_putchar(UART0_PHYS_ADDR, c); 6 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
7} 7}
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index caae22858163..cad555ebeca3 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -1,11 +1,7 @@
1config CAVIUM_OCTEON_SPECIFIC_OPTIONS 1if CPU_CAVIUM_OCTEON
2 bool "Enable Octeon specific options"
3 depends on CPU_CAVIUM_OCTEON
4 default "y"
5 2
6config CAVIUM_CN63XXP1 3config CAVIUM_CN63XXP1
7 bool "Enable CN63XXP1 errata worarounds" 4 bool "Enable CN63XXP1 errata worarounds"
8 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
9 default "n" 5 default "n"
10 help 6 help
11 The CN63XXP1 chip requires build time workarounds to 7 The CN63XXP1 chip requires build time workarounds to
@@ -16,7 +12,6 @@ config CAVIUM_CN63XXP1
16 12
17config CAVIUM_OCTEON_2ND_KERNEL 13config CAVIUM_OCTEON_2ND_KERNEL
18 bool "Build the kernel to be used as a 2nd kernel on the same chip" 14 bool "Build the kernel to be used as a 2nd kernel on the same chip"
19 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
20 default "n" 15 default "n"
21 help 16 help
22 This option configures this kernel to be linked at a different 17 This option configures this kernel to be linked at a different
@@ -26,7 +21,6 @@ config CAVIUM_OCTEON_2ND_KERNEL
26 21
27config CAVIUM_OCTEON_HW_FIX_UNALIGNED 22config CAVIUM_OCTEON_HW_FIX_UNALIGNED
28 bool "Enable hardware fixups of unaligned loads and stores" 23 bool "Enable hardware fixups of unaligned loads and stores"
29 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
30 default "y" 24 default "y"
31 help 25 help
32 Configure the Octeon hardware to automatically fix unaligned loads 26 Configure the Octeon hardware to automatically fix unaligned loads
@@ -38,7 +32,6 @@ config CAVIUM_OCTEON_HW_FIX_UNALIGNED
38 32
39config CAVIUM_OCTEON_CVMSEG_SIZE 33config CAVIUM_OCTEON_CVMSEG_SIZE
40 int "Number of L1 cache lines reserved for CVMSEG memory" 34 int "Number of L1 cache lines reserved for CVMSEG memory"
41 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
42 range 0 54 35 range 0 54
43 default 1 36 default 1
44 help 37 help
@@ -50,7 +43,6 @@ config CAVIUM_OCTEON_CVMSEG_SIZE
50 43
51config CAVIUM_OCTEON_LOCK_L2 44config CAVIUM_OCTEON_LOCK_L2
52 bool "Lock often used kernel code in the L2" 45 bool "Lock often used kernel code in the L2"
53 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
54 default "y" 46 default "y"
55 help 47 help
56 Enable locking parts of the kernel into the L2 cache. 48 Enable locking parts of the kernel into the L2 cache.
@@ -93,7 +85,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY
93config ARCH_SPARSEMEM_ENABLE 85config ARCH_SPARSEMEM_ENABLE
94 def_bool y 86 def_bool y
95 select SPARSEMEM_STATIC 87 select SPARSEMEM_STATIC
96 depends on CPU_CAVIUM_OCTEON
97 88
98config CAVIUM_OCTEON_HELPER 89config CAVIUM_OCTEON_HELPER
99 def_bool y 90 def_bool y
@@ -107,6 +98,8 @@ config NEED_SG_DMA_LENGTH
107 98
108config SWIOTLB 99config SWIOTLB
109 def_bool y 100 def_bool y
110 depends on CPU_CAVIUM_OCTEON
111 select IOMMU_HELPER 101 select IOMMU_HELPER
112 select NEED_SG_DMA_LENGTH 102 select NEED_SG_DMA_LENGTH
103
104
105endif # CPU_CAVIUM_OCTEON
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 0707fae3f0ee..2d9028f1474c 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -288,7 +288,6 @@ void octeon_user_io_init(void)
288 union octeon_cvmemctl cvmmemctl; 288 union octeon_cvmemctl cvmmemctl;
289 union cvmx_iob_fau_timeout fau_timeout; 289 union cvmx_iob_fau_timeout fau_timeout;
290 union cvmx_pow_nw_tim nm_tim; 290 union cvmx_pow_nw_tim nm_tim;
291 uint64_t cvmctl;
292 291
293 /* Get the current settings for CP0_CVMMEMCTL_REG */ 292 /* Get the current settings for CP0_CVMMEMCTL_REG */
294 cvmmemctl.u64 = read_c0_cvmmemctl(); 293 cvmmemctl.u64 = read_c0_cvmmemctl();
@@ -392,12 +391,6 @@ void octeon_user_io_init(void)
392 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 391 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
393 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 392 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
394 393
395 /* Move the performance counter interrupts to IRQ 6 */
396 cvmctl = read_c0_cvmctl();
397 cvmctl &= ~(7 << 7);
398 cvmctl |= 6 << 7;
399 write_c0_cvmctl(cvmctl);
400
401 /* Set a default for the hardware timeouts */ 394 /* Set a default for the hardware timeouts */
402 fau_timeout.u64 = 0; 395 fau_timeout.u64 = 0;
403 fau_timeout.s.tout_val = 0xfff; 396 fau_timeout.s.tout_val = 0xfff;
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index ba78b21cc8d0..8b606423bbd7 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -37,13 +37,15 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
37 uint64_t action; 37 uint64_t action;
38 38
39 /* Load the mailbox register to figure out what we're supposed to do */ 39 /* Load the mailbox register to figure out what we're supposed to do */
40 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)); 40 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
41 41
42 /* Clear the mailbox to clear the interrupt */ 42 /* Clear the mailbox to clear the interrupt */
43 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action); 43 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
44 44
45 if (action & SMP_CALL_FUNCTION) 45 if (action & SMP_CALL_FUNCTION)
46 smp_call_function_interrupt(); 46 smp_call_function_interrupt();
47 if (action & SMP_RESCHEDULE_YOURSELF)
48 scheduler_ipi();
47 49
48 /* Check if we've been told to flush the icache */ 50 /* Check if we've been told to flush the icache */
49 if (action & SMP_ICACHE_FLUSH) 51 if (action & SMP_ICACHE_FLUSH)
@@ -200,16 +202,15 @@ void octeon_prepare_cpus(unsigned int max_cpus)
200 if (labi->labi_signature != LABI_SIGNATURE) 202 if (labi->labi_signature != LABI_SIGNATURE)
201 panic("The bootloader version on this board is incorrect."); 203 panic("The bootloader version on this board is incorrect.");
202#endif 204#endif
203 205 /*
204 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); 206 * Only the low order mailbox bits are used for IPIs, leave
207 * the other bits alone.
208 */
209 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
205 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, 210 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
206 "mailbox0", mailbox_interrupt)) { 211 "SMP-IPI", mailbox_interrupt)) {
207 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); 212 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
208 } 213 }
209 if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
210 "mailbox1", mailbox_interrupt)) {
211 panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
212 }
213} 214}
214 215
215/** 216/**
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
index 167c1d07b809..b6acd2f256b6 100644
--- a/arch/mips/configs/lemote2f_defconfig
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -86,8 +86,8 @@ CONFIG_NET_SCHED=y
86CONFIG_NET_EMATCH=y 86CONFIG_NET_EMATCH=y
87CONFIG_NET_CLS_ACT=y 87CONFIG_NET_CLS_ACT=y
88CONFIG_BT=m 88CONFIG_BT=m
89CONFIG_BT_L2CAP=m 89CONFIG_BT_L2CAP=y
90CONFIG_BT_SCO=m 90CONFIG_BT_SCO=y
91CONFIG_BT_RFCOMM=m 91CONFIG_BT_RFCOMM=m
92CONFIG_BT_RFCOMM_TTY=y 92CONFIG_BT_RFCOMM_TTY=y
93CONFIG_BT_BNEP=m 93CONFIG_BT_BNEP=m
@@ -329,7 +329,7 @@ CONFIG_USB_LED=m
329CONFIG_USB_GADGET=m 329CONFIG_USB_GADGET=m
330CONFIG_USB_GADGET_M66592=y 330CONFIG_USB_GADGET_M66592=y
331CONFIG_MMC=m 331CONFIG_MMC=m
332CONFIG_LEDS_CLASS=m 332CONFIG_LEDS_CLASS=y
333CONFIG_STAGING=y 333CONFIG_STAGING=y
334# CONFIG_STAGING_EXCLUDE_BUILD is not set 334# CONFIG_STAGING_EXCLUDE_BUILD is not set
335CONFIG_FB_SM7XX=y 335CONFIG_FB_SM7XX=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 7270f3183bda..5527abbb7dea 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -374,7 +374,7 @@ CONFIG_FB_CIRRUS=y
374# CONFIG_VGA_CONSOLE is not set 374# CONFIG_VGA_CONSOLE is not set
375CONFIG_FRAMEBUFFER_CONSOLE=y 375CONFIG_FRAMEBUFFER_CONSOLE=y
376CONFIG_HID=m 376CONFIG_HID=m
377CONFIG_LEDS_CLASS=m 377CONFIG_LEDS_CLASS=y
378CONFIG_LEDS_TRIGGER_TIMER=m 378CONFIG_LEDS_TRIGGER_TIMER=m
379CONFIG_LEDS_TRIGGER_IDE_DISK=y 379CONFIG_LEDS_TRIGGER_IDE_DISK=y
380CONFIG_LEDS_TRIGGER_HEARTBEAT=m 380CONFIG_LEDS_TRIGGER_HEARTBEAT=m
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index a97a42c6b2c8..37862b2ce363 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -225,8 +225,8 @@ CONFIG_TOSHIBA_FIR=m
225CONFIG_VLSI_FIR=m 225CONFIG_VLSI_FIR=m
226CONFIG_MCS_FIR=m 226CONFIG_MCS_FIR=m
227CONFIG_BT=m 227CONFIG_BT=m
228CONFIG_BT_L2CAP=m 228CONFIG_BT_L2CAP=y
229CONFIG_BT_SCO=m 229CONFIG_BT_SCO=y
230CONFIG_BT_RFCOMM=m 230CONFIG_BT_RFCOMM=m
231CONFIG_BT_RFCOMM_TTY=y 231CONFIG_BT_RFCOMM_TTY=y
232CONFIG_BT_BNEP=m 232CONFIG_BT_BNEP=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
new file mode 100644
index 000000000000..e4b399fdaa61
--- /dev/null
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -0,0 +1,574 @@
1CONFIG_NLM_XLR_BOARD=y
2CONFIG_HIGHMEM=y
3CONFIG_KSM=y
4CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
5CONFIG_SMP=y
6CONFIG_NO_HZ=y
7CONFIG_HIGH_RES_TIMERS=y
8CONFIG_PREEMPT_VOLUNTARY=y
9CONFIG_KEXEC=y
10CONFIG_EXPERIMENTAL=y
11CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-"
12# CONFIG_LOCALVERSION_AUTO is not set
13CONFIG_SYSVIPC=y
14CONFIG_POSIX_MQUEUE=y
15CONFIG_BSD_PROCESS_ACCT=y
16CONFIG_BSD_PROCESS_ACCT_V3=y
17CONFIG_TASKSTATS=y
18CONFIG_TASK_DELAY_ACCT=y
19CONFIG_TASK_XACCT=y
20CONFIG_TASK_IO_ACCOUNTING=y
21CONFIG_AUDIT=y
22CONFIG_NAMESPACES=y
23CONFIG_SCHED_AUTOGROUP=y
24CONFIG_BLK_DEV_INITRD=y
25CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs"
26CONFIG_RD_BZIP2=y
27CONFIG_RD_LZMA=y
28CONFIG_INITRAMFS_COMPRESSION_GZIP=y
29# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
30CONFIG_EXPERT=y
31CONFIG_KALLSYMS_ALL=y
32# CONFIG_ELF_CORE is not set
33# CONFIG_PCSPKR_PLATFORM is not set
34# CONFIG_PERF_EVENTS is not set
35# CONFIG_COMPAT_BRK is not set
36CONFIG_PROFILING=y
37CONFIG_MODULES=y
38CONFIG_MODULE_UNLOAD=y
39CONFIG_MODVERSIONS=y
40CONFIG_MODULE_SRCVERSION_ALL=y
41CONFIG_BLK_DEV_INTEGRITY=y
42CONFIG_BINFMT_MISC=m
43CONFIG_PM_RUNTIME=y
44CONFIG_PM_DEBUG=y
45CONFIG_PACKET=y
46CONFIG_UNIX=y
47CONFIG_XFRM_USER=m
48CONFIG_NET_KEY=m
49CONFIG_INET=y
50CONFIG_IP_MULTICAST=y
51CONFIG_IP_ADVANCED_ROUTER=y
52CONFIG_IP_MULTIPLE_TABLES=y
53CONFIG_IP_ROUTE_MULTIPATH=y
54CONFIG_IP_ROUTE_VERBOSE=y
55CONFIG_NET_IPIP=m
56CONFIG_IP_MROUTE=y
57CONFIG_IP_PIMSM_V1=y
58CONFIG_IP_PIMSM_V2=y
59CONFIG_SYN_COOKIES=y
60CONFIG_INET_AH=m
61CONFIG_INET_ESP=m
62CONFIG_INET_IPCOMP=m
63CONFIG_INET_XFRM_MODE_TRANSPORT=m
64CONFIG_INET_XFRM_MODE_TUNNEL=m
65CONFIG_INET_XFRM_MODE_BEET=m
66CONFIG_TCP_CONG_ADVANCED=y
67CONFIG_TCP_CONG_HSTCP=m
68CONFIG_TCP_CONG_HYBLA=m
69CONFIG_TCP_CONG_SCALABLE=m
70CONFIG_TCP_CONG_LP=m
71CONFIG_TCP_CONG_VENO=m
72CONFIG_TCP_CONG_YEAH=m
73CONFIG_TCP_CONG_ILLINOIS=m
74CONFIG_TCP_MD5SIG=y
75CONFIG_IPV6=y
76CONFIG_IPV6_PRIVACY=y
77CONFIG_INET6_AH=m
78CONFIG_INET6_ESP=m
79CONFIG_INET6_IPCOMP=m
80CONFIG_INET6_XFRM_MODE_TRANSPORT=m
81CONFIG_INET6_XFRM_MODE_TUNNEL=m
82CONFIG_INET6_XFRM_MODE_BEET=m
83CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
84CONFIG_IPV6_SIT=m
85CONFIG_IPV6_TUNNEL=m
86CONFIG_IPV6_MULTIPLE_TABLES=y
87CONFIG_NETLABEL=y
88CONFIG_NETFILTER=y
89CONFIG_NF_CONNTRACK=m
90CONFIG_NF_CONNTRACK_SECMARK=y
91CONFIG_NF_CONNTRACK_EVENTS=y
92CONFIG_NF_CT_PROTO_UDPLITE=m
93CONFIG_NF_CONNTRACK_AMANDA=m
94CONFIG_NF_CONNTRACK_FTP=m
95CONFIG_NF_CONNTRACK_H323=m
96CONFIG_NF_CONNTRACK_IRC=m
97CONFIG_NF_CONNTRACK_NETBIOS_NS=m
98CONFIG_NF_CONNTRACK_PPTP=m
99CONFIG_NF_CONNTRACK_SANE=m
100CONFIG_NF_CONNTRACK_SIP=m
101CONFIG_NF_CONNTRACK_TFTP=m
102CONFIG_NF_CT_NETLINK=m
103CONFIG_NETFILTER_TPROXY=m
104CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
105CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
106CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
107CONFIG_NETFILTER_XT_TARGET_DSCP=m
108CONFIG_NETFILTER_XT_TARGET_MARK=m
109CONFIG_NETFILTER_XT_TARGET_NFLOG=m
110CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
111CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
112CONFIG_NETFILTER_XT_TARGET_TPROXY=m
113CONFIG_NETFILTER_XT_TARGET_TRACE=m
114CONFIG_NETFILTER_XT_TARGET_SECMARK=m
115CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
116CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
117CONFIG_NETFILTER_XT_MATCH_COMMENT=m
118CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
119CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
120CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
121CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
122CONFIG_NETFILTER_XT_MATCH_DSCP=m
123CONFIG_NETFILTER_XT_MATCH_ESP=m
124CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
125CONFIG_NETFILTER_XT_MATCH_HELPER=m
126CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
127CONFIG_NETFILTER_XT_MATCH_LENGTH=m
128CONFIG_NETFILTER_XT_MATCH_LIMIT=m
129CONFIG_NETFILTER_XT_MATCH_MAC=m
130CONFIG_NETFILTER_XT_MATCH_MARK=m
131CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
132CONFIG_NETFILTER_XT_MATCH_OSF=m
133CONFIG_NETFILTER_XT_MATCH_OWNER=m
134CONFIG_NETFILTER_XT_MATCH_POLICY=m
135CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
136CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
137CONFIG_NETFILTER_XT_MATCH_QUOTA=m
138CONFIG_NETFILTER_XT_MATCH_RATEEST=m
139CONFIG_NETFILTER_XT_MATCH_REALM=m
140CONFIG_NETFILTER_XT_MATCH_RECENT=m
141CONFIG_NETFILTER_XT_MATCH_SOCKET=m
142CONFIG_NETFILTER_XT_MATCH_STATE=m
143CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
144CONFIG_NETFILTER_XT_MATCH_STRING=m
145CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
146CONFIG_NETFILTER_XT_MATCH_TIME=m
147CONFIG_NETFILTER_XT_MATCH_U32=m
148CONFIG_IP_VS=m
149CONFIG_IP_VS_IPV6=y
150CONFIG_IP_VS_PROTO_TCP=y
151CONFIG_IP_VS_PROTO_UDP=y
152CONFIG_IP_VS_PROTO_ESP=y
153CONFIG_IP_VS_PROTO_AH=y
154CONFIG_IP_VS_RR=m
155CONFIG_IP_VS_WRR=m
156CONFIG_IP_VS_LC=m
157CONFIG_IP_VS_WLC=m
158CONFIG_IP_VS_LBLC=m
159CONFIG_IP_VS_LBLCR=m
160CONFIG_IP_VS_DH=m
161CONFIG_IP_VS_SH=m
162CONFIG_IP_VS_SED=m
163CONFIG_IP_VS_NQ=m
164CONFIG_IP_VS_FTP=m
165CONFIG_NF_CONNTRACK_IPV4=m
166CONFIG_IP_NF_QUEUE=m
167CONFIG_IP_NF_IPTABLES=m
168CONFIG_IP_NF_MATCH_AH=m
169CONFIG_IP_NF_MATCH_ECN=m
170CONFIG_IP_NF_MATCH_TTL=m
171CONFIG_IP_NF_FILTER=m
172CONFIG_IP_NF_TARGET_REJECT=m
173CONFIG_IP_NF_TARGET_LOG=m
174CONFIG_IP_NF_TARGET_ULOG=m
175CONFIG_NF_NAT=m
176CONFIG_IP_NF_TARGET_MASQUERADE=m
177CONFIG_IP_NF_TARGET_NETMAP=m
178CONFIG_IP_NF_TARGET_REDIRECT=m
179CONFIG_IP_NF_MANGLE=m
180CONFIG_IP_NF_TARGET_CLUSTERIP=m
181CONFIG_IP_NF_TARGET_ECN=m
182CONFIG_IP_NF_TARGET_TTL=m
183CONFIG_IP_NF_RAW=m
184CONFIG_IP_NF_SECURITY=m
185CONFIG_IP_NF_ARPTABLES=m
186CONFIG_IP_NF_ARPFILTER=m
187CONFIG_IP_NF_ARP_MANGLE=m
188CONFIG_NF_CONNTRACK_IPV6=m
189CONFIG_IP6_NF_QUEUE=m
190CONFIG_IP6_NF_IPTABLES=m
191CONFIG_IP6_NF_MATCH_AH=m
192CONFIG_IP6_NF_MATCH_EUI64=m
193CONFIG_IP6_NF_MATCH_FRAG=m
194CONFIG_IP6_NF_MATCH_OPTS=m
195CONFIG_IP6_NF_MATCH_HL=m
196CONFIG_IP6_NF_MATCH_IPV6HEADER=m
197CONFIG_IP6_NF_MATCH_MH=m
198CONFIG_IP6_NF_MATCH_RT=m
199CONFIG_IP6_NF_TARGET_HL=m
200CONFIG_IP6_NF_TARGET_LOG=m
201CONFIG_IP6_NF_FILTER=m
202CONFIG_IP6_NF_TARGET_REJECT=m
203CONFIG_IP6_NF_MANGLE=m
204CONFIG_IP6_NF_RAW=m
205CONFIG_IP6_NF_SECURITY=m
206CONFIG_DECNET_NF_GRABULATOR=m
207CONFIG_BRIDGE_NF_EBTABLES=m
208CONFIG_BRIDGE_EBT_BROUTE=m
209CONFIG_BRIDGE_EBT_T_FILTER=m
210CONFIG_BRIDGE_EBT_T_NAT=m
211CONFIG_BRIDGE_EBT_802_3=m
212CONFIG_BRIDGE_EBT_AMONG=m
213CONFIG_BRIDGE_EBT_ARP=m
214CONFIG_BRIDGE_EBT_IP=m
215CONFIG_BRIDGE_EBT_IP6=m
216CONFIG_BRIDGE_EBT_LIMIT=m
217CONFIG_BRIDGE_EBT_MARK=m
218CONFIG_BRIDGE_EBT_PKTTYPE=m
219CONFIG_BRIDGE_EBT_STP=m
220CONFIG_BRIDGE_EBT_VLAN=m
221CONFIG_BRIDGE_EBT_ARPREPLY=m
222CONFIG_BRIDGE_EBT_DNAT=m
223CONFIG_BRIDGE_EBT_MARK_T=m
224CONFIG_BRIDGE_EBT_REDIRECT=m
225CONFIG_BRIDGE_EBT_SNAT=m
226CONFIG_BRIDGE_EBT_LOG=m
227CONFIG_BRIDGE_EBT_ULOG=m
228CONFIG_BRIDGE_EBT_NFLOG=m
229CONFIG_IP_DCCP=m
230CONFIG_RDS=m
231CONFIG_RDS_TCP=m
232CONFIG_TIPC=m
233CONFIG_ATM=m
234CONFIG_ATM_CLIP=m
235CONFIG_ATM_LANE=m
236CONFIG_ATM_MPOA=m
237CONFIG_ATM_BR2684=m
238CONFIG_BRIDGE=m
239CONFIG_VLAN_8021Q=m
240CONFIG_VLAN_8021Q_GVRP=y
241CONFIG_DECNET=m
242CONFIG_LLC2=m
243CONFIG_IPX=m
244CONFIG_ATALK=m
245CONFIG_DEV_APPLETALK=m
246CONFIG_IPDDP=m
247CONFIG_IPDDP_ENCAP=y
248CONFIG_IPDDP_DECAP=y
249CONFIG_X25=m
250CONFIG_LAPB=m
251CONFIG_ECONET=m
252CONFIG_ECONET_AUNUDP=y
253CONFIG_ECONET_NATIVE=y
254CONFIG_WAN_ROUTER=m
255CONFIG_PHONET=m
256CONFIG_IEEE802154=m
257CONFIG_NET_SCHED=y
258CONFIG_NET_SCH_CBQ=m
259CONFIG_NET_SCH_HTB=m
260CONFIG_NET_SCH_HFSC=m
261CONFIG_NET_SCH_ATM=m
262CONFIG_NET_SCH_PRIO=m
263CONFIG_NET_SCH_MULTIQ=m
264CONFIG_NET_SCH_RED=m
265CONFIG_NET_SCH_SFQ=m
266CONFIG_NET_SCH_TEQL=m
267CONFIG_NET_SCH_TBF=m
268CONFIG_NET_SCH_GRED=m
269CONFIG_NET_SCH_DSMARK=m
270CONFIG_NET_SCH_NETEM=m
271CONFIG_NET_SCH_DRR=m
272CONFIG_NET_SCH_INGRESS=m
273CONFIG_NET_CLS_BASIC=m
274CONFIG_NET_CLS_TCINDEX=m
275CONFIG_NET_CLS_ROUTE4=m
276CONFIG_NET_CLS_FW=m
277CONFIG_NET_CLS_U32=m
278CONFIG_CLS_U32_MARK=y
279CONFIG_NET_CLS_RSVP=m
280CONFIG_NET_CLS_RSVP6=m
281CONFIG_NET_CLS_FLOW=m
282CONFIG_NET_EMATCH=y
283CONFIG_NET_EMATCH_CMP=m
284CONFIG_NET_EMATCH_NBYTE=m
285CONFIG_NET_EMATCH_U32=m
286CONFIG_NET_EMATCH_META=m
287CONFIG_NET_EMATCH_TEXT=m
288CONFIG_NET_CLS_ACT=y
289CONFIG_NET_ACT_POLICE=m
290CONFIG_NET_ACT_GACT=m
291CONFIG_GACT_PROB=y
292CONFIG_NET_ACT_MIRRED=m
293CONFIG_NET_ACT_IPT=m
294CONFIG_NET_ACT_NAT=m
295CONFIG_NET_ACT_PEDIT=m
296CONFIG_NET_ACT_SIMP=m
297CONFIG_NET_ACT_SKBEDIT=m
298CONFIG_DCB=y
299CONFIG_NET_PKTGEN=m
300# CONFIG_WIRELESS is not set
301CONFIG_DEVTMPFS=y
302CONFIG_DEVTMPFS_MOUNT=y
303# CONFIG_STANDALONE is not set
304CONFIG_CONNECTOR=y
305CONFIG_MTD=m
306CONFIG_BLK_DEV_LOOP=y
307CONFIG_BLK_DEV_CRYPTOLOOP=m
308CONFIG_BLK_DEV_NBD=m
309CONFIG_BLK_DEV_OSD=m
310CONFIG_BLK_DEV_RAM=y
311CONFIG_BLK_DEV_RAM_SIZE=65536
312CONFIG_CDROM_PKTCDVD=y
313CONFIG_MISC_DEVICES=y
314CONFIG_RAID_ATTRS=m
315CONFIG_SCSI=y
316CONFIG_SCSI_TGT=m
317CONFIG_BLK_DEV_SD=y
318CONFIG_CHR_DEV_ST=m
319CONFIG_CHR_DEV_OSST=m
320CONFIG_BLK_DEV_SR=y
321CONFIG_CHR_DEV_SG=y
322CONFIG_CHR_DEV_SCH=m
323CONFIG_SCSI_MULTI_LUN=y
324CONFIG_SCSI_CONSTANTS=y
325CONFIG_SCSI_LOGGING=y
326CONFIG_SCSI_SCAN_ASYNC=y
327CONFIG_SCSI_SPI_ATTRS=m
328CONFIG_SCSI_FC_TGT_ATTRS=y
329CONFIG_SCSI_SAS_LIBSAS=m
330CONFIG_SCSI_SRP_ATTRS=m
331CONFIG_SCSI_SRP_TGT_ATTRS=y
332CONFIG_ISCSI_TCP=m
333CONFIG_LIBFCOE=m
334CONFIG_SCSI_DEBUG=m
335CONFIG_SCSI_DH=y
336CONFIG_SCSI_DH_RDAC=m
337CONFIG_SCSI_DH_HP_SW=m
338CONFIG_SCSI_DH_EMC=m
339CONFIG_SCSI_DH_ALUA=m
340CONFIG_SCSI_OSD_INITIATOR=m
341CONFIG_SCSI_OSD_ULD=m
342# CONFIG_INPUT_MOUSEDEV is not set
343CONFIG_INPUT_EVDEV=y
344CONFIG_INPUT_EVBUG=m
345# CONFIG_INPUT_KEYBOARD is not set
346# CONFIG_INPUT_MOUSE is not set
347# CONFIG_SERIO_I8042 is not set
348CONFIG_SERIO_SERPORT=m
349CONFIG_SERIO_LIBPS2=y
350CONFIG_SERIO_RAW=m
351CONFIG_VT_HW_CONSOLE_BINDING=y
352CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
353CONFIG_LEGACY_PTY_COUNT=0
354CONFIG_SERIAL_NONSTANDARD=y
355CONFIG_N_HDLC=m
356# CONFIG_DEVKMEM is not set
357CONFIG_STALDRV=y
358CONFIG_SERIAL_8250=y
359CONFIG_SERIAL_8250_CONSOLE=y
360CONFIG_SERIAL_8250_NR_UARTS=48
361CONFIG_SERIAL_8250_EXTENDED=y
362CONFIG_SERIAL_8250_MANY_PORTS=y
363CONFIG_SERIAL_8250_SHARE_IRQ=y
364CONFIG_SERIAL_8250_RSA=y
365CONFIG_HW_RANDOM=y
366CONFIG_HW_RANDOM_TIMERIOMEM=m
367CONFIG_RAW_DRIVER=m
368# CONFIG_HWMON is not set
369# CONFIG_VGA_CONSOLE is not set
370# CONFIG_HID_SUPPORT is not set
371# CONFIG_USB_SUPPORT is not set
372CONFIG_UIO=y
373CONFIG_UIO_PDRV=m
374CONFIG_UIO_PDRV_GENIRQ=m
375CONFIG_EXT2_FS=y
376CONFIG_EXT2_FS_XATTR=y
377CONFIG_EXT2_FS_POSIX_ACL=y
378CONFIG_EXT2_FS_SECURITY=y
379CONFIG_EXT3_FS=y
380CONFIG_EXT3_FS_POSIX_ACL=y
381CONFIG_EXT3_FS_SECURITY=y
382CONFIG_EXT4_FS=y
383CONFIG_EXT4_FS_POSIX_ACL=y
384CONFIG_EXT4_FS_SECURITY=y
385CONFIG_GFS2_FS=m
386CONFIG_GFS2_FS_LOCKING_DLM=y
387CONFIG_OCFS2_FS=m
388CONFIG_BTRFS_FS=m
389CONFIG_BTRFS_FS_POSIX_ACL=y
390CONFIG_NILFS2_FS=m
391CONFIG_QUOTA_NETLINK_INTERFACE=y
392# CONFIG_PRINT_QUOTA_WARNING is not set
393CONFIG_QFMT_V1=m
394CONFIG_QFMT_V2=m
395CONFIG_AUTOFS4_FS=m
396CONFIG_FUSE_FS=y
397CONFIG_CUSE=m
398CONFIG_FSCACHE=m
399CONFIG_FSCACHE_STATS=y
400CONFIG_FSCACHE_HISTOGRAM=y
401CONFIG_CACHEFILES=m
402CONFIG_ISO9660_FS=m
403CONFIG_JOLIET=y
404CONFIG_ZISOFS=y
405CONFIG_UDF_FS=m
406CONFIG_MSDOS_FS=m
407CONFIG_VFAT_FS=m
408CONFIG_NTFS_FS=m
409CONFIG_PROC_KCORE=y
410CONFIG_TMPFS=y
411CONFIG_TMPFS_POSIX_ACL=y
412CONFIG_CONFIGFS_FS=y
413CONFIG_ADFS_FS=m
414CONFIG_AFFS_FS=m
415CONFIG_ECRYPT_FS=y
416CONFIG_HFS_FS=m
417CONFIG_HFSPLUS_FS=m
418CONFIG_BEFS_FS=m
419CONFIG_BFS_FS=m
420CONFIG_EFS_FS=m
421CONFIG_CRAMFS=m
422CONFIG_SQUASHFS=m
423CONFIG_VXFS_FS=m
424CONFIG_MINIX_FS=m
425CONFIG_OMFS_FS=m
426CONFIG_HPFS_FS=m
427CONFIG_QNX4FS_FS=m
428CONFIG_ROMFS_FS=m
429CONFIG_SYSV_FS=m
430CONFIG_UFS_FS=m
431CONFIG_EXOFS_FS=m
432CONFIG_NFS_FS=m
433CONFIG_NFS_V3=y
434CONFIG_NFS_V3_ACL=y
435CONFIG_NFS_V4=y
436CONFIG_NFS_FSCACHE=y
437CONFIG_NFSD=m
438CONFIG_NFSD_V3_ACL=y
439CONFIG_NFSD_V4=y
440CONFIG_CIFS=m
441CONFIG_CIFS_WEAK_PW_HASH=y
442CONFIG_CIFS_UPCALL=y
443CONFIG_CIFS_XATTR=y
444CONFIG_CIFS_POSIX=y
445CONFIG_CIFS_DFS_UPCALL=y
446CONFIG_CIFS_EXPERIMENTAL=y
447CONFIG_NCP_FS=m
448CONFIG_NCPFS_PACKET_SIGNING=y
449CONFIG_NCPFS_IOCTL_LOCKING=y
450CONFIG_NCPFS_STRONG=y
451CONFIG_NCPFS_NFS_NS=y
452CONFIG_NCPFS_OS2_NS=y
453CONFIG_NCPFS_NLS=y
454CONFIG_NCPFS_EXTRAS=y
455CONFIG_CODA_FS=m
456CONFIG_AFS_FS=m
457CONFIG_PARTITION_ADVANCED=y
458CONFIG_ACORN_PARTITION=y
459CONFIG_ACORN_PARTITION_ICS=y
460CONFIG_ACORN_PARTITION_RISCIX=y
461CONFIG_OSF_PARTITION=y
462CONFIG_AMIGA_PARTITION=y
463CONFIG_ATARI_PARTITION=y
464CONFIG_MAC_PARTITION=y
465CONFIG_BSD_DISKLABEL=y
466CONFIG_MINIX_SUBPARTITION=y
467CONFIG_SOLARIS_X86_PARTITION=y
468CONFIG_UNIXWARE_DISKLABEL=y
469CONFIG_LDM_PARTITION=y
470CONFIG_SGI_PARTITION=y
471CONFIG_ULTRIX_PARTITION=y
472CONFIG_SUN_PARTITION=y
473CONFIG_KARMA_PARTITION=y
474CONFIG_EFI_PARTITION=y
475CONFIG_SYSV68_PARTITION=y
476CONFIG_NLS=y
477CONFIG_NLS_DEFAULT="cp437"
478CONFIG_NLS_CODEPAGE_437=m
479CONFIG_NLS_CODEPAGE_737=m
480CONFIG_NLS_CODEPAGE_775=m
481CONFIG_NLS_CODEPAGE_850=m
482CONFIG_NLS_CODEPAGE_852=m
483CONFIG_NLS_CODEPAGE_855=m
484CONFIG_NLS_CODEPAGE_857=m
485CONFIG_NLS_CODEPAGE_860=m
486CONFIG_NLS_CODEPAGE_861=m
487CONFIG_NLS_CODEPAGE_862=m
488CONFIG_NLS_CODEPAGE_863=m
489CONFIG_NLS_CODEPAGE_864=m
490CONFIG_NLS_CODEPAGE_865=m
491CONFIG_NLS_CODEPAGE_866=m
492CONFIG_NLS_CODEPAGE_869=m
493CONFIG_NLS_CODEPAGE_936=m
494CONFIG_NLS_CODEPAGE_950=m
495CONFIG_NLS_CODEPAGE_932=m
496CONFIG_NLS_CODEPAGE_949=m
497CONFIG_NLS_CODEPAGE_874=m
498CONFIG_NLS_ISO8859_8=m
499CONFIG_NLS_CODEPAGE_1250=m
500CONFIG_NLS_CODEPAGE_1251=m
501CONFIG_NLS_ASCII=m
502CONFIG_NLS_ISO8859_1=m
503CONFIG_NLS_ISO8859_2=m
504CONFIG_NLS_ISO8859_3=m
505CONFIG_NLS_ISO8859_4=m
506CONFIG_NLS_ISO8859_5=m
507CONFIG_NLS_ISO8859_6=m
508CONFIG_NLS_ISO8859_7=m
509CONFIG_NLS_ISO8859_9=m
510CONFIG_NLS_ISO8859_13=m
511CONFIG_NLS_ISO8859_14=m
512CONFIG_NLS_ISO8859_15=m
513CONFIG_NLS_KOI8_R=m
514CONFIG_NLS_KOI8_U=m
515CONFIG_PRINTK_TIME=y
516# CONFIG_ENABLE_WARN_DEPRECATED is not set
517# CONFIG_ENABLE_MUST_CHECK is not set
518CONFIG_UNUSED_SYMBOLS=y
519CONFIG_DEBUG_KERNEL=y
520CONFIG_DETECT_HUNG_TASK=y
521CONFIG_SCHEDSTATS=y
522CONFIG_TIMER_STATS=y
523CONFIG_DEBUG_INFO=y
524CONFIG_DEBUG_MEMORY_INIT=y
525CONFIG_SYSCTL_SYSCALL_CHECK=y
526CONFIG_SCHED_TRACER=y
527CONFIG_BLK_DEV_IO_TRACE=y
528CONFIG_KGDB=y
529CONFIG_SECURITY=y
530CONFIG_SECURITY_NETWORK=y
531CONFIG_LSM_MMAP_MIN_ADDR=0
532CONFIG_SECURITY_SELINUX=y
533CONFIG_SECURITY_SELINUX_BOOTPARAM=y
534CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
535CONFIG_SECURITY_SELINUX_DISABLE=y
536CONFIG_SECURITY_SMACK=y
537CONFIG_SECURITY_TOMOYO=y
538CONFIG_CRYPTO_NULL=m
539CONFIG_CRYPTO_CRYPTD=m
540CONFIG_CRYPTO_TEST=m
541CONFIG_CRYPTO_CCM=m
542CONFIG_CRYPTO_GCM=m
543CONFIG_CRYPTO_CTS=m
544CONFIG_CRYPTO_LRW=m
545CONFIG_CRYPTO_PCBC=m
546CONFIG_CRYPTO_XTS=m
547CONFIG_CRYPTO_HMAC=y
548CONFIG_CRYPTO_XCBC=m
549CONFIG_CRYPTO_VMAC=m
550CONFIG_CRYPTO_MICHAEL_MIC=m
551CONFIG_CRYPTO_RMD128=m
552CONFIG_CRYPTO_RMD160=m
553CONFIG_CRYPTO_RMD256=m
554CONFIG_CRYPTO_RMD320=m
555CONFIG_CRYPTO_SHA256=m
556CONFIG_CRYPTO_SHA512=m
557CONFIG_CRYPTO_TGR192=m
558CONFIG_CRYPTO_WP512=m
559CONFIG_CRYPTO_ANUBIS=m
560CONFIG_CRYPTO_BLOWFISH=m
561CONFIG_CRYPTO_CAMELLIA=m
562CONFIG_CRYPTO_CAST5=m
563CONFIG_CRYPTO_CAST6=m
564CONFIG_CRYPTO_FCRYPT=m
565CONFIG_CRYPTO_KHAZAD=m
566CONFIG_CRYPTO_SALSA20=m
567CONFIG_CRYPTO_SEED=m
568CONFIG_CRYPTO_SERPENT=m
569CONFIG_CRYPTO_TEA=m
570CONFIG_CRYPTO_TWOFISH=m
571CONFIG_CRYPTO_ZLIB=m
572CONFIG_CRYPTO_LZO=m
573CONFIG_CRC_CCITT=m
574CONFIG_CRC7=m
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 650ac9ba734c..b4db69fbc40c 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -17,6 +17,6 @@
17#define SMP_CACHE_SHIFT L1_CACHE_SHIFT 17#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
18#define SMP_CACHE_BYTES L1_CACHE_BYTES 18#define SMP_CACHE_BYTES L1_CACHE_BYTES
19 19
20#define __read_mostly __attribute__((__section__(".data.read_mostly"))) 20#define __read_mostly __attribute__((__section__(".data..read_mostly")))
21 21
22#endif /* _ASM_CACHE_H */ 22#endif /* _ASM_CACHE_H */
diff --git a/arch/mips/include/asm/cevt-r4k.h b/arch/mips/include/asm/cevt-r4k.h
index fa4328f9124f..65f9bdd02f1f 100644
--- a/arch/mips/include/asm/cevt-r4k.h
+++ b/arch/mips/include/asm/cevt-r4k.h
@@ -14,6 +14,9 @@
14#ifndef __ASM_CEVT_R4K_H 14#ifndef __ASM_CEVT_R4K_H
15#define __ASM_CEVT_R4K_H 15#define __ASM_CEVT_R4K_H
16 16
17#include <linux/clockchips.h>
18#include <asm/time.h>
19
17DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); 20DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
18 21
19void mips_event_handler(struct clock_event_device *dev); 22void mips_event_handler(struct clock_event_device *dev);
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 86877539c6e8..34c0d3cb116f 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -33,6 +33,7 @@
33#define PRID_COMP_TOSHIBA 0x070000 33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000 34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000 35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_NETLOGIC 0x0c0000
36#define PRID_COMP_CAVIUM 0x0d0000 37#define PRID_COMP_CAVIUM 0x0d0000
37#define PRID_COMP_INGENIC 0xd00000 38#define PRID_COMP_INGENIC 0xd00000
38 39
@@ -142,6 +143,31 @@
142#define PRID_IMP_JZRISC 0x0200 143#define PRID_IMP_JZRISC 0x0200
143 144
144/* 145/*
146 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
147 */
148#define PRID_IMP_NETLOGIC_XLR732 0x0000
149#define PRID_IMP_NETLOGIC_XLR716 0x0200
150#define PRID_IMP_NETLOGIC_XLR532 0x0900
151#define PRID_IMP_NETLOGIC_XLR308 0x0600
152#define PRID_IMP_NETLOGIC_XLR532C 0x0800
153#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
154#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
155#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
156#define PRID_IMP_NETLOGIC_XLS608 0x8000
157#define PRID_IMP_NETLOGIC_XLS408 0x8800
158#define PRID_IMP_NETLOGIC_XLS404 0x8c00
159#define PRID_IMP_NETLOGIC_XLS208 0x8e00
160#define PRID_IMP_NETLOGIC_XLS204 0x8f00
161#define PRID_IMP_NETLOGIC_XLS108 0xce00
162#define PRID_IMP_NETLOGIC_XLS104 0xcf00
163#define PRID_IMP_NETLOGIC_XLS616B 0x4000
164#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
165#define PRID_IMP_NETLOGIC_XLS416B 0x4400
166#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
167#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
168#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
169
170/*
145 * Definitions for 7:0 on legacy processors 171 * Definitions for 7:0 on legacy processors
146 */ 172 */
147 173
@@ -234,6 +260,7 @@ enum cpu_type_enum {
234 */ 260 */
235 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 261 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
236 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 262 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
263 CPU_XLR,
237 264
238 CPU_LAST 265 CPU_LAST
239}; 266};
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 655f849bd08d..7aa37ddfca4b 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -5,7 +5,9 @@
5#include <asm/cache.h> 5#include <asm/cache.h>
6#include <asm-generic/dma-coherent.h> 6#include <asm-generic/dma-coherent.h>
7 7
8#ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */
8#include <dma-coherence.h> 9#include <dma-coherence.h>
10#endif
9 11
10extern struct dma_map_ops *mips_dma_map_ops; 12extern struct dma_map_ops *mips_dma_map_ops;
11 13
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index f5e856015329..c565b7c3f0b5 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -70,6 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, 70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
71 unsigned long addr, pte_t *ptep) 71 unsigned long addr, pte_t *ptep)
72{ 72{
73 flush_tlb_mm(vma->vm_mm);
73} 74}
74 75
75static inline int huge_pte_none(pte_t pte) 76static inline int huge_pte_none(pte_t pte)
diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h
index 7622ccf75076..1881b316ca45 100644
--- a/arch/mips/include/asm/jump_label.h
+++ b/arch/mips/include/asm/jump_label.h
@@ -20,16 +20,18 @@
20#define WORD_INSN ".word" 20#define WORD_INSN ".word"
21#endif 21#endif
22 22
23#define JUMP_LABEL(key, label) \ 23static __always_inline bool arch_static_branch(struct jump_label_key *key)
24 do { \ 24{
25 asm goto("1:\tnop\n\t" \ 25 asm goto("1:\tnop\n\t"
26 "nop\n\t" \ 26 "nop\n\t"
27 ".pushsection __jump_table, \"a\"\n\t" \ 27 ".pushsection __jump_table, \"aw\"\n\t"
28 WORD_INSN " 1b, %l[" #label "], %0\n\t" \ 28 WORD_INSN " 1b, %l[l_yes], %0\n\t"
29 ".popsection\n\t" \ 29 ".popsection\n\t"
30 : : "i" (key) : : label); \ 30 : : "i" (key) : : l_yes);
31 } while (0) 31 return false;
32 32l_yes:
33 return true;
34}
33 35
34#endif /* __KERNEL__ */ 36#endif /* __KERNEL__ */
35 37
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index a6976619160a..f260ebed713b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -161,6 +161,45 @@ static inline int alchemy_get_cputype(void)
161 return ALCHEMY_CPU_UNKNOWN; 161 return ALCHEMY_CPU_UNKNOWN;
162} 162}
163 163
164/* return number of uarts on a given cputype */
165static inline int alchemy_get_uarts(int type)
166{
167 switch (type) {
168 case ALCHEMY_CPU_AU1000:
169 return 4;
170 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200:
172 return 2;
173 case ALCHEMY_CPU_AU1100:
174 case ALCHEMY_CPU_AU1550:
175 return 3;
176 }
177 return 0;
178}
179
180/* enable an UART block if it isn't already */
181static inline void alchemy_uart_enable(u32 uart_phys)
182{
183 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
184
185 /* reset, enable clock, deassert reset */
186 if ((__raw_readl(addr + 0x100) & 3) != 3) {
187 __raw_writel(0, addr + 0x100);
188 wmb();
189 __raw_writel(1, addr + 0x100);
190 wmb();
191 }
192 __raw_writel(3, addr + 0x100);
193 wmb();
194}
195
196static inline void alchemy_uart_disable(u32 uart_phys)
197{
198 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
199 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
200 wmb();
201}
202
164static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) 203static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
165{ 204{
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys); 205 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
@@ -180,6 +219,20 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
180 wmb(); 219 wmb();
181} 220}
182 221
222/* return number of ethernet MACs on a given cputype */
223static inline int alchemy_get_macs(int type)
224{
225 switch (type) {
226 case ALCHEMY_CPU_AU1000:
227 case ALCHEMY_CPU_AU1500:
228 case ALCHEMY_CPU_AU1550:
229 return 2;
230 case ALCHEMY_CPU_AU1100:
231 return 1;
232 }
233 return 0;
234}
235
183/* arch/mips/au1000/common/clocks.c */ 236/* arch/mips/au1000/common/clocks.c */
184extern void set_au1x00_speed(unsigned int new_freq); 237extern void set_au1x00_speed(unsigned int new_freq);
185extern unsigned int get_au1x00_speed(void); 238extern unsigned int get_au1x00_speed(void);
@@ -630,38 +683,42 @@ enum soc_au1200_ints {
630 683
631/* 684/*
632 * Physical base addresses for integrated peripherals 685 * Physical base addresses for integrated peripherals
686 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
633 */ 687 */
634 688
689#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
690#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */
691#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
692#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
693#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
694#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
695#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */
696#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
697#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
698#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
699#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
700#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
701#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
702#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
703#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
704#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
705#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
706#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
707#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */
708#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
709#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
710#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
711#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
712#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
713
714
635#ifdef CONFIG_SOC_AU1000 715#ifdef CONFIG_SOC_AU1000
636#define MEM_PHYS_ADDR 0x14000000 716#define MEM_PHYS_ADDR 0x14000000
637#define STATIC_MEM_PHYS_ADDR 0x14001000 717#define STATIC_MEM_PHYS_ADDR 0x14001000
638#define DMA0_PHYS_ADDR 0x14002000
639#define DMA1_PHYS_ADDR 0x14002100
640#define DMA2_PHYS_ADDR 0x14002200
641#define DMA3_PHYS_ADDR 0x14002300
642#define DMA4_PHYS_ADDR 0x14002400
643#define DMA5_PHYS_ADDR 0x14002500
644#define DMA6_PHYS_ADDR 0x14002600
645#define DMA7_PHYS_ADDR 0x14002700
646#define IC0_PHYS_ADDR 0x10400000
647#define IC1_PHYS_ADDR 0x11800000
648#define AC97_PHYS_ADDR 0x10000000
649#define USBH_PHYS_ADDR 0x10100000 718#define USBH_PHYS_ADDR 0x10100000
650#define USBD_PHYS_ADDR 0x10200000
651#define IRDA_PHYS_ADDR 0x10300000 719#define IRDA_PHYS_ADDR 0x10300000
652#define MAC0_PHYS_ADDR 0x10500000
653#define MAC1_PHYS_ADDR 0x10510000
654#define MACEN_PHYS_ADDR 0x10520000
655#define MACDMA0_PHYS_ADDR 0x14004000
656#define MACDMA1_PHYS_ADDR 0x14004200
657#define I2S_PHYS_ADDR 0x11000000
658#define UART0_PHYS_ADDR 0x11100000
659#define UART1_PHYS_ADDR 0x11200000
660#define UART2_PHYS_ADDR 0x11300000
661#define UART3_PHYS_ADDR 0x11400000
662#define SSI0_PHYS_ADDR 0x11600000 720#define SSI0_PHYS_ADDR 0x11600000
663#define SSI1_PHYS_ADDR 0x11680000 721#define SSI1_PHYS_ADDR 0x11680000
664#define SYS_PHYS_ADDR 0x11900000
665#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 722#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
666#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 723#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
667#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 724#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
@@ -672,30 +729,8 @@ enum soc_au1200_ints {
672#ifdef CONFIG_SOC_AU1500 729#ifdef CONFIG_SOC_AU1500
673#define MEM_PHYS_ADDR 0x14000000 730#define MEM_PHYS_ADDR 0x14000000
674#define STATIC_MEM_PHYS_ADDR 0x14001000 731#define STATIC_MEM_PHYS_ADDR 0x14001000
675#define DMA0_PHYS_ADDR 0x14002000
676#define DMA1_PHYS_ADDR 0x14002100
677#define DMA2_PHYS_ADDR 0x14002200
678#define DMA3_PHYS_ADDR 0x14002300
679#define DMA4_PHYS_ADDR 0x14002400
680#define DMA5_PHYS_ADDR 0x14002500
681#define DMA6_PHYS_ADDR 0x14002600
682#define DMA7_PHYS_ADDR 0x14002700
683#define IC0_PHYS_ADDR 0x10400000
684#define IC1_PHYS_ADDR 0x11800000
685#define AC97_PHYS_ADDR 0x10000000
686#define USBH_PHYS_ADDR 0x10100000 732#define USBH_PHYS_ADDR 0x10100000
687#define USBD_PHYS_ADDR 0x10200000
688#define PCI_PHYS_ADDR 0x14005000 733#define PCI_PHYS_ADDR 0x14005000
689#define MAC0_PHYS_ADDR 0x11500000
690#define MAC1_PHYS_ADDR 0x11510000
691#define MACEN_PHYS_ADDR 0x11520000
692#define MACDMA0_PHYS_ADDR 0x14004000
693#define MACDMA1_PHYS_ADDR 0x14004200
694#define I2S_PHYS_ADDR 0x11000000
695#define UART0_PHYS_ADDR 0x11100000
696#define UART3_PHYS_ADDR 0x11400000
697#define GPIO2_PHYS_ADDR 0x11700000
698#define SYS_PHYS_ADDR 0x11900000
699#define PCI_MEM_PHYS_ADDR 0x400000000ULL 734#define PCI_MEM_PHYS_ADDR 0x400000000ULL
700#define PCI_IO_PHYS_ADDR 0x500000000ULL 735#define PCI_IO_PHYS_ADDR 0x500000000ULL
701#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 736#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
@@ -710,34 +745,10 @@ enum soc_au1200_ints {
710#ifdef CONFIG_SOC_AU1100 745#ifdef CONFIG_SOC_AU1100
711#define MEM_PHYS_ADDR 0x14000000 746#define MEM_PHYS_ADDR 0x14000000
712#define STATIC_MEM_PHYS_ADDR 0x14001000 747#define STATIC_MEM_PHYS_ADDR 0x14001000
713#define DMA0_PHYS_ADDR 0x14002000
714#define DMA1_PHYS_ADDR 0x14002100
715#define DMA2_PHYS_ADDR 0x14002200
716#define DMA3_PHYS_ADDR 0x14002300
717#define DMA4_PHYS_ADDR 0x14002400
718#define DMA5_PHYS_ADDR 0x14002500
719#define DMA6_PHYS_ADDR 0x14002600
720#define DMA7_PHYS_ADDR 0x14002700
721#define IC0_PHYS_ADDR 0x10400000
722#define SD0_PHYS_ADDR 0x10600000
723#define SD1_PHYS_ADDR 0x10680000
724#define IC1_PHYS_ADDR 0x11800000
725#define AC97_PHYS_ADDR 0x10000000
726#define USBH_PHYS_ADDR 0x10100000 748#define USBH_PHYS_ADDR 0x10100000
727#define USBD_PHYS_ADDR 0x10200000
728#define IRDA_PHYS_ADDR 0x10300000 749#define IRDA_PHYS_ADDR 0x10300000
729#define MAC0_PHYS_ADDR 0x10500000
730#define MACEN_PHYS_ADDR 0x10520000
731#define MACDMA0_PHYS_ADDR 0x14004000
732#define MACDMA1_PHYS_ADDR 0x14004200
733#define I2S_PHYS_ADDR 0x11000000
734#define UART0_PHYS_ADDR 0x11100000
735#define UART1_PHYS_ADDR 0x11200000
736#define UART3_PHYS_ADDR 0x11400000
737#define SSI0_PHYS_ADDR 0x11600000 750#define SSI0_PHYS_ADDR 0x11600000
738#define SSI1_PHYS_ADDR 0x11680000 751#define SSI1_PHYS_ADDR 0x11680000
739#define GPIO2_PHYS_ADDR 0x11700000
740#define SYS_PHYS_ADDR 0x11900000
741#define LCD_PHYS_ADDR 0x15000000 752#define LCD_PHYS_ADDR 0x15000000
742#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 753#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
743#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 754#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
@@ -749,22 +760,8 @@ enum soc_au1200_ints {
749#ifdef CONFIG_SOC_AU1550 760#ifdef CONFIG_SOC_AU1550
750#define MEM_PHYS_ADDR 0x14000000 761#define MEM_PHYS_ADDR 0x14000000
751#define STATIC_MEM_PHYS_ADDR 0x14001000 762#define STATIC_MEM_PHYS_ADDR 0x14001000
752#define IC0_PHYS_ADDR 0x10400000
753#define IC1_PHYS_ADDR 0x11800000
754#define USBH_PHYS_ADDR 0x14020000 763#define USBH_PHYS_ADDR 0x14020000
755#define USBD_PHYS_ADDR 0x10200000
756#define PCI_PHYS_ADDR 0x14005000 764#define PCI_PHYS_ADDR 0x14005000
757#define MAC0_PHYS_ADDR 0x10500000
758#define MAC1_PHYS_ADDR 0x10510000
759#define MACEN_PHYS_ADDR 0x10520000
760#define MACDMA0_PHYS_ADDR 0x14004000
761#define MACDMA1_PHYS_ADDR 0x14004200
762#define UART0_PHYS_ADDR 0x11100000
763#define UART1_PHYS_ADDR 0x11200000
764#define UART3_PHYS_ADDR 0x11400000
765#define GPIO2_PHYS_ADDR 0x11700000
766#define SYS_PHYS_ADDR 0x11900000
767#define DDMA_PHYS_ADDR 0x14002000
768#define PE_PHYS_ADDR 0x14008000 765#define PE_PHYS_ADDR 0x14008000
769#define PSC0_PHYS_ADDR 0x11A00000 766#define PSC0_PHYS_ADDR 0x11A00000
770#define PSC1_PHYS_ADDR 0x11B00000 767#define PSC1_PHYS_ADDR 0x11B00000
@@ -786,19 +783,10 @@ enum soc_au1200_ints {
786#define STATIC_MEM_PHYS_ADDR 0x14001000 783#define STATIC_MEM_PHYS_ADDR 0x14001000
787#define AES_PHYS_ADDR 0x10300000 784#define AES_PHYS_ADDR 0x10300000
788#define CIM_PHYS_ADDR 0x14004000 785#define CIM_PHYS_ADDR 0x14004000
789#define IC0_PHYS_ADDR 0x10400000
790#define IC1_PHYS_ADDR 0x11800000
791#define USBM_PHYS_ADDR 0x14020000 786#define USBM_PHYS_ADDR 0x14020000
792#define USBH_PHYS_ADDR 0x14020100 787#define USBH_PHYS_ADDR 0x14020100
793#define UART0_PHYS_ADDR 0x11100000
794#define UART1_PHYS_ADDR 0x11200000
795#define GPIO2_PHYS_ADDR 0x11700000
796#define SYS_PHYS_ADDR 0x11900000
797#define DDMA_PHYS_ADDR 0x14002000
798#define PSC0_PHYS_ADDR 0x11A00000 788#define PSC0_PHYS_ADDR 0x11A00000
799#define PSC1_PHYS_ADDR 0x11B00000 789#define PSC1_PHYS_ADDR 0x11B00000
800#define SD0_PHYS_ADDR 0x10600000
801#define SD1_PHYS_ADDR 0x10680000
802#define LCD_PHYS_ADDR 0x15000000 790#define LCD_PHYS_ADDR 0x15000000
803#define SWCNT_PHYS_ADDR 0x1110010C 791#define SWCNT_PHYS_ADDR 0x1110010C
804#define MAEFE_PHYS_ADDR 0x14012000 792#define MAEFE_PHYS_ADDR 0x14012000
@@ -835,183 +823,43 @@ enum soc_au1200_ints {
835#endif 823#endif
836 824
837 825
838/* Interrupt Controller register offsets */
839#define IC_CFG0RD 0x40
840#define IC_CFG0SET 0x40
841#define IC_CFG0CLR 0x44
842#define IC_CFG1RD 0x48
843#define IC_CFG1SET 0x48
844#define IC_CFG1CLR 0x4C
845#define IC_CFG2RD 0x50
846#define IC_CFG2SET 0x50
847#define IC_CFG2CLR 0x54
848#define IC_REQ0INT 0x54
849#define IC_SRCRD 0x58
850#define IC_SRCSET 0x58
851#define IC_SRCCLR 0x5C
852#define IC_REQ1INT 0x5C
853#define IC_ASSIGNRD 0x60
854#define IC_ASSIGNSET 0x60
855#define IC_ASSIGNCLR 0x64
856#define IC_WAKERD 0x68
857#define IC_WAKESET 0x68
858#define IC_WAKECLR 0x6C
859#define IC_MASKRD 0x70
860#define IC_MASKSET 0x70
861#define IC_MASKCLR 0x74
862#define IC_RISINGRD 0x78
863#define IC_RISINGCLR 0x78
864#define IC_FALLINGRD 0x7C
865#define IC_FALLINGCLR 0x7C
866#define IC_TESTBIT 0x80
867
868
869/* Interrupt Controller 0 */
870#define IC0_CFG0RD 0xB0400040
871#define IC0_CFG0SET 0xB0400040
872#define IC0_CFG0CLR 0xB0400044
873
874#define IC0_CFG1RD 0xB0400048
875#define IC0_CFG1SET 0xB0400048
876#define IC0_CFG1CLR 0xB040004C
877
878#define IC0_CFG2RD 0xB0400050
879#define IC0_CFG2SET 0xB0400050
880#define IC0_CFG2CLR 0xB0400054
881
882#define IC0_REQ0INT 0xB0400054
883#define IC0_SRCRD 0xB0400058
884#define IC0_SRCSET 0xB0400058
885#define IC0_SRCCLR 0xB040005C
886#define IC0_REQ1INT 0xB040005C
887
888#define IC0_ASSIGNRD 0xB0400060
889#define IC0_ASSIGNSET 0xB0400060
890#define IC0_ASSIGNCLR 0xB0400064
891
892#define IC0_WAKERD 0xB0400068
893#define IC0_WAKESET 0xB0400068
894#define IC0_WAKECLR 0xB040006C
895
896#define IC0_MASKRD 0xB0400070
897#define IC0_MASKSET 0xB0400070
898#define IC0_MASKCLR 0xB0400074
899
900#define IC0_RISINGRD 0xB0400078
901#define IC0_RISINGCLR 0xB0400078
902#define IC0_FALLINGRD 0xB040007C
903#define IC0_FALLINGCLR 0xB040007C
904
905#define IC0_TESTBIT 0xB0400080
906
907/* Interrupt Controller 1 */
908#define IC1_CFG0RD 0xB1800040
909#define IC1_CFG0SET 0xB1800040
910#define IC1_CFG0CLR 0xB1800044
911
912#define IC1_CFG1RD 0xB1800048
913#define IC1_CFG1SET 0xB1800048
914#define IC1_CFG1CLR 0xB180004C
915
916#define IC1_CFG2RD 0xB1800050
917#define IC1_CFG2SET 0xB1800050
918#define IC1_CFG2CLR 0xB1800054
919
920#define IC1_REQ0INT 0xB1800054
921#define IC1_SRCRD 0xB1800058
922#define IC1_SRCSET 0xB1800058
923#define IC1_SRCCLR 0xB180005C
924#define IC1_REQ1INT 0xB180005C
925
926#define IC1_ASSIGNRD 0xB1800060
927#define IC1_ASSIGNSET 0xB1800060
928#define IC1_ASSIGNCLR 0xB1800064
929
930#define IC1_WAKERD 0xB1800068
931#define IC1_WAKESET 0xB1800068
932#define IC1_WAKECLR 0xB180006C
933
934#define IC1_MASKRD 0xB1800070
935#define IC1_MASKSET 0xB1800070
936#define IC1_MASKCLR 0xB1800074
937
938#define IC1_RISINGRD 0xB1800078
939#define IC1_RISINGCLR 0xB1800078
940#define IC1_FALLINGRD 0xB180007C
941#define IC1_FALLINGCLR 0xB180007C
942
943#define IC1_TESTBIT 0xB1800080
944 826
945 827
946/* Au1000 */ 828/* Au1000 */
947#ifdef CONFIG_SOC_AU1000 829#ifdef CONFIG_SOC_AU1000
948 830
949#define UART0_ADDR 0xB1100000
950#define UART3_ADDR 0xB1400000
951
952#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 831#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
953#define USB_HOST_CONFIG 0xB017FFFC 832#define USB_HOST_CONFIG 0xB017FFFC
954#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT 833#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
955
956#define AU1000_ETH0_BASE 0xB0500000
957#define AU1000_ETH1_BASE 0xB0510000
958#define AU1000_MAC0_ENABLE 0xB0520000
959#define AU1000_MAC1_ENABLE 0xB0520004
960#define NUM_ETH_INTERFACES 2
961#endif /* CONFIG_SOC_AU1000 */ 834#endif /* CONFIG_SOC_AU1000 */
962 835
963/* Au1500 */ 836/* Au1500 */
964#ifdef CONFIG_SOC_AU1500 837#ifdef CONFIG_SOC_AU1500
965 838
966#define UART0_ADDR 0xB1100000
967#define UART3_ADDR 0xB1400000
968
969#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 839#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
970#define USB_HOST_CONFIG 0xB017fffc 840#define USB_HOST_CONFIG 0xB017fffc
971#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT 841#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
972
973#define AU1500_ETH0_BASE 0xB1500000
974#define AU1500_ETH1_BASE 0xB1510000
975#define AU1500_MAC0_ENABLE 0xB1520000
976#define AU1500_MAC1_ENABLE 0xB1520004
977#define NUM_ETH_INTERFACES 2
978#endif /* CONFIG_SOC_AU1500 */ 842#endif /* CONFIG_SOC_AU1500 */
979 843
980/* Au1100 */ 844/* Au1100 */
981#ifdef CONFIG_SOC_AU1100 845#ifdef CONFIG_SOC_AU1100
982 846
983#define UART0_ADDR 0xB1100000
984#define UART3_ADDR 0xB1400000
985
986#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 847#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
987#define USB_HOST_CONFIG 0xB017FFFC 848#define USB_HOST_CONFIG 0xB017FFFC
988#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT 849#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
989
990#define AU1100_ETH0_BASE 0xB0500000
991#define AU1100_MAC0_ENABLE 0xB0520000
992#define NUM_ETH_INTERFACES 1
993#endif /* CONFIG_SOC_AU1100 */ 850#endif /* CONFIG_SOC_AU1100 */
994 851
995#ifdef CONFIG_SOC_AU1550 852#ifdef CONFIG_SOC_AU1550
996#define UART0_ADDR 0xB1100000
997 853
998#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ 854#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
999#define USB_OHCI_LEN 0x00060000 855#define USB_OHCI_LEN 0x00060000
1000#define USB_HOST_CONFIG 0xB4027ffc 856#define USB_HOST_CONFIG 0xB4027ffc
1001#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT 857#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
1002
1003#define AU1550_ETH0_BASE 0xB0500000
1004#define AU1550_ETH1_BASE 0xB0510000
1005#define AU1550_MAC0_ENABLE 0xB0520000
1006#define AU1550_MAC1_ENABLE 0xB0520004
1007#define NUM_ETH_INTERFACES 2
1008#endif /* CONFIG_SOC_AU1550 */ 858#endif /* CONFIG_SOC_AU1550 */
1009 859
1010 860
1011#ifdef CONFIG_SOC_AU1200 861#ifdef CONFIG_SOC_AU1200
1012 862
1013#define UART0_ADDR 0xB1100000
1014
1015#define USB_UOC_BASE 0x14020020 863#define USB_UOC_BASE 0x14020020
1016#define USB_UOC_LEN 0x20 864#define USB_UOC_LEN 0x20
1017#define USB_OHCI_BASE 0x14020100 865#define USB_OHCI_BASE 0x14020100
@@ -1504,22 +1352,6 @@ enum soc_au1200_ints {
1504#define SYS_PINFUNC_S1B (1 << 2) 1352#define SYS_PINFUNC_S1B (1 << 2)
1505#endif 1353#endif
1506 1354
1507#define SYS_TRIOUTRD 0xB1900100
1508#define SYS_TRIOUTCLR 0xB1900100
1509#define SYS_OUTPUTRD 0xB1900108
1510#define SYS_OUTPUTSET 0xB1900108
1511#define SYS_OUTPUTCLR 0xB190010C
1512#define SYS_PINSTATERD 0xB1900110
1513#define SYS_PININPUTEN 0xB1900110
1514
1515/* GPIO2, Au1500, Au1550 only */
1516#define GPIO2_BASE 0xB1700000
1517#define GPIO2_DIR (GPIO2_BASE + 0)
1518#define GPIO2_OUTPUT (GPIO2_BASE + 8)
1519#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1520#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1521#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1522
1523/* Power Management */ 1355/* Power Management */
1524#define SYS_SCRATCH0 0xB1900018 1356#define SYS_SCRATCH0 0xB1900018
1525#define SYS_SCRATCH1 0xB190001C 1357#define SYS_SCRATCH1 0xB190001C
@@ -1635,12 +1467,6 @@ enum soc_au1200_ints {
1635# define AC97C_RS (1 << 1) 1467# define AC97C_RS (1 << 1)
1636# define AC97C_CE (1 << 0) 1468# define AC97C_CE (1 << 0)
1637 1469
1638/* Secure Digital (SD) Controller */
1639#define SD0_XMIT_FIFO 0xB0600000
1640#define SD0_RECV_FIFO 0xB0600004
1641#define SD1_XMIT_FIFO 0xB0680000
1642#define SD1_RECV_FIFO 0xB0680004
1643
1644#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1470#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1645/* Au1500 PCI Controller */ 1471/* Au1500 PCI Controller */
1646#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ 1472#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index c333b4e1cd44..59f5b55b2200 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -37,10 +37,6 @@
37 37
38#define NUM_AU1000_DMA_CHANNELS 8 38#define NUM_AU1000_DMA_CHANNELS 8
39 39
40/* DMA Channel Base Addresses */
41#define DMA_CHANNEL_BASE 0xB4002000
42#define DMA_CHANNEL_LEN 0x00000100
43
44/* DMA Channel Register Offsets */ 40/* DMA Channel Register Offsets */
45#define DMA_MODE_SET 0x00000000 41#define DMA_MODE_SET 0x00000000
46#define DMA_MODE_READ DMA_MODE_SET 42#define DMA_MODE_READ DMA_MODE_SET
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index c8a553a36ba4..2fdacfe85e23 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -37,14 +37,6 @@
37 37
38#ifndef _LANGUAGE_ASSEMBLY 38#ifndef _LANGUAGE_ASSEMBLY
39 39
40/*
41 * The DMA base addresses.
42 * The channels are every 256 bytes (0x0100) from the channel 0 base.
43 * Interrupt status/enable is bits 15:0 for channels 15 to zero.
44 */
45#define DDMA_GLOBAL_BASE 0xb4003000
46#define DDMA_CHANNEL_BASE 0xb4002000
47
48typedef volatile struct dbdma_global { 40typedef volatile struct dbdma_global {
49 u32 ddma_config; 41 u32 ddma_config;
50 u32 ddma_intstat; 42 u32 ddma_intstat;
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 62d2f136d941..1f41a522906d 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -24,6 +24,23 @@
24 24
25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) 25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26 26
27/* GPIO1 registers within SYS_ area */
28#define SYS_TRIOUTRD 0x100
29#define SYS_TRIOUTCLR 0x100
30#define SYS_OUTPUTRD 0x108
31#define SYS_OUTPUTSET 0x108
32#define SYS_OUTPUTCLR 0x10C
33#define SYS_PINSTATERD 0x110
34#define SYS_PININPUTEN 0x110
35
36/* register offsets within GPIO2 block */
37#define GPIO2_DIR 0x00
38#define GPIO2_OUTPUT 0x08
39#define GPIO2_PINSTATE 0x0C
40#define GPIO2_INTENABLE 0x10
41#define GPIO2_ENABLE 0x14
42
43struct gpio;
27 44
28static inline int au1000_gpio1_to_irq(int gpio) 45static inline int au1000_gpio1_to_irq(int gpio)
29{ 46{
@@ -200,23 +217,26 @@ static inline int au1200_irq_to_gpio(int irq)
200 */ 217 */
201static inline void alchemy_gpio1_set_value(int gpio, int v) 218static inline void alchemy_gpio1_set_value(int gpio, int v)
202{ 219{
220 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
203 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 221 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
204 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; 222 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
205 au_writel(mask, r); 223 __raw_writel(mask, base + r);
206 au_sync(); 224 wmb();
207} 225}
208 226
209static inline int alchemy_gpio1_get_value(int gpio) 227static inline int alchemy_gpio1_get_value(int gpio)
210{ 228{
229 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
211 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 230 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
212 return au_readl(SYS_PINSTATERD) & mask; 231 return __raw_readl(base + SYS_PINSTATERD) & mask;
213} 232}
214 233
215static inline int alchemy_gpio1_direction_input(int gpio) 234static inline int alchemy_gpio1_direction_input(int gpio)
216{ 235{
236 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
217 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 237 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
218 au_writel(mask, SYS_TRIOUTCLR); 238 __raw_writel(mask, base + SYS_TRIOUTCLR);
219 au_sync(); 239 wmb();
220 return 0; 240 return 0;
221} 241}
222 242
@@ -257,27 +277,31 @@ static inline int alchemy_gpio1_to_irq(int gpio)
257 */ 277 */
258static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) 278static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
259{ 279{
280 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
260 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); 281 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
261 unsigned long d = au_readl(GPIO2_DIR); 282 unsigned long d = __raw_readl(base + GPIO2_DIR);
283
262 if (to_out) 284 if (to_out)
263 d |= mask; 285 d |= mask;
264 else 286 else
265 d &= ~mask; 287 d &= ~mask;
266 au_writel(d, GPIO2_DIR); 288 __raw_writel(d, base + GPIO2_DIR);
267 au_sync(); 289 wmb();
268} 290}
269 291
270static inline void alchemy_gpio2_set_value(int gpio, int v) 292static inline void alchemy_gpio2_set_value(int gpio, int v)
271{ 293{
294 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
272 unsigned long mask; 295 unsigned long mask;
273 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); 296 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
274 au_writel(mask, GPIO2_OUTPUT); 297 __raw_writel(mask, base + GPIO2_OUTPUT);
275 au_sync(); 298 wmb();
276} 299}
277 300
278static inline int alchemy_gpio2_get_value(int gpio) 301static inline int alchemy_gpio2_get_value(int gpio)
279{ 302{
280 return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); 303 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
304 return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
281} 305}
282 306
283static inline int alchemy_gpio2_direction_input(int gpio) 307static inline int alchemy_gpio2_direction_input(int gpio)
@@ -329,21 +353,23 @@ static inline int alchemy_gpio2_to_irq(int gpio)
329 */ 353 */
330static inline void alchemy_gpio1_input_enable(void) 354static inline void alchemy_gpio1_input_enable(void)
331{ 355{
332 au_writel(0, SYS_PININPUTEN); /* the write op is key */ 356 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
333 au_sync(); 357 __raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
358 wmb();
334} 359}
335 360
336/* GPIO2 shared interrupts and control */ 361/* GPIO2 shared interrupts and control */
337 362
338static inline void __alchemy_gpio2_mod_int(int gpio2, int en) 363static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
339{ 364{
340 unsigned long r = au_readl(GPIO2_INTENABLE); 365 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
366 unsigned long r = __raw_readl(base + GPIO2_INTENABLE);
341 if (en) 367 if (en)
342 r |= 1 << gpio2; 368 r |= 1 << gpio2;
343 else 369 else
344 r &= ~(1 << gpio2); 370 r &= ~(1 << gpio2);
345 au_writel(r, GPIO2_INTENABLE); 371 __raw_writel(r, base + GPIO2_INTENABLE);
346 au_sync(); 372 wmb();
347} 373}
348 374
349/** 375/**
@@ -418,10 +444,11 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
418 */ 444 */
419static inline void alchemy_gpio2_enable(void) 445static inline void alchemy_gpio2_enable(void)
420{ 446{
421 au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */ 447 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
422 au_sync(); 448 __raw_writel(3, base + GPIO2_ENABLE); /* reset, clock enabled */
423 au_writel(1, GPIO2_ENABLE); /* clock enabled */ 449 wmb();
424 au_sync(); 450 __raw_writel(1, base + GPIO2_ENABLE); /* clock enabled */
451 wmb();
425} 452}
426 453
427/** 454/**
@@ -431,8 +458,9 @@ static inline void alchemy_gpio2_enable(void)
431 */ 458 */
432static inline void alchemy_gpio2_disable(void) 459static inline void alchemy_gpio2_disable(void)
433{ 460{
434 au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */ 461 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
435 au_sync(); 462 __raw_writel(2, base + GPIO2_ENABLE); /* reset, clock disabled */
463 wmb();
436} 464}
437 465
438/**********************************************************************/ 466/**********************************************************************/
@@ -556,6 +584,16 @@ static inline void gpio_set_value(int gpio, int v)
556 alchemy_gpio_set_value(gpio, v); 584 alchemy_gpio_set_value(gpio, v);
557} 585}
558 586
587static inline int gpio_get_value_cansleep(unsigned gpio)
588{
589 return gpio_get_value(gpio);
590}
591
592static inline void gpio_set_value_cansleep(unsigned gpio, int value)
593{
594 gpio_set_value(gpio, value);
595}
596
559static inline int gpio_is_valid(int gpio) 597static inline int gpio_is_valid(int gpio)
560{ 598{
561 return alchemy_gpio_is_valid(gpio); 599 return alchemy_gpio_is_valid(gpio);
@@ -581,10 +619,50 @@ static inline int gpio_request(unsigned gpio, const char *label)
581 return 0; 619 return 0;
582} 620}
583 621
622static inline int gpio_request_one(unsigned gpio,
623 unsigned long flags, const char *label)
624{
625 return 0;
626}
627
628static inline int gpio_request_array(struct gpio *array, size_t num)
629{
630 return 0;
631}
632
584static inline void gpio_free(unsigned gpio) 633static inline void gpio_free(unsigned gpio)
585{ 634{
586} 635}
587 636
637static inline void gpio_free_array(struct gpio *array, size_t num)
638{
639}
640
641static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
642{
643 return -ENOSYS;
644}
645
646static inline int gpio_export(unsigned gpio, bool direction_may_change)
647{
648 return -ENOSYS;
649}
650
651static inline int gpio_export_link(struct device *dev, const char *name,
652 unsigned gpio)
653{
654 return -ENOSYS;
655}
656
657static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
658{
659 return -ENOSYS;
660}
661
662static inline void gpio_unexport(unsigned gpio)
663{
664}
665
588#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ 666#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
589 667
590 668
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index 9759588ba3cf..184d5ecb5f51 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -39,8 +39,16 @@ extern int nvram_getenv(char *name, char *val, size_t val_len);
39 39
40static inline void nvram_parse_macaddr(char *buf, u8 *macaddr) 40static inline void nvram_parse_macaddr(char *buf, u8 *macaddr)
41{ 41{
42 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1], 42 if (strchr(buf, ':'))
43 &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); 43 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
44 &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
45 &macaddr[5]);
46 else if (strchr(buf, '-'))
47 sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
48 &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
49 &macaddr[5]);
50 else
51 printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
44} 52}
45 53
46#endif 54#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
index 32978d32561a..ed72e6a26b73 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -88,7 +88,7 @@ struct bcm_tag {
88 char kernel_crc[CRC_LEN]; 88 char kernel_crc[CRC_LEN];
89 /* 228-235: Unused at present */ 89 /* 228-235: Unused at present */
90 char reserved1[8]; 90 char reserved1[8];
91 /* 236-239: CRC32 of header excluding tagVersion */ 91 /* 236-239: CRC32 of header excluding last 20 bytes */
92 char header_crc[CRC_LEN]; 92 char header_crc[CRC_LEN];
93 /* 240-255: Unused at present */ 93 /* 240-255: Unused at present */
94 char reserved2[16]; 94 char reserved2[16];
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 0b2b5eb22e9b..dedef7d2b01f 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,11 @@
63 # CN30XX Disable instruction prefetching 63 # CN30XX Disable instruction prefetching
64 or v0, v0, 0x2000 64 or v0, v0, 0x2000
65skip: 65skip:
66 # First clear off CvmCtl[IPPCI] bit and move the performance
67 # counters interrupt to IRQ 6
68 li v1, ~(7 << 7)
69 and v0, v0, v1
70 ori v0, v0, (6 << 7)
66 # Write the cavium control register 71 # Write the cavium control register
67 dmtc0 v0, CP0_CVMCTL_REG 72 dmtc0 v0, CP0_CVMCTL_REG
68 sync 73 sync
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
new file mode 100644
index 000000000000..ce2f02929d22
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -0,0 +1,63 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8#ifndef _LANTIQ_H__
9#define _LANTIQ_H__
10
11#include <linux/irq.h>
12
13/* generic reg access functions */
14#define ltq_r32(reg) __raw_readl(reg)
15#define ltq_w32(val, reg) __raw_writel(val, reg)
16#define ltq_w32_mask(clear, set, reg) \
17 ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
18#define ltq_r8(reg) __raw_readb(reg)
19#define ltq_w8(val, reg) __raw_writeb(val, reg)
20
21/* register access macros for EBU and CGU */
22#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
23#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
24#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
25#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
26
27extern __iomem void *ltq_ebu_membase;
28extern __iomem void *ltq_cgu_membase;
29
30extern unsigned int ltq_get_cpu_ver(void);
31extern unsigned int ltq_get_soc_type(void);
32
33/* clock speeds */
34#define CLOCK_60M 60000000
35#define CLOCK_83M 83333333
36#define CLOCK_111M 111111111
37#define CLOCK_133M 133333333
38#define CLOCK_167M 166666667
39#define CLOCK_200M 200000000
40#define CLOCK_266M 266666666
41#define CLOCK_333M 333333333
42#define CLOCK_400M 400000000
43
44/* spinlock all ebu i/o */
45extern spinlock_t ebu_lock;
46
47/* some irq helpers */
48extern void ltq_disable_irq(struct irq_data *data);
49extern void ltq_mask_and_ack_irq(struct irq_data *data);
50extern void ltq_enable_irq(struct irq_data *data);
51
52/* find out what caused the last cpu reset */
53extern int ltq_reset_cause(void);
54#define LTQ_RST_CAUSE_WDTRST 0x20
55
56#define IOPORT_RESOURCE_START 0x10000000
57#define IOPORT_RESOURCE_END 0xffffffff
58#define IOMEM_RESOURCE_START 0x10000000
59#define IOMEM_RESOURCE_END 0xffffffff
60#define LTQ_FLASH_START 0x10000000
61#define LTQ_FLASH_MAX 0x04000000
62
63#endif
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
new file mode 100644
index 000000000000..a305f1d0259e
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -0,0 +1,53 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LANTIQ_PLATFORM_H__
10#define _LANTIQ_PLATFORM_H__
11
12#include <linux/mtd/partitions.h>
13#include <linux/socket.h>
14
15/* struct used to pass info to the pci core */
16enum {
17 PCI_CLOCK_INT = 0,
18 PCI_CLOCK_EXT
19};
20
21#define PCI_EXIN0 0x0001
22#define PCI_EXIN1 0x0002
23#define PCI_EXIN2 0x0004
24#define PCI_EXIN3 0x0008
25#define PCI_EXIN4 0x0010
26#define PCI_EXIN5 0x0020
27#define PCI_EXIN_MAX 6
28
29#define PCI_GNT1 0x0040
30#define PCI_GNT2 0x0080
31#define PCI_GNT3 0x0100
32#define PCI_GNT4 0x0200
33
34#define PCI_REQ1 0x0400
35#define PCI_REQ2 0x0800
36#define PCI_REQ3 0x1000
37#define PCI_REQ4 0x2000
38#define PCI_REQ_SHIFT 10
39#define PCI_REQ_MASK 0xf
40
41struct ltq_pci_data {
42 int clock;
43 int gpio;
44 int irq[16];
45};
46
47/* struct used to pass info to network drivers */
48struct ltq_eth_data {
49 struct sockaddr mac;
50 int mii_mode;
51};
52
53#endif
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
new file mode 100644
index 000000000000..01b08ef368d1
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -0,0 +1,24 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 */
7#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
8#define __ASM_MIPS_MACH_LANTIQ_WAR_H
9
10#define R4600_V1_INDEX_ICACHEOP_WAR 0
11#define R4600_V1_HIT_CACHEOP_WAR 0
12#define R4600_V2_HIT_CACHEOP_WAR 0
13#define R5432_CP0_INTERRUPT_WAR 0
14#define BCM1250_M3_WAR 0
15#define SIBYTE_1956_WAR 0
16#define MIPS4K_ICACHE_REFILL_WAR 0
17#define MIPS_CACHE_SYNC_WAR 0
18#define TX49XX_ICACHE_INDEX_INV_WAR 0
19#define RM9000_CDEX_SMP_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h
new file mode 100644
index 000000000000..a1471d2dd0d2
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -0,0 +1,18 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef __LANTIQ_IRQ_H
10#define __LANTIQ_IRQ_H
11
12#include <lantiq_irq.h>
13
14#define NR_IRQS 256
15
16#include_next <irq.h>
17
18#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
new file mode 100644
index 000000000000..b4465a888e20
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -0,0 +1,66 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LANTIQ_XWAY_IRQ_H__
10#define _LANTIQ_XWAY_IRQ_H__
11
12#define INT_NUM_IRQ0 8
13#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
14#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
15#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
16#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
17#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
18#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
19
20#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
21#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
22#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
23
24#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0
25#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2)
26#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3)
27
28#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
29#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
30#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
31
32#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
33#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
34
35#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
36#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
37#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
38
39#define MIPS_CPU_TIMER_IRQ 7
40
41#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
42#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
43#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
44#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
45#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
46#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
47#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
48#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
49#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
50#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
51#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
52#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
53#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
54#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
55#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
56#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
57#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
58#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
59#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
60#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
61
62#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
63
64#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
65
66#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
new file mode 100644
index 000000000000..8a3c6be669d2
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -0,0 +1,141 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_XWAY_H__
10#define _LTQ_XWAY_H__
11
12#ifdef CONFIG_SOC_TYPE_XWAY
13
14#include <lantiq.h>
15
16/* Chip IDs */
17#define SOC_ID_DANUBE1 0x129
18#define SOC_ID_DANUBE2 0x12B
19#define SOC_ID_TWINPASS 0x12D
20#define SOC_ID_AMAZON_SE 0x152
21#define SOC_ID_ARX188 0x16C
22#define SOC_ID_ARX168 0x16D
23#define SOC_ID_ARX182 0x16F
24
25/* SoC Types */
26#define SOC_TYPE_DANUBE 0x01
27#define SOC_TYPE_TWINPASS 0x02
28#define SOC_TYPE_AR9 0x03
29#define SOC_TYPE_VR9 0x04
30#define SOC_TYPE_AMAZON_SE 0x05
31
32/* ASC0/1 - serial port */
33#define LTQ_ASC0_BASE_ADDR 0x1E100400
34#define LTQ_ASC1_BASE_ADDR 0x1E100C00
35#define LTQ_ASC_SIZE 0x400
36
37/* RCU - reset control unit */
38#define LTQ_RCU_BASE_ADDR 0x1F203000
39#define LTQ_RCU_SIZE 0x1000
40
41/* GPTU - general purpose timer unit */
42#define LTQ_GPTU_BASE_ADDR 0x18000300
43#define LTQ_GPTU_SIZE 0x100
44
45/* EBU - external bus unit */
46#define LTQ_EBU_GPIO_START 0x14000000
47#define LTQ_EBU_GPIO_SIZE 0x1000
48
49#define LTQ_EBU_BASE_ADDR 0x1E105300
50#define LTQ_EBU_SIZE 0x100
51
52#define LTQ_EBU_BUSCON0 0x0060
53#define LTQ_EBU_PCC_CON 0x0090
54#define LTQ_EBU_PCC_IEN 0x00A4
55#define LTQ_EBU_PCC_ISTAT 0x00A0
56#define LTQ_EBU_BUSCON1 0x0064
57#define LTQ_EBU_ADDRSEL1 0x0024
58#define EBU_WRDIS 0x80000000
59
60/* CGU - clock generation unit */
61#define LTQ_CGU_BASE_ADDR 0x1F103000
62#define LTQ_CGU_SIZE 0x1000
63
64/* ICU - interrupt control unit */
65#define LTQ_ICU_BASE_ADDR 0x1F880200
66#define LTQ_ICU_SIZE 0x100
67
68/* EIU - external interrupt unit */
69#define LTQ_EIU_BASE_ADDR 0x1F101000
70#define LTQ_EIU_SIZE 0x1000
71
72/* PMU - power management unit */
73#define LTQ_PMU_BASE_ADDR 0x1F102000
74#define LTQ_PMU_SIZE 0x1000
75
76#define PMU_DMA 0x0020
77#define PMU_USB 0x8041
78#define PMU_LED 0x0800
79#define PMU_GPT 0x1000
80#define PMU_PPE 0x2000
81#define PMU_FPI 0x4000
82#define PMU_SWITCH 0x10000000
83
84/* ETOP - ethernet */
85#define LTQ_ETOP_BASE_ADDR 0x1E180000
86#define LTQ_ETOP_SIZE 0x40000
87
88/* DMA */
89#define LTQ_DMA_BASE_ADDR 0x1E104100
90#define LTQ_DMA_SIZE 0x800
91
92/* PCI */
93#define PCI_CR_BASE_ADDR 0x1E105400
94#define PCI_CR_SIZE 0x400
95
96/* WDT */
97#define LTQ_WDT_BASE_ADDR 0x1F8803F0
98#define LTQ_WDT_SIZE 0x10
99
100/* STP - serial to parallel conversion unit */
101#define LTQ_STP_BASE_ADDR 0x1E100BB0
102#define LTQ_STP_SIZE 0x40
103
104/* GPIO */
105#define LTQ_GPIO0_BASE_ADDR 0x1E100B10
106#define LTQ_GPIO1_BASE_ADDR 0x1E100B40
107#define LTQ_GPIO2_BASE_ADDR 0x1E100B70
108#define LTQ_GPIO_SIZE 0x30
109
110/* SSC */
111#define LTQ_SSC_BASE_ADDR 0x1e100800
112#define LTQ_SSC_SIZE 0x100
113
114/* MEI - dsl core */
115#define LTQ_MEI_BASE_ADDR 0x1E116000
116
117/* DEU - data encryption unit */
118#define LTQ_DEU_BASE_ADDR 0x1E103100
119
120/* MPS - multi processor unit (voice) */
121#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
122#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
123
124/* request a non-gpio and set the PIO config */
125extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
126 unsigned int alt1, unsigned int dir, const char *name);
127extern void ltq_pmu_enable(unsigned int module);
128extern void ltq_pmu_disable(unsigned int module);
129
130static inline int ltq_is_ar9(void)
131{
132 return (ltq_get_soc_type() == SOC_TYPE_AR9);
133}
134
135static inline int ltq_is_vr9(void)
136{
137 return (ltq_get_soc_type() == SOC_TYPE_VR9);
138}
139
140#endif /* CONFIG_SOC_TYPE_XWAY */
141#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
new file mode 100644
index 000000000000..872943a4b90e
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
@@ -0,0 +1,60 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
16 */
17
18#ifndef LTQ_DMA_H__
19#define LTQ_DMA_H__
20
21#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */
22#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */
23
24#define LTQ_DMA_OWN BIT(31) /* owner bit */
25#define LTQ_DMA_C BIT(30) /* complete bit */
26#define LTQ_DMA_SOP BIT(29) /* start of packet */
27#define LTQ_DMA_EOP BIT(28) /* end of packet */
28#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */
29#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */
30#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */
31
32struct ltq_dma_desc {
33 u32 ctl;
34 u32 addr;
35};
36
37struct ltq_dma_channel {
38 int nr; /* the channel number */
39 int irq; /* the mapped irq */
40 int desc; /* the current descriptor */
41 struct ltq_dma_desc *desc_base; /* the descriptor base */
42 int phys; /* physical addr */
43};
44
45enum {
46 DMA_PORT_ETOP = 0,
47 DMA_PORT_DEU,
48};
49
50extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
51extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
52extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
53extern void ltq_dma_open(struct ltq_dma_channel *ch);
54extern void ltq_dma_close(struct ltq_dma_channel *ch);
55extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
56extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
57extern void ltq_dma_free(struct ltq_dma_channel *ch);
58extern void ltq_dma_init_port(int p);
59
60#endif
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
new file mode 100644
index 000000000000..3b728275b9b0
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -0,0 +1,47 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 Netlogic Microsystems
7 * Copyright (C) 2003 Ralf Baechle
8 */
9#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
11
12#define cpu_has_4kex 1
13#define cpu_has_4k_cache 1
14#define cpu_has_watch 1
15#define cpu_has_mips16 0
16#define cpu_has_counter 1
17#define cpu_has_divec 1
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
30#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0
32#define cpu_icache_snoops_remote_store 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_mips32r1 1
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 1
40#define cpu_has_mips64r2 0
41
42#define cpu_has_inclusive_pcaches 0
43
44#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32
46
47#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
new file mode 100644
index 000000000000..b5902458e7c1
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -0,0 +1,14 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 Netlogic Microsystems.
7 */
8#ifndef __ASM_NETLOGIC_IRQ_H
9#define __ASM_NETLOGIC_IRQ_H
10
11#define NR_IRQS 64
12#define MIPS_CPU_IRQ_BASE 0
13
14#endif /* __ASM_NETLOGIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
new file mode 100644
index 000000000000..22da89327352
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/war.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 Netlogic Microsystems.
7 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_MIPS_MACH_NLM_WAR_H
10#define __ASM_MIPS_MACH_NLM_WAR_H
11
12#define R4600_V1_INDEX_ICACHEOP_WAR 0
13#define R4600_V1_HIT_CACHEOP_WAR 0
14#define R4600_V2_HIT_CACHEOP_WAR 0
15#define R5432_CP0_INTERRUPT_WAR 0
16#define BCM1250_M3_WAR 0
17#define SIBYTE_1956_WAR 0
18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0
25
26#endif /* __ASM_MIPS_MACH_NLM_WAR_H */
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index d94085a3eafb..bc01a02cacd8 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr)
118#define MODULE_PROC_FAMILY "LOONGSON2 " 118#define MODULE_PROC_FAMILY "LOONGSON2 "
119#elif defined CONFIG_CPU_CAVIUM_OCTEON 119#elif defined CONFIG_CPU_CAVIUM_OCTEON
120#define MODULE_PROC_FAMILY "OCTEON " 120#define MODULE_PROC_FAMILY "OCTEON "
121#elif defined CONFIG_CPU_XLR
122#define MODULE_PROC_FAMILY "XLR "
121#else 123#else
122#error MODULE_PROC_FAMILY undefined for your processor configuration 124#error MODULE_PROC_FAMILY undefined for your processor configuration
123#endif 125#endif
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
new file mode 100644
index 000000000000..a85aadb6cfd7
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_INTERRUPT_H
36#define _ASM_NLM_INTERRUPT_H
37
38/* Defines for the IRQ numbers */
39
40#define IRQ_IPI_SMP_FUNCTION 3
41#define IRQ_IPI_SMP_RESCHEDULE 4
42#define IRQ_MSGRING 6
43#define IRQ_TIMER 7
44
45#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
new file mode 100644
index 000000000000..8c53d0ba4bf2
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_MIPS_EXTS_H
36#define _ASM_NLM_MIPS_EXTS_H
37
38/*
39 * XLR and XLP interrupt request and interrupt mask registers
40 */
41#define read_c0_eirr() __read_64bit_c0_register($9, 6)
42#define read_c0_eimr() __read_64bit_c0_register($9, 7)
43#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val)
44
45/*
46 * Writing EIMR in 32 bit is a special case, the lower 8 bit of the
47 * EIMR is shadowed in the status register, so we cannot save and
48 * restore status register for split read.
49 */
50#define write_c0_eimr(val) \
51do { \
52 if (sizeof(unsigned long) == 4) { \
53 unsigned long __flags; \
54 \
55 local_irq_save(__flags); \
56 __asm__ __volatile__( \
57 ".set\tmips64\n\t" \
58 "dsll\t%L0, %L0, 32\n\t" \
59 "dsrl\t%L0, %L0, 32\n\t" \
60 "dsll\t%M0, %M0, 32\n\t" \
61 "or\t%L0, %L0, %M0\n\t" \
62 "dmtc0\t%L0, $9, 7\n\t" \
63 ".set\tmips0" \
64 : : "r" (val)); \
65 __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\
66 local_irq_restore(__flags); \
67 } else \
68 __write_64bit_c0_register($9, 7, (val)); \
69} while (0)
70
71static inline int hard_smp_processor_id(void)
72{
73 return __read_32bit_c0_register($15, 1) & 0x3ff;
74}
75
76#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h
new file mode 100644
index 000000000000..6878307f0ee6
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NETLOGIC_BOOTINFO_H
36#define _ASM_NETLOGIC_BOOTINFO_H
37
38struct psb_info {
39 uint64_t boot_level;
40 uint64_t io_base;
41 uint64_t output_device;
42 uint64_t uart_print;
43 uint64_t led_output;
44 uint64_t init;
45 uint64_t exit;
46 uint64_t warm_reset;
47 uint64_t wakeup;
48 uint64_t online_cpu_map;
49 uint64_t master_reentry_sp;
50 uint64_t master_reentry_gp;
51 uint64_t master_reentry_fn;
52 uint64_t slave_reentry_fn;
53 uint64_t magic_dword;
54 uint64_t uart_putchar;
55 uint64_t size;
56 uint64_t uart_getchar;
57 uint64_t nmi_handler;
58 uint64_t psb_version;
59 uint64_t mac_addr;
60 uint64_t cpu_frequency;
61 uint64_t board_version;
62 uint64_t malloc;
63 uint64_t free;
64 uint64_t global_shmem_addr;
65 uint64_t global_shmem_size;
66 uint64_t psb_os_cpu_map;
67 uint64_t userapp_cpu_map;
68 uint64_t wakeup_os;
69 uint64_t psb_mem_map;
70 uint64_t board_major_version;
71 uint64_t board_minor_version;
72 uint64_t board_manf_revision;
73 uint64_t board_serial_number;
74 uint64_t psb_physaddr_map;
75 uint64_t xlr_loaderip_config;
76 uint64_t bldr_envp;
77 uint64_t avail_mem_map;
78};
79
80enum {
81 NETLOGIC_IO_SPACE = 0x10,
82 PCIX_IO_SPACE,
83 PCIX_CFG_SPACE,
84 PCIX_MEMORY_SPACE,
85 HT_IO_SPACE,
86 HT_CFG_SPACE,
87 HT_MEMORY_SPACE,
88 SRAM_SPACE,
89 FLASH_CONTROLLER_SPACE
90};
91
92#define NLM_MAX_ARGS 64
93#define NLM_MAX_ENVS 32
94
95/* This is what netlboot passes and linux boot_mem_map is subtly different */
96#define NLM_BOOT_MEM_MAP_MAX 32
97struct nlm_boot_mem_map {
98 int nr_map;
99 struct nlm_boot_mem_map_entry {
100 uint64_t addr; /* start of memory segment */
101 uint64_t size; /* size of memory segment */
102 uint32_t type; /* type of memory segment */
103 } map[NLM_BOOT_MEM_MAP_MAX];
104};
105
106/* Pointer to saved boot loader info */
107extern struct psb_info nlm_prom_info;
108
109#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
new file mode 100644
index 000000000000..51f6ad4aeb14
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_GPIO_H
36#define _ASM_NLM_GPIO_H
37
38#define NETLOGIC_GPIO_INT_EN_REG 0
39#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1
40#define NETLOGIC_GPIO_IO_DIR_REG 2
41#define NETLOGIC_GPIO_IO_DATA_WR_REG 3
42#define NETLOGIC_GPIO_IO_DATA_RD_REG 4
43
44#define NETLOGIC_GPIO_SWRESET_REG 8
45#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9
46#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10
47#define NETLOGIC_GPIO_DRAM1_RESET_REG 11
48#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12
49#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13
50#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14
51#define NETLOGIC_GPIO_DRAM2_RESET_REG 15
52#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16
53
54#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21
55#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24
56#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25
57#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26
58
59#define NETLOGIC_GPIO_FUSE_BANK_REG 35
60#define NETLOGIC_GPIO_CPU_RESET_REG 40
61#define NETLOGIC_GPIO_RNG_REG 43
62
63#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17
64#define NETLOGIC_GPIO_LED_BITMAP 0x1700000
65#define NETLOGIC_GPIO_LED_0_SHIFT 20
66#define NETLOGIC_GPIO_LED_1_SHIFT 24
67
68#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01
69#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
70#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
71#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04
72
73#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
new file mode 100644
index 000000000000..2e3a4dd53045
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -0,0 +1,131 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_IOMAP_H
36#define _ASM_NLM_IOMAP_H
37
38#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43#define NETLOGIC_IO_PIC_OFFSET 0x08000
44#define NETLOGIC_IO_UART_0_OFFSET 0x14000
45#define NETLOGIC_IO_UART_1_OFFSET 0x15100
46
47#define NETLOGIC_IO_SIZE 0x1000
48
49#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
50
51#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000
52#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000
53
54#define NETLOGIC_IO_SRAM_OFFSET 0x07000
55
56#define NETLOGIC_IO_PCIX_OFFSET 0x09000
57#define NETLOGIC_IO_HT_OFFSET 0x0A000
58
59#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000
60
61#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000
62#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000
63#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000
64#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000
65
66/* XLS devices */
67#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000
68#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000
69#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000
70#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000
71
72#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000
73#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000
74#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000
75#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000
76
77#define NETLOGIC_IO_USB_0_OFFSET 0x24000
78#define NETLOGIC_IO_USB_1_OFFSET 0x25000
79
80#define NETLOGIC_IO_COMP_OFFSET 0x1D000
81/* end XLS devices */
82
83/* XLR devices */
84#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000
85#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000
86#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000
87#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000
88/* end XLR devices */
89
90#define NETLOGIC_IO_I2C_0_OFFSET 0x16000
91#define NETLOGIC_IO_I2C_1_OFFSET 0x17000
92
93#define NETLOGIC_IO_GPIO_OFFSET 0x18000
94#define NETLOGIC_IO_FLASH_OFFSET 0x19000
95#define NETLOGIC_IO_TB_OFFSET 0x1C000
96
97#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000)
98
99/*
100 * Base Address (Virtual) of the PCI Config address space
101 * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
102 * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
103 * ie 1<<24 = 16M
104 */
105#define DEFAULT_PCI_CONFIG_BASE 0x18000000
106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
108
109#ifndef __ASSEMBLY__
110#include <linux/types.h>
111#include <asm/byteorder.h>
112
113typedef volatile __u32 nlm_reg_t;
114extern unsigned long netlogic_io_base;
115
116/* FIXME read once in write_reg */
117#ifdef CONFIG_CPU_LITTLE_ENDIAN
118#define netlogic_read_reg(base, offset) ((base)[(offset)])
119#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
120#else
121#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
122#define netlogic_write_reg(base, offset, value) \
123 ((base)[(offset)] = cpu_to_be32((value)))
124#endif
125
126#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
127#define netlogic_write_reg_le32(base, offset, value) \
128 ((base)[(offset)] = cpu_to_le32((value)))
129#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
130#endif /* __ASSEMBLY__ */
131#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
new file mode 100644
index 000000000000..5cceb746f080
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -0,0 +1,231 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_XLR_PIC_H
36#define _ASM_NLM_XLR_PIC_H
37
38#define PIC_CLKS_PER_SEC 66666666ULL
39/* PIC hardware interrupt numbers */
40#define PIC_IRT_WD_INDEX 0
41#define PIC_IRT_TIMER_0_INDEX 1
42#define PIC_IRT_TIMER_1_INDEX 2
43#define PIC_IRT_TIMER_2_INDEX 3
44#define PIC_IRT_TIMER_3_INDEX 4
45#define PIC_IRT_TIMER_4_INDEX 5
46#define PIC_IRT_TIMER_5_INDEX 6
47#define PIC_IRT_TIMER_6_INDEX 7
48#define PIC_IRT_TIMER_7_INDEX 8
49#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
50#define PIC_IRT_UART_0_INDEX 9
51#define PIC_IRT_UART_1_INDEX 10
52#define PIC_IRT_I2C_0_INDEX 11
53#define PIC_IRT_I2C_1_INDEX 12
54#define PIC_IRT_PCMCIA_INDEX 13
55#define PIC_IRT_GPIO_INDEX 14
56#define PIC_IRT_HYPER_INDEX 15
57#define PIC_IRT_PCIX_INDEX 16
58/* XLS */
59#define PIC_IRT_CDE_INDEX 15
60#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16
61/* XLS */
62#define PIC_IRT_GMAC0_INDEX 17
63#define PIC_IRT_GMAC1_INDEX 18
64#define PIC_IRT_GMAC2_INDEX 19
65#define PIC_IRT_GMAC3_INDEX 20
66#define PIC_IRT_XGS0_INDEX 21
67#define PIC_IRT_XGS1_INDEX 22
68#define PIC_IRT_HYPER_FATAL_INDEX 23
69#define PIC_IRT_PCIX_FATAL_INDEX 24
70#define PIC_IRT_BRIDGE_AERR_INDEX 25
71#define PIC_IRT_BRIDGE_BERR_INDEX 26
72#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27
73#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
74/* XLS */
75#define PIC_IRT_GMAC4_INDEX 21
76#define PIC_IRT_GMAC5_INDEX 22
77#define PIC_IRT_GMAC6_INDEX 23
78#define PIC_IRT_GMAC7_INDEX 24
79#define PIC_IRT_BRIDGE_ERR_INDEX 25
80#define PIC_IRT_PCIE_LINK0_INDEX 26
81#define PIC_IRT_PCIE_LINK1_INDEX 27
82#define PIC_IRT_PCIE_LINK2_INDEX 23
83#define PIC_IRT_PCIE_LINK3_INDEX 24
84#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28
85#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29
86#define PIC_IRT_SRIO_LINK0_INDEX 26
87#define PIC_IRT_SRIO_LINK1_INDEX 27
88#define PIC_IRT_SRIO_LINK2_INDEX 28
89#define PIC_IRT_SRIO_LINK3_INDEX 29
90#define PIC_IRT_PCIE_INT_INDEX 28
91#define PIC_IRT_PCIE_FATAL_INDEX 29
92#define PIC_IRT_GPIO_B_INDEX 30
93#define PIC_IRT_USB_INDEX 31
94/* XLS */
95#define PIC_NUM_IRTS 32
96
97
98#define PIC_CLOCK_TIMER 7
99
100/* PIC Registers */
101#define PIC_CTRL 0x00
102#define PIC_IPI 0x04
103#define PIC_INT_ACK 0x06
104
105#define WD_MAX_VAL_0 0x08
106#define WD_MAX_VAL_1 0x09
107#define WD_MASK_0 0x0a
108#define WD_MASK_1 0x0b
109#define WD_HEARBEAT_0 0x0c
110#define WD_HEARBEAT_1 0x0d
111
112#define PIC_IRT_0_BASE 0x40
113#define PIC_IRT_1_BASE 0x80
114#define PIC_TIMER_MAXVAL_0_BASE 0x100
115#define PIC_TIMER_MAXVAL_1_BASE 0x110
116#define PIC_TIMER_COUNT_0_BASE 0x120
117#define PIC_TIMER_COUNT_1_BASE 0x130
118
119#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
120#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
121
122#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
123#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
124#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
125#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
126
127/*
128 * Mapping between hardware interrupt numbers and IRQs on CPU
129 * we use a simple scheme to map PIC interrupts 0-31 to IRQs
130 * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
131 * count/compare and FMN
132 */
133#define PIC_IRQ_BASE 8
134#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
135#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
136
137#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
138#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
139#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
140#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
141#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
142#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
143#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
144#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
145#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
146#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
147#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ)
148#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
149#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
150#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
151#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
152#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
153#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
154#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
155#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
156/* XLS */
157#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
158#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
159/* end XLS */
160#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
161#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
162#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
163#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
164#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
165#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
166#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
167#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
168#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
169#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
170#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
171#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
172/* XLS defines */
173#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
174#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
175#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
176#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
177#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
178#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
179#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
180#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
181#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
182#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
183#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
184#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
185#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
186#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
187#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
188#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
189#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
190#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
191#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
192#define PIC_IRT_LAST_IRQ PIC_USB_IRQ
193/* end XLS */
194
195#ifndef __ASSEMBLY__
196static inline void pic_send_ipi(u32 ipi)
197{
198 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
199
200 netlogic_write_reg(mmio, PIC_IPI, ipi);
201}
202
203static inline u32 pic_read_control(void)
204{
205 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
206
207 return netlogic_read_reg(mmio, PIC_CTRL);
208}
209
210static inline void pic_write_control(u32 control)
211{
212 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
213
214 netlogic_write_reg(mmio, PIC_CTRL, control);
215}
216
217static inline void pic_update_control(u32 control)
218{
219 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
220
221 netlogic_write_reg(mmio, PIC_CTRL,
222 (control | netlogic_read_reg(mmio, PIC_CTRL)));
223}
224
225#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
226 ((irq) <= PIC_TIMER_7_IRQ))
227#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
228 ((irq) <= PIC_IRT_LAST_IRQ))
229#endif
230
231#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
new file mode 100644
index 000000000000..3e6372692a04
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -0,0 +1,75 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_XLR_H
36#define _ASM_NLM_XLR_H
37
38/* Platform UART functions */
39struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int);
42
43/* SMP support functions */
44struct irq_desc;
45void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
46void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
47int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
48void nlm_smp_irq_init(void);
49void nlm_boot_smp_nmi(void);
50void prom_pre_boot_secondary_cpus(void);
51
52extern struct plat_smp_ops nlm_smp_ops;
53extern unsigned long nlm_common_ebase;
54
55/* XLS B silicon "Rook" */
56static inline unsigned int nlm_chip_is_xls_b(void)
57{
58 uint32_t prid = read_c0_prid();
59
60 return ((prid & 0xf000) == 0x4000);
61}
62
63/*
64 * XLR chip types
65 */
66 /* The XLS product line has chip versions 0x[48c]? */
67static inline unsigned int nlm_chip_is_xls(void)
68{
69 uint32_t prid = read_c0_prid();
70
71 return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
72 (prid & 0xf000) == 0xc000);
73}
74
75#endif /* _ASM_NLM_XLR_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 9f1b8dba2c81..de39b1f343ea 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -141,7 +141,8 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
141#define instruction_pointer(regs) ((regs)->cp0_epc) 141#define instruction_pointer(regs) ((regs)->cp0_epc)
142#define profile_pc(regs) instruction_pointer(regs) 142#define profile_pc(regs) instruction_pointer(regs)
143 143
144extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); 144extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
145extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
145 146
146extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET; 147extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
147 148
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index d71160de4d10..97f8bf6639e7 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -149,6 +149,9 @@ register struct thread_info *__current_thread_info __asm__("$28");
149#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 149#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
150#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 150#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
151 151
152/* work to do in syscall_trace_leave() */
153#define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
154
152/* work to do on interrupt/exception return */ 155/* work to do on interrupt/exception return */
153#define _TIF_WORK_MASK (0x0000ffef & \ 156#define _TIF_WORK_MASK (0x0000ffef & \
154 ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT)) 157 ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT))
diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index 9ce9f64cb76f..2d8e447cb828 100644
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -211,7 +211,7 @@ EXPORT_SYMBOL(vdma_free);
211 */ 211 */
212int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size) 212int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
213{ 213{
214 int first, pages, npages; 214 int first, pages;
215 215
216 if (laddr > 0xffffff) { 216 if (laddr > 0xffffff) {
217 if (vdma_debug) 217 if (vdma_debug)
@@ -228,8 +228,7 @@ int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
228 return -EINVAL; /* invalid physical address */ 228 return -EINVAL; /* invalid physical address */
229 } 229 }
230 230
231 npages = pages = 231 pages = (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;
232 (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;
233 first = laddr >> 12; 232 first = laddr >> 12;
234 if (vdma_debug) 233 if (vdma_debug)
235 printk("vdma_remap: first=%x, pages=%x\n", first, pages); 234 printk("vdma_remap: first=%x, pages=%x\n", first, pages);
diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c
index 5ebe75a68350..d7feb898692c 100644
--- a/arch/mips/jz4740/dma.c
+++ b/arch/mips/jz4740/dma.c
@@ -242,9 +242,7 @@ EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
242 242
243static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma) 243static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
244{ 244{
245 uint32_t status; 245 (void) jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
246
247 status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
248 246
249 jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, 247 jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
250 JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE); 248 JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
index 6a9e14dab91e..d97cfbf882f5 100644
--- a/arch/mips/jz4740/setup.c
+++ b/arch/mips/jz4740/setup.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
3 * JZ4740 setup code 4 * JZ4740 setup code
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
@@ -14,13 +15,44 @@
14 */ 15 */
15 16
16#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/io.h>
17#include <linux/kernel.h> 19#include <linux/kernel.h>
18 20
21#include <asm/bootinfo.h>
22
23#include <asm/mach-jz4740/base.h>
24
19#include "reset.h" 25#include "reset.h"
20 26
27
28#define JZ4740_EMC_SDRAM_CTRL 0x80
29
30
31static void __init jz4740_detect_mem(void)
32{
33 void __iomem *jz_emc_base;
34 u32 ctrl, bus, bank, rows, cols;
35 phys_t size;
36
37 jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
38 ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
39 bus = 2 - ((ctrl >> 31) & 1);
40 bank = 1 + ((ctrl >> 19) & 1);
41 cols = 8 + ((ctrl >> 26) & 7);
42 rows = 11 + ((ctrl >> 20) & 3);
43 printk(KERN_DEBUG
44 "SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n",
45 bus, bank, rows, cols);
46 iounmap(jz_emc_base);
47
48 size = 1 << (bus + bank + cols + rows);
49 add_memory_region(0, size, BOOT_MEM_RAM);
50}
51
21void __init plat_mem_setup(void) 52void __init plat_mem_setup(void)
22{ 53{
23 jz4740_reset_init(); 54 jz4740_reset_init();
55 jz4740_detect_mem();
24} 56}
25 57
26const char *get_system_type(void) 58const char *get_system_type(void)
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index 03dfd4e0da4e..f83c2dd07a27 100644
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -89,7 +89,7 @@ static int jz4740_clockevent_set_next(unsigned long evt,
89 89
90static struct clock_event_device jz4740_clockevent = { 90static struct clock_event_device jz4740_clockevent = {
91 .name = "jz4740-timer", 91 .name = "jz4740-timer",
92 .features = CLOCK_EVT_FEAT_PERIODIC, 92 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
93 .set_next_event = jz4740_clockevent_set_next, 93 .set_next_event = jz4740_clockevent_set_next,
94 .set_mode = jz4740_clockevent_set_mode, 94 .set_mode = jz4740_clockevent_set_mode,
95 .rating = 200, 95 .rating = 200,
diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c
index b2c015129055..654d5c3900b6 100644
--- a/arch/mips/jz4740/timer.c
+++ b/arch/mips/jz4740/timer.c
@@ -27,11 +27,13 @@ void jz4740_timer_enable_watchdog(void)
27{ 27{
28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); 28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
29} 29}
30EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog);
30 31
31void jz4740_timer_disable_watchdog(void) 32void jz4740_timer_disable_watchdog(void)
32{ 33{
33 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); 34 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
34} 35}
36EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog);
35 37
36void __init jz4740_timer_init(void) 38void __init jz4740_timer_init(void)
37{ 39{
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index cedee2bcbd18..83bba332bbfc 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
52obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o 52obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
53obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o 53obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
54obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o 54obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
55obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o
55 56
56obj-$(CONFIG_SMP) += smp.o 57obj-$(CONFIG_SMP) += smp.o
57obj-$(CONFIG_SMP_UP) += smp-up.o 58obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f65d4c8c65a6..bb133d10b145 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -291,6 +291,12 @@ static inline int cpu_has_confreg(void)
291#endif 291#endif
292} 292}
293 293
294static inline void set_elf_platform(int cpu, const char *plat)
295{
296 if (cpu == 0)
297 __elf_platform = plat;
298}
299
294/* 300/*
295 * Get the FPU Implementation/Revision. 301 * Get the FPU Implementation/Revision.
296 */ 302 */
@@ -614,6 +620,16 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
614 case PRID_IMP_LOONGSON2: 620 case PRID_IMP_LOONGSON2:
615 c->cputype = CPU_LOONGSON2; 621 c->cputype = CPU_LOONGSON2;
616 __cpu_name[cpu] = "ICT Loongson-2"; 622 __cpu_name[cpu] = "ICT Loongson-2";
623
624 switch (c->processor_id & PRID_REV_MASK) {
625 case PRID_REV_LOONGSON2E:
626 set_elf_platform(cpu, "loongson2e");
627 break;
628 case PRID_REV_LOONGSON2F:
629 set_elf_platform(cpu, "loongson2f");
630 break;
631 }
632
617 c->isa_level = MIPS_CPU_ISA_III; 633 c->isa_level = MIPS_CPU_ISA_III;
618 c->options = R4K_OPTS | 634 c->options = R4K_OPTS |
619 MIPS_CPU_FPU | MIPS_CPU_LLSC | 635 MIPS_CPU_FPU | MIPS_CPU_LLSC |
@@ -911,12 +927,14 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
911 case PRID_IMP_BMIPS32_REV8: 927 case PRID_IMP_BMIPS32_REV8:
912 c->cputype = CPU_BMIPS32; 928 c->cputype = CPU_BMIPS32;
913 __cpu_name[cpu] = "Broadcom BMIPS32"; 929 __cpu_name[cpu] = "Broadcom BMIPS32";
930 set_elf_platform(cpu, "bmips32");
914 break; 931 break;
915 case PRID_IMP_BMIPS3300: 932 case PRID_IMP_BMIPS3300:
916 case PRID_IMP_BMIPS3300_ALT: 933 case PRID_IMP_BMIPS3300_ALT:
917 case PRID_IMP_BMIPS3300_BUG: 934 case PRID_IMP_BMIPS3300_BUG:
918 c->cputype = CPU_BMIPS3300; 935 c->cputype = CPU_BMIPS3300;
919 __cpu_name[cpu] = "Broadcom BMIPS3300"; 936 __cpu_name[cpu] = "Broadcom BMIPS3300";
937 set_elf_platform(cpu, "bmips3300");
920 break; 938 break;
921 case PRID_IMP_BMIPS43XX: { 939 case PRID_IMP_BMIPS43XX: {
922 int rev = c->processor_id & 0xff; 940 int rev = c->processor_id & 0xff;
@@ -925,15 +943,18 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
925 rev <= PRID_REV_BMIPS4380_HI) { 943 rev <= PRID_REV_BMIPS4380_HI) {
926 c->cputype = CPU_BMIPS4380; 944 c->cputype = CPU_BMIPS4380;
927 __cpu_name[cpu] = "Broadcom BMIPS4380"; 945 __cpu_name[cpu] = "Broadcom BMIPS4380";
946 set_elf_platform(cpu, "bmips4380");
928 } else { 947 } else {
929 c->cputype = CPU_BMIPS4350; 948 c->cputype = CPU_BMIPS4350;
930 __cpu_name[cpu] = "Broadcom BMIPS4350"; 949 __cpu_name[cpu] = "Broadcom BMIPS4350";
950 set_elf_platform(cpu, "bmips4350");
931 } 951 }
932 break; 952 break;
933 } 953 }
934 case PRID_IMP_BMIPS5000: 954 case PRID_IMP_BMIPS5000:
935 c->cputype = CPU_BMIPS5000; 955 c->cputype = CPU_BMIPS5000;
936 __cpu_name[cpu] = "Broadcom BMIPS5000"; 956 __cpu_name[cpu] = "Broadcom BMIPS5000";
957 set_elf_platform(cpu, "bmips5000");
937 c->options |= MIPS_CPU_ULRI; 958 c->options |= MIPS_CPU_ULRI;
938 break; 959 break;
939 } 960 }
@@ -956,14 +977,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
956 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 977 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
957 __cpu_name[cpu] = "Cavium Octeon+"; 978 __cpu_name[cpu] = "Cavium Octeon+";
958platform: 979platform:
959 if (cpu == 0) 980 set_elf_platform(cpu, "octeon");
960 __elf_platform = "octeon";
961 break; 981 break;
962 case PRID_IMP_CAVIUM_CN63XX: 982 case PRID_IMP_CAVIUM_CN63XX:
963 c->cputype = CPU_CAVIUM_OCTEON2; 983 c->cputype = CPU_CAVIUM_OCTEON2;
964 __cpu_name[cpu] = "Cavium Octeon II"; 984 __cpu_name[cpu] = "Cavium Octeon II";
965 if (cpu == 0) 985 set_elf_platform(cpu, "octeon2");
966 __elf_platform = "octeon2";
967 break; 986 break;
968 default: 987 default:
969 printk(KERN_INFO "Unknown Octeon chip!\n"); 988 printk(KERN_INFO "Unknown Octeon chip!\n");
@@ -988,6 +1007,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
988 } 1007 }
989} 1008}
990 1009
1010static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1011{
1012 decode_configs(c);
1013
1014 c->options = (MIPS_CPU_TLB |
1015 MIPS_CPU_4KEX |
1016 MIPS_CPU_COUNTER |
1017 MIPS_CPU_DIVEC |
1018 MIPS_CPU_WATCH |
1019 MIPS_CPU_EJTAG |
1020 MIPS_CPU_LLSC);
1021
1022 switch (c->processor_id & 0xff00) {
1023 case PRID_IMP_NETLOGIC_XLR732:
1024 case PRID_IMP_NETLOGIC_XLR716:
1025 case PRID_IMP_NETLOGIC_XLR532:
1026 case PRID_IMP_NETLOGIC_XLR308:
1027 case PRID_IMP_NETLOGIC_XLR532C:
1028 case PRID_IMP_NETLOGIC_XLR516C:
1029 case PRID_IMP_NETLOGIC_XLR508C:
1030 case PRID_IMP_NETLOGIC_XLR308C:
1031 c->cputype = CPU_XLR;
1032 __cpu_name[cpu] = "Netlogic XLR";
1033 break;
1034
1035 case PRID_IMP_NETLOGIC_XLS608:
1036 case PRID_IMP_NETLOGIC_XLS408:
1037 case PRID_IMP_NETLOGIC_XLS404:
1038 case PRID_IMP_NETLOGIC_XLS208:
1039 case PRID_IMP_NETLOGIC_XLS204:
1040 case PRID_IMP_NETLOGIC_XLS108:
1041 case PRID_IMP_NETLOGIC_XLS104:
1042 case PRID_IMP_NETLOGIC_XLS616B:
1043 case PRID_IMP_NETLOGIC_XLS608B:
1044 case PRID_IMP_NETLOGIC_XLS416B:
1045 case PRID_IMP_NETLOGIC_XLS412B:
1046 case PRID_IMP_NETLOGIC_XLS408B:
1047 case PRID_IMP_NETLOGIC_XLS404B:
1048 c->cputype = CPU_XLR;
1049 __cpu_name[cpu] = "Netlogic XLS";
1050 break;
1051
1052 default:
1053 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1054 c->processor_id);
1055 c->cputype = CPU_XLR;
1056 break;
1057 }
1058
1059 c->isa_level = MIPS_CPU_ISA_M64R1;
1060 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1061}
1062
991#ifdef CONFIG_64BIT 1063#ifdef CONFIG_64BIT
992/* For use by uaccess.h */ 1064/* For use by uaccess.h */
993u64 __ua_limit; 1065u64 __ua_limit;
@@ -1035,6 +1107,9 @@ __cpuinit void cpu_probe(void)
1035 case PRID_COMP_INGENIC: 1107 case PRID_COMP_INGENIC:
1036 cpu_probe_ingenic(c, cpu); 1108 cpu_probe_ingenic(c, cpu);
1037 break; 1109 break;
1110 case PRID_COMP_NETLOGIC:
1111 cpu_probe_netlogic(c, cpu);
1112 break;
1038 } 1113 }
1039 1114
1040 BUG_ON(!__cpu_name[cpu]); 1115 BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index ffa331029e08..37acfa036d44 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -167,14 +167,13 @@ work_notifysig: # deal with pending signals and
167FEXPORT(syscall_exit_work_partial) 167FEXPORT(syscall_exit_work_partial)
168 SAVE_STATIC 168 SAVE_STATIC
169syscall_exit_work: 169syscall_exit_work:
170 li t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 170 li t0, _TIF_WORK_SYSCALL_EXIT
171 and t0, a2 # a2 is preloaded with TI_FLAGS 171 and t0, a2 # a2 is preloaded with TI_FLAGS
172 beqz t0, work_pending # trace bit set? 172 beqz t0, work_pending # trace bit set?
173 local_irq_enable # could let do_syscall_trace() 173 local_irq_enable # could let syscall_trace_leave()
174 # call schedule() instead 174 # call schedule() instead
175 move a0, sp 175 move a0, sp
176 li a1, 1 176 jal syscall_trace_leave
177 jal do_syscall_trace
178 b resume_userspace 177 b resume_userspace
179 178
180#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT) 179#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT)
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 94ca2b018af7..feb8021a305f 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -23,6 +23,7 @@
23 23
24#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ 24#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
25#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ 25#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */
26#define JUMP_RANGE_MASK ((1UL << 28) - 1)
26 27
27#define INSN_NOP 0x00000000 /* nop */ 28#define INSN_NOP 0x00000000 /* nop */
28#define INSN_JAL(addr) \ 29#define INSN_JAL(addr) \
@@ -44,12 +45,12 @@ static inline void ftrace_dyn_arch_init_insns(void)
44 45
45 /* jal (ftrace_caller + 8), jump over the first two instruction */ 46 /* jal (ftrace_caller + 8), jump over the first two instruction */
46 buf = (u32 *)&insn_jal_ftrace_caller; 47 buf = (u32 *)&insn_jal_ftrace_caller;
47 uasm_i_jal(&buf, (FTRACE_ADDR + 8)); 48 uasm_i_jal(&buf, (FTRACE_ADDR + 8) & JUMP_RANGE_MASK);
48 49
49#ifdef CONFIG_FUNCTION_GRAPH_TRACER 50#ifdef CONFIG_FUNCTION_GRAPH_TRACER
50 /* j ftrace_graph_caller */ 51 /* j ftrace_graph_caller */
51 buf = (u32 *)&insn_j_ftrace_graph_caller; 52 buf = (u32 *)&insn_j_ftrace_graph_caller;
52 uasm_i_j(&buf, (unsigned long)ftrace_graph_caller); 53 uasm_i_j(&buf, (unsigned long)ftrace_graph_caller & JUMP_RANGE_MASK);
53#endif 54#endif
54} 55}
55 56
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index d21c388c0116..4e6ea1ffad46 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -533,15 +533,10 @@ static inline int audit_arch(void)
533 * Notification of system call entry/exit 533 * Notification of system call entry/exit
534 * - triggered by current->work.syscall_trace 534 * - triggered by current->work.syscall_trace
535 */ 535 */
536asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) 536asmlinkage void syscall_trace_enter(struct pt_regs *regs)
537{ 537{
538 /* do the secure computing check first */ 538 /* do the secure computing check first */
539 if (!entryexit) 539 secure_computing(regs->regs[2]);
540 secure_computing(regs->regs[2]);
541
542 if (unlikely(current->audit_context) && entryexit)
543 audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]),
544 regs->regs[2]);
545 540
546 if (!(current->ptrace & PT_PTRACED)) 541 if (!(current->ptrace & PT_PTRACED))
547 goto out; 542 goto out;
@@ -565,8 +560,40 @@ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
565 } 560 }
566 561
567out: 562out:
568 if (unlikely(current->audit_context) && !entryexit) 563 if (unlikely(current->audit_context))
569 audit_syscall_entry(audit_arch(), regs->regs[2], 564 audit_syscall_entry(audit_arch(), regs->regs[2],
570 regs->regs[4], regs->regs[5], 565 regs->regs[4], regs->regs[5],
571 regs->regs[6], regs->regs[7]); 566 regs->regs[6], regs->regs[7]);
572} 567}
568
569/*
570 * Notification of system call entry/exit
571 * - triggered by current->work.syscall_trace
572 */
573asmlinkage void syscall_trace_leave(struct pt_regs *regs)
574{
575 if (unlikely(current->audit_context))
576 audit_syscall_exit(AUDITSC_RESULT(regs->regs[7]),
577 -regs->regs[2]);
578
579 if (!(current->ptrace & PT_PTRACED))
580 return;
581
582 if (!test_thread_flag(TIF_SYSCALL_TRACE))
583 return;
584
585 /* The 0x80 provides a way for the tracing parent to distinguish
586 between a syscall stop and SIGTRAP delivery */
587 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
588 0x80 : 0));
589
590 /*
591 * this isn't the same as continuing with a signal, but it will do
592 * for normal use. strace only continues with a signal if the
593 * stopping signal is not SIGTRAP. -brl
594 */
595 if (current->exit_code) {
596 send_sig(current->exit_code, current, 1);
597 current->exit_code = 0;
598 }
599}
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 7f5468b38d4c..7a8e1dd7f6f2 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -88,8 +88,7 @@ syscall_trace_entry:
88 SAVE_STATIC 88 SAVE_STATIC
89 move s0, t2 89 move s0, t2
90 move a0, sp 90 move a0, sp
91 li a1, 0 91 jal syscall_trace_enter
92 jal do_syscall_trace
93 92
94 move t0, s0 93 move t0, s0
95 RESTORE_STATIC 94 RESTORE_STATIC
@@ -565,7 +564,7 @@ einval: li v0, -ENOSYS
565 sys sys_ioprio_get 2 /* 4315 */ 564 sys sys_ioprio_get 2 /* 4315 */
566 sys sys_utimensat 4 565 sys sys_utimensat 4
567 sys sys_signalfd 3 566 sys sys_signalfd 3
568 sys sys_ni_syscall 0 567 sys sys_ni_syscall 0 /* was timerfd */
569 sys sys_eventfd 1 568 sys sys_eventfd 1
570 sys sys_fallocate 6 /* 4320 */ 569 sys sys_fallocate 6 /* 4320 */
571 sys sys_timerfd_create 2 570 sys sys_timerfd_create 2
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index a2e1fcbc41dc..2d31c83224f9 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -91,8 +91,7 @@ syscall_trace_entry:
91 SAVE_STATIC 91 SAVE_STATIC
92 move s0, t2 92 move s0, t2
93 move a0, sp 93 move a0, sp
94 li a1, 0 94 jal syscall_trace_enter
95 jal do_syscall_trace
96 95
97 move t0, s0 96 move t0, s0
98 RESTORE_STATIC 97 RESTORE_STATIC
@@ -404,7 +403,7 @@ sys_call_table:
404 PTR sys_ioprio_get 403 PTR sys_ioprio_get
405 PTR sys_utimensat /* 5275 */ 404 PTR sys_utimensat /* 5275 */
406 PTR sys_signalfd 405 PTR sys_signalfd
407 PTR sys_ni_syscall 406 PTR sys_ni_syscall /* was timerfd */
408 PTR sys_eventfd 407 PTR sys_eventfd
409 PTR sys_fallocate 408 PTR sys_fallocate
410 PTR sys_timerfd_create /* 5280 */ 409 PTR sys_timerfd_create /* 5280 */
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index b2c7624995b8..38a0503b9a4a 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -89,8 +89,7 @@ n32_syscall_trace_entry:
89 SAVE_STATIC 89 SAVE_STATIC
90 move s0, t2 90 move s0, t2
91 move a0, sp 91 move a0, sp
92 li a1, 0 92 jal syscall_trace_enter
93 jal do_syscall_trace
94 93
95 move t0, s0 94 move t0, s0
96 RESTORE_STATIC 95 RESTORE_STATIC
@@ -403,7 +402,7 @@ EXPORT(sysn32_call_table)
403 PTR sys_ioprio_get 402 PTR sys_ioprio_get
404 PTR compat_sys_utimensat 403 PTR compat_sys_utimensat
405 PTR compat_sys_signalfd /* 6280 */ 404 PTR compat_sys_signalfd /* 6280 */
406 PTR sys_ni_syscall 405 PTR sys_ni_syscall /* was timerfd */
407 PTR sys_eventfd 406 PTR sys_eventfd
408 PTR sys_fallocate 407 PTR sys_fallocate
409 PTR sys_timerfd_create 408 PTR sys_timerfd_create
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 049a9c8c49a0..91ea5e4041dd 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -123,8 +123,7 @@ trace_a_syscall:
123 123
124 move s0, t2 # Save syscall pointer 124 move s0, t2 # Save syscall pointer
125 move a0, sp 125 move a0, sp
126 li a1, 0 126 jal syscall_trace_enter
127 jal do_syscall_trace
128 127
129 move t0, s0 128 move t0, s0
130 RESTORE_STATIC 129 RESTORE_STATIC
@@ -522,7 +521,7 @@ sys_call_table:
522 PTR sys_ioprio_get /* 4315 */ 521 PTR sys_ioprio_get /* 4315 */
523 PTR compat_sys_utimensat 522 PTR compat_sys_utimensat
524 PTR compat_sys_signalfd 523 PTR compat_sys_signalfd
525 PTR sys_ni_syscall 524 PTR sys_ni_syscall /* was timerfd */
526 PTR sys_eventfd 525 PTR sys_eventfd
527 PTR sys32_fallocate /* 4320 */ 526 PTR sys32_fallocate /* 4320 */
528 PTR sys_timerfd_create 527 PTR sys_timerfd_create
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 5a88cc4ccd5a..cedac4633741 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -929,7 +929,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
929 929
930static void ipi_resched_interrupt(void) 930static void ipi_resched_interrupt(void)
931{ 931{
932 /* Return from interrupt should be enough to cause scheduler check */ 932 scheduler_ipi();
933} 933}
934 934
935static void ipi_call_interrupt(void) 935static void ipi_call_interrupt(void)
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 58beabf50b3c..d02765708ddb 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -10,12 +10,9 @@
10#include <linux/capability.h> 10#include <linux/capability.h>
11#include <linux/errno.h> 11#include <linux/errno.h>
12#include <linux/linkage.h> 12#include <linux/linkage.h>
13#include <linux/mm.h>
14#include <linux/fs.h> 13#include <linux/fs.h>
15#include <linux/smp.h> 14#include <linux/smp.h>
16#include <linux/mman.h>
17#include <linux/ptrace.h> 15#include <linux/ptrace.h>
18#include <linux/sched.h>
19#include <linux/string.h> 16#include <linux/string.h>
20#include <linux/syscalls.h> 17#include <linux/syscalls.h>
21#include <linux/file.h> 18#include <linux/file.h>
@@ -25,11 +22,9 @@
25#include <linux/msg.h> 22#include <linux/msg.h>
26#include <linux/shm.h> 23#include <linux/shm.h>
27#include <linux/compiler.h> 24#include <linux/compiler.h>
28#include <linux/module.h>
29#include <linux/ipc.h> 25#include <linux/ipc.h>
30#include <linux/uaccess.h> 26#include <linux/uaccess.h>
31#include <linux/slab.h> 27#include <linux/slab.h>
32#include <linux/random.h>
33#include <linux/elf.h> 28#include <linux/elf.h>
34 29
35#include <asm/asm.h> 30#include <asm/asm.h>
@@ -66,121 +61,6 @@ out:
66 return res; 61 return res;
67} 62}
68 63
69unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
70
71EXPORT_SYMBOL(shm_align_mask);
72
73#define COLOUR_ALIGN(addr,pgoff) \
74 ((((addr) + shm_align_mask) & ~shm_align_mask) + \
75 (((pgoff) << PAGE_SHIFT) & shm_align_mask))
76
77unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
78 unsigned long len, unsigned long pgoff, unsigned long flags)
79{
80 struct vm_area_struct * vmm;
81 int do_color_align;
82 unsigned long task_size;
83
84#ifdef CONFIG_32BIT
85 task_size = TASK_SIZE;
86#else /* Must be CONFIG_64BIT*/
87 task_size = test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE;
88#endif
89
90 if (len > task_size)
91 return -ENOMEM;
92
93 if (flags & MAP_FIXED) {
94 /* Even MAP_FIXED mappings must reside within task_size. */
95 if (task_size - len < addr)
96 return -EINVAL;
97
98 /*
99 * We do not accept a shared mapping if it would violate
100 * cache aliasing constraints.
101 */
102 if ((flags & MAP_SHARED) &&
103 ((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
104 return -EINVAL;
105 return addr;
106 }
107
108 do_color_align = 0;
109 if (filp || (flags & MAP_SHARED))
110 do_color_align = 1;
111 if (addr) {
112 if (do_color_align)
113 addr = COLOUR_ALIGN(addr, pgoff);
114 else
115 addr = PAGE_ALIGN(addr);
116 vmm = find_vma(current->mm, addr);
117 if (task_size - len >= addr &&
118 (!vmm || addr + len <= vmm->vm_start))
119 return addr;
120 }
121 addr = current->mm->mmap_base;
122 if (do_color_align)
123 addr = COLOUR_ALIGN(addr, pgoff);
124 else
125 addr = PAGE_ALIGN(addr);
126
127 for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) {
128 /* At this point: (!vmm || addr < vmm->vm_end). */
129 if (task_size - len < addr)
130 return -ENOMEM;
131 if (!vmm || addr + len <= vmm->vm_start)
132 return addr;
133 addr = vmm->vm_end;
134 if (do_color_align)
135 addr = COLOUR_ALIGN(addr, pgoff);
136 }
137}
138
139void arch_pick_mmap_layout(struct mm_struct *mm)
140{
141 unsigned long random_factor = 0UL;
142
143 if (current->flags & PF_RANDOMIZE) {
144 random_factor = get_random_int();
145 random_factor = random_factor << PAGE_SHIFT;
146 if (TASK_IS_32BIT_ADDR)
147 random_factor &= 0xfffffful;
148 else
149 random_factor &= 0xffffffful;
150 }
151
152 mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
153 mm->get_unmapped_area = arch_get_unmapped_area;
154 mm->unmap_area = arch_unmap_area;
155}
156
157static inline unsigned long brk_rnd(void)
158{
159 unsigned long rnd = get_random_int();
160
161 rnd = rnd << PAGE_SHIFT;
162 /* 8MB for 32bit, 256MB for 64bit */
163 if (TASK_IS_32BIT_ADDR)
164 rnd = rnd & 0x7ffffful;
165 else
166 rnd = rnd & 0xffffffful;
167
168 return rnd;
169}
170
171unsigned long arch_randomize_brk(struct mm_struct *mm)
172{
173 unsigned long base = mm->brk;
174 unsigned long ret;
175
176 ret = PAGE_ALIGN(base + brk_rnd());
177
178 if (ret < mm->brk)
179 return mm->brk;
180
181 return ret;
182}
183
184SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len, 64SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
185 unsigned long, prot, unsigned long, flags, unsigned long, 65 unsigned long, prot, unsigned long, flags, unsigned long,
186 fd, off_t, offset) 66 fd, off_t, offset)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 71350f7f2d88..e9b3af27d844 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -374,7 +374,8 @@ void __noreturn die(const char *str, struct pt_regs *regs)
374 unsigned long dvpret = dvpe(); 374 unsigned long dvpret = dvpe();
375#endif /* CONFIG_MIPS_MT_SMTC */ 375#endif /* CONFIG_MIPS_MT_SMTC */
376 376
377 notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV); 377 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
378 sig = 0;
378 379
379 console_verbose(); 380 console_verbose();
380 spin_lock_irq(&die_lock); 381 spin_lock_irq(&die_lock);
@@ -383,9 +384,6 @@ void __noreturn die(const char *str, struct pt_regs *regs)
383 mips_mt_regdump(dvpret); 384 mips_mt_regdump(dvpret);
384#endif /* CONFIG_MIPS_MT_SMTC */ 385#endif /* CONFIG_MIPS_MT_SMTC */
385 386
386 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
387 sig = 0;
388
389 printk("%s[#%d]:\n", str, ++die_counter); 387 printk("%s[#%d]:\n", str, ++die_counter);
390 show_registers(regs); 388 show_registers(regs);
391 add_taint(TAINT_DIE); 389 add_taint(TAINT_DIE);
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 832afbb87588..cd2ca544454b 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -68,12 +68,14 @@ SECTIONS
68 RODATA 68 RODATA
69 69
70 /* writeable */ 70 /* writeable */
71 _sdata = .; /* Start of data section */
71 .data : { /* Data */ 72 .data : { /* Data */
72 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ 73 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
73 74
74 INIT_TASK_DATA(PAGE_SIZE) 75 INIT_TASK_DATA(PAGE_SIZE)
75 NOSAVE_DATA 76 NOSAVE_DATA
76 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) 77 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
78 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
77 DATA_DATA 79 DATA_DATA
78 CONSTRUCTORS 80 CONSTRUCTORS
79 } 81 }
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
new file mode 100644
index 000000000000..3fccf2104513
--- /dev/null
+++ b/arch/mips/lantiq/Kconfig
@@ -0,0 +1,23 @@
1if LANTIQ
2
3config SOC_TYPE_XWAY
4 bool
5 default n
6
7choice
8 prompt "SoC Type"
9 default SOC_XWAY
10
11config SOC_AMAZON_SE
12 bool "Amazon SE"
13 select SOC_TYPE_XWAY
14
15config SOC_XWAY
16 bool "XWAY"
17 select SOC_TYPE_XWAY
18 select HW_HAS_PCI
19endchoice
20
21source "arch/mips/lantiq/xway/Kconfig"
22
23endif
diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
new file mode 100644
index 000000000000..e5dae0e24b00
--- /dev/null
+++ b/arch/mips/lantiq/Makefile
@@ -0,0 +1,11 @@
1# Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2#
3# This program is free software; you can redistribute it and/or modify it
4# under the terms of the GNU General Public License version 2 as published
5# by the Free Software Foundation.
6
7obj-y := irq.o setup.o clk.o prom.o devices.o
8
9obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
10
11obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
new file mode 100644
index 000000000000..f3dff05722de
--- /dev/null
+++ b/arch/mips/lantiq/Platform
@@ -0,0 +1,8 @@
1#
2# Lantiq
3#
4
5platform-$(CONFIG_LANTIQ) += lantiq/
6cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
7load-$(CONFIG_LANTIQ) = 0xffffffff80002000
8cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
new file mode 100644
index 000000000000..94560899d13e
--- /dev/null
+++ b/arch/mips/lantiq/clk.c
@@ -0,0 +1,140 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
7 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
8 */
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/list.h>
17
18#include <asm/time.h>
19#include <asm/irq.h>
20#include <asm/div64.h>
21
22#include <lantiq_soc.h>
23
24#include "clk.h"
25
26struct clk {
27 const char *name;
28 unsigned long rate;
29 unsigned long (*get_rate) (void);
30};
31
32static struct clk *cpu_clk;
33static int cpu_clk_cnt;
34
35/* lantiq socs have 3 static clocks */
36static struct clk cpu_clk_generic[] = {
37 {
38 .name = "cpu",
39 .get_rate = ltq_get_cpu_hz,
40 }, {
41 .name = "fpi",
42 .get_rate = ltq_get_fpi_hz,
43 }, {
44 .name = "io",
45 .get_rate = ltq_get_io_region_clock,
46 },
47};
48
49static struct resource ltq_cgu_resource = {
50 .name = "cgu",
51 .start = LTQ_CGU_BASE_ADDR,
52 .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
53 .flags = IORESOURCE_MEM,
54};
55
56/* remapped clock register range */
57void __iomem *ltq_cgu_membase;
58
59void clk_init(void)
60{
61 cpu_clk = cpu_clk_generic;
62 cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
63}
64
65static inline int clk_good(struct clk *clk)
66{
67 return clk && !IS_ERR(clk);
68}
69
70unsigned long clk_get_rate(struct clk *clk)
71{
72 if (unlikely(!clk_good(clk)))
73 return 0;
74
75 if (clk->rate != 0)
76 return clk->rate;
77
78 if (clk->get_rate != NULL)
79 return clk->get_rate();
80
81 return 0;
82}
83EXPORT_SYMBOL(clk_get_rate);
84
85struct clk *clk_get(struct device *dev, const char *id)
86{
87 int i;
88
89 for (i = 0; i < cpu_clk_cnt; i++)
90 if (!strcmp(id, cpu_clk[i].name))
91 return &cpu_clk[i];
92 BUG();
93 return ERR_PTR(-ENOENT);
94}
95EXPORT_SYMBOL(clk_get);
96
97void clk_put(struct clk *clk)
98{
99 /* not used */
100}
101EXPORT_SYMBOL(clk_put);
102
103static inline u32 ltq_get_counter_resolution(void)
104{
105 u32 res;
106
107 __asm__ __volatile__(
108 ".set push\n"
109 ".set mips32r2\n"
110 "rdhwr %0, $3\n"
111 ".set pop\n"
112 : "=&r" (res)
113 : /* no input */
114 : "memory");
115
116 return res;
117}
118
119void __init plat_time_init(void)
120{
121 struct clk *clk;
122
123 if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
124 panic("Failed to insert cgu memory\n");
125
126 if (request_mem_region(ltq_cgu_resource.start,
127 resource_size(&ltq_cgu_resource), "cgu") < 0)
128 panic("Failed to request cgu memory\n");
129
130 ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
131 resource_size(&ltq_cgu_resource));
132 if (!ltq_cgu_membase) {
133 pr_err("Failed to remap cgu memory\n");
134 unreachable();
135 }
136 clk = clk_get(0, "cpu");
137 mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
138 write_c0_compare(read_c0_count());
139 clk_put(clk);
140}
diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
new file mode 100644
index 000000000000..3328925f2c3f
--- /dev/null
+++ b/arch/mips/lantiq/clk.h
@@ -0,0 +1,18 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_CLK_H__
10#define _LTQ_CLK_H__
11
12extern void clk_init(void);
13
14extern unsigned long ltq_get_cpu_hz(void);
15extern unsigned long ltq_get_fpi_hz(void);
16extern unsigned long ltq_get_io_region_clock(void);
17
18#endif
diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c
new file mode 100644
index 000000000000..7b82c34cb169
--- /dev/null
+++ b/arch/mips/lantiq/devices.c
@@ -0,0 +1,122 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/reboot.h>
15#include <linux/platform_device.h>
16#include <linux/leds.h>
17#include <linux/etherdevice.h>
18#include <linux/reboot.h>
19#include <linux/time.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/leds.h>
23
24#include <asm/bootinfo.h>
25#include <asm/irq.h>
26
27#include <lantiq_soc.h>
28
29#include "devices.h"
30
31/* nor flash */
32static struct resource ltq_nor_resource = {
33 .name = "nor",
34 .start = LTQ_FLASH_START,
35 .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
36 .flags = IORESOURCE_MEM,
37};
38
39static struct platform_device ltq_nor = {
40 .name = "ltq_nor",
41 .resource = &ltq_nor_resource,
42 .num_resources = 1,
43};
44
45void __init ltq_register_nor(struct physmap_flash_data *data)
46{
47 ltq_nor.dev.platform_data = data;
48 platform_device_register(&ltq_nor);
49}
50
51/* watchdog */
52static struct resource ltq_wdt_resource = {
53 .name = "watchdog",
54 .start = LTQ_WDT_BASE_ADDR,
55 .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
56 .flags = IORESOURCE_MEM,
57};
58
59void __init ltq_register_wdt(void)
60{
61 platform_device_register_simple("ltq_wdt", 0, &ltq_wdt_resource, 1);
62}
63
64/* asc ports */
65static struct resource ltq_asc0_resources[] = {
66 {
67 .name = "asc0",
68 .start = LTQ_ASC0_BASE_ADDR,
69 .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
70 .flags = IORESOURCE_MEM,
71 },
72 IRQ_RES(tx, LTQ_ASC_TIR(0)),
73 IRQ_RES(rx, LTQ_ASC_RIR(0)),
74 IRQ_RES(err, LTQ_ASC_EIR(0)),
75};
76
77static struct resource ltq_asc1_resources[] = {
78 {
79 .name = "asc1",
80 .start = LTQ_ASC1_BASE_ADDR,
81 .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
82 .flags = IORESOURCE_MEM,
83 },
84 IRQ_RES(tx, LTQ_ASC_TIR(1)),
85 IRQ_RES(rx, LTQ_ASC_RIR(1)),
86 IRQ_RES(err, LTQ_ASC_EIR(1)),
87};
88
89void __init ltq_register_asc(int port)
90{
91 switch (port) {
92 case 0:
93 platform_device_register_simple("ltq_asc", 0,
94 ltq_asc0_resources, ARRAY_SIZE(ltq_asc0_resources));
95 break;
96 case 1:
97 platform_device_register_simple("ltq_asc", 1,
98 ltq_asc1_resources, ARRAY_SIZE(ltq_asc1_resources));
99 break;
100 default:
101 break;
102 }
103}
104
105#ifdef CONFIG_PCI
106/* pci */
107static struct platform_device ltq_pci = {
108 .name = "ltq_pci",
109 .num_resources = 0,
110};
111
112void __init ltq_register_pci(struct ltq_pci_data *data)
113{
114 ltq_pci.dev.platform_data = data;
115 platform_device_register(&ltq_pci);
116}
117#else
118void __init ltq_register_pci(struct ltq_pci_data *data)
119{
120 pr_err("kernel is compiled without PCI support\n");
121}
122#endif
diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h
new file mode 100644
index 000000000000..2947bb19a528
--- /dev/null
+++ b/arch/mips/lantiq/devices.h
@@ -0,0 +1,23 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_DEVICES_H__
10#define _LTQ_DEVICES_H__
11
12#include <lantiq_platform.h>
13#include <linux/mtd/physmap.h>
14
15#define IRQ_RES(resname, irq) \
16 {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
17
18extern void ltq_register_nor(struct physmap_flash_data *data);
19extern void ltq_register_wdt(void);
20extern void ltq_register_asc(int port);
21extern void ltq_register_pci(struct ltq_pci_data *data);
22
23#endif
diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
new file mode 100644
index 000000000000..972e05f87631
--- /dev/null
+++ b/arch/mips/lantiq/early_printk.c
@@ -0,0 +1,33 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/cpu.h>
11
12#include <lantiq.h>
13#include <lantiq_soc.h>
14
15/* no ioremap possible at this early stage, lets use KSEG1 instead */
16#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
17#define ASC_BUF 1024
18#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048))
19#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020))
20#define TXMASK 0x3F00
21#define TXOFFSET 8
22
23void prom_putchar(char c)
24{
25 unsigned long flags;
26
27 local_irq_save(flags);
28 do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
29 if (c == '\n')
30 ltq_w32('\r', LTQ_ASC_TBUF);
31 ltq_w32(c, LTQ_ASC_TBUF);
32 local_irq_restore(flags);
33}
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
new file mode 100644
index 000000000000..fc89795cafdb
--- /dev/null
+++ b/arch/mips/lantiq/irq.c
@@ -0,0 +1,326 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
8 */
9
10#include <linux/interrupt.h>
11#include <linux/ioport.h>
12
13#include <asm/bootinfo.h>
14#include <asm/irq_cpu.h>
15
16#include <lantiq_soc.h>
17#include <irq.h>
18
19/* register definitions */
20#define LTQ_ICU_IM0_ISR 0x0000
21#define LTQ_ICU_IM0_IER 0x0008
22#define LTQ_ICU_IM0_IOSR 0x0010
23#define LTQ_ICU_IM0_IRSR 0x0018
24#define LTQ_ICU_IM0_IMR 0x0020
25#define LTQ_ICU_IM1_ISR 0x0028
26#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
27
28#define LTQ_EIU_EXIN_C 0x0000
29#define LTQ_EIU_EXIN_INIC 0x0004
30#define LTQ_EIU_EXIN_INEN 0x000C
31
32/* irq numbers used by the external interrupt unit (EIU) */
33#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
34#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
35#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
36#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
37#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
38#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
39#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
40
41#define MAX_EIU 6
42
43/* irqs generated by device attached to the EBU need to be acked in
44 * a special manner
45 */
46#define LTQ_ICU_EBU_IRQ 22
47
48#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
49#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
50
51#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
52#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
53
54static unsigned short ltq_eiu_irq[MAX_EIU] = {
55 LTQ_EIU_IR0,
56 LTQ_EIU_IR1,
57 LTQ_EIU_IR2,
58 LTQ_EIU_IR3,
59 LTQ_EIU_IR4,
60 LTQ_EIU_IR5,
61};
62
63static struct resource ltq_icu_resource = {
64 .name = "icu",
65 .start = LTQ_ICU_BASE_ADDR,
66 .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1,
67 .flags = IORESOURCE_MEM,
68};
69
70static struct resource ltq_eiu_resource = {
71 .name = "eiu",
72 .start = LTQ_EIU_BASE_ADDR,
73 .end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
74 .flags = IORESOURCE_MEM,
75};
76
77static void __iomem *ltq_icu_membase;
78static void __iomem *ltq_eiu_membase;
79
80void ltq_disable_irq(struct irq_data *d)
81{
82 u32 ier = LTQ_ICU_IM0_IER;
83 int irq_nr = d->irq - INT_NUM_IRQ0;
84
85 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
86 irq_nr %= INT_NUM_IM_OFFSET;
87 ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
88}
89
90void ltq_mask_and_ack_irq(struct irq_data *d)
91{
92 u32 ier = LTQ_ICU_IM0_IER;
93 u32 isr = LTQ_ICU_IM0_ISR;
94 int irq_nr = d->irq - INT_NUM_IRQ0;
95
96 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
97 isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
98 irq_nr %= INT_NUM_IM_OFFSET;
99 ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
100 ltq_icu_w32((1 << irq_nr), isr);
101}
102
103static void ltq_ack_irq(struct irq_data *d)
104{
105 u32 isr = LTQ_ICU_IM0_ISR;
106 int irq_nr = d->irq - INT_NUM_IRQ0;
107
108 isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
109 irq_nr %= INT_NUM_IM_OFFSET;
110 ltq_icu_w32((1 << irq_nr), isr);
111}
112
113void ltq_enable_irq(struct irq_data *d)
114{
115 u32 ier = LTQ_ICU_IM0_IER;
116 int irq_nr = d->irq - INT_NUM_IRQ0;
117
118 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
119 irq_nr %= INT_NUM_IM_OFFSET;
120 ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
121}
122
123static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
124{
125 int i;
126 int irq_nr = d->irq - INT_NUM_IRQ0;
127
128 ltq_enable_irq(d);
129 for (i = 0; i < MAX_EIU; i++) {
130 if (irq_nr == ltq_eiu_irq[i]) {
131 /* low level - we should really handle set_type */
132 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
133 (0x6 << (i * 4)), LTQ_EIU_EXIN_C);
134 /* clear all pending */
135 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i),
136 LTQ_EIU_EXIN_INIC);
137 /* enable */
138 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i),
139 LTQ_EIU_EXIN_INEN);
140 break;
141 }
142 }
143
144 return 0;
145}
146
147static void ltq_shutdown_eiu_irq(struct irq_data *d)
148{
149 int i;
150 int irq_nr = d->irq - INT_NUM_IRQ0;
151
152 ltq_disable_irq(d);
153 for (i = 0; i < MAX_EIU; i++) {
154 if (irq_nr == ltq_eiu_irq[i]) {
155 /* disable */
156 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i),
157 LTQ_EIU_EXIN_INEN);
158 break;
159 }
160 }
161}
162
163static struct irq_chip ltq_irq_type = {
164 "icu",
165 .irq_enable = ltq_enable_irq,
166 .irq_disable = ltq_disable_irq,
167 .irq_unmask = ltq_enable_irq,
168 .irq_ack = ltq_ack_irq,
169 .irq_mask = ltq_disable_irq,
170 .irq_mask_ack = ltq_mask_and_ack_irq,
171};
172
173static struct irq_chip ltq_eiu_type = {
174 "eiu",
175 .irq_startup = ltq_startup_eiu_irq,
176 .irq_shutdown = ltq_shutdown_eiu_irq,
177 .irq_enable = ltq_enable_irq,
178 .irq_disable = ltq_disable_irq,
179 .irq_unmask = ltq_enable_irq,
180 .irq_ack = ltq_ack_irq,
181 .irq_mask = ltq_disable_irq,
182 .irq_mask_ack = ltq_mask_and_ack_irq,
183};
184
185static void ltq_hw_irqdispatch(int module)
186{
187 u32 irq;
188
189 irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
190 if (irq == 0)
191 return;
192
193 /* silicon bug causes only the msb set to 1 to be valid. all
194 * other bits might be bogus
195 */
196 irq = __fls(irq);
197 do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
198
199 /* if this is a EBU irq, we need to ack it or get a deadlock */
200 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
201 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
202 LTQ_EBU_PCC_ISTAT);
203}
204
205#define DEFINE_HWx_IRQDISPATCH(x) \
206 static void ltq_hw ## x ## _irqdispatch(void) \
207 { \
208 ltq_hw_irqdispatch(x); \
209 }
210DEFINE_HWx_IRQDISPATCH(0)
211DEFINE_HWx_IRQDISPATCH(1)
212DEFINE_HWx_IRQDISPATCH(2)
213DEFINE_HWx_IRQDISPATCH(3)
214DEFINE_HWx_IRQDISPATCH(4)
215
216static void ltq_hw5_irqdispatch(void)
217{
218 do_IRQ(MIPS_CPU_TIMER_IRQ);
219}
220
221asmlinkage void plat_irq_dispatch(void)
222{
223 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
224 unsigned int i;
225
226 if (pending & CAUSEF_IP7) {
227 do_IRQ(MIPS_CPU_TIMER_IRQ);
228 goto out;
229 } else {
230 for (i = 0; i < 5; i++) {
231 if (pending & (CAUSEF_IP2 << i)) {
232 ltq_hw_irqdispatch(i);
233 goto out;
234 }
235 }
236 }
237 pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
238
239out:
240 return;
241}
242
243static struct irqaction cascade = {
244 .handler = no_action,
245 .flags = IRQF_DISABLED,
246 .name = "cascade",
247};
248
249void __init arch_init_irq(void)
250{
251 int i;
252
253 if (insert_resource(&iomem_resource, &ltq_icu_resource) < 0)
254 panic("Failed to insert icu memory\n");
255
256 if (request_mem_region(ltq_icu_resource.start,
257 resource_size(&ltq_icu_resource), "icu") < 0)
258 panic("Failed to request icu memory\n");
259
260 ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
261 resource_size(&ltq_icu_resource));
262 if (!ltq_icu_membase)
263 panic("Failed to remap icu memory\n");
264
265 if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
266 panic("Failed to insert eiu memory\n");
267
268 if (request_mem_region(ltq_eiu_resource.start,
269 resource_size(&ltq_eiu_resource), "eiu") < 0)
270 panic("Failed to request eiu memory\n");
271
272 ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
273 resource_size(&ltq_eiu_resource));
274 if (!ltq_eiu_membase)
275 panic("Failed to remap eiu memory\n");
276
277 /* make sure all irqs are turned off by default */
278 for (i = 0; i < 5; i++)
279 ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
280
281 /* clear all possibly pending interrupts */
282 ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
283
284 mips_cpu_irq_init();
285
286 for (i = 2; i <= 6; i++)
287 setup_irq(i, &cascade);
288
289 if (cpu_has_vint) {
290 pr_info("Setting up vectored interrupts\n");
291 set_vi_handler(2, ltq_hw0_irqdispatch);
292 set_vi_handler(3, ltq_hw1_irqdispatch);
293 set_vi_handler(4, ltq_hw2_irqdispatch);
294 set_vi_handler(5, ltq_hw3_irqdispatch);
295 set_vi_handler(6, ltq_hw4_irqdispatch);
296 set_vi_handler(7, ltq_hw5_irqdispatch);
297 }
298
299 for (i = INT_NUM_IRQ0;
300 i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
301 if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
302 (i == LTQ_EIU_IR2))
303 irq_set_chip_and_handler(i, &ltq_eiu_type,
304 handle_level_irq);
305 /* EIU3-5 only exist on ar9 and vr9 */
306 else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) ||
307 (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9()))
308 irq_set_chip_and_handler(i, &ltq_eiu_type,
309 handle_level_irq);
310 else
311 irq_set_chip_and_handler(i, &ltq_irq_type,
312 handle_level_irq);
313
314#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
315 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
316 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
317#else
318 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
319 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
320#endif
321}
322
323unsigned int __cpuinit get_c0_compare_int(void)
324{
325 return CP0_LEGACY_COMPARE_IRQ;
326}
diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h
new file mode 100644
index 000000000000..7e01b8c484eb
--- /dev/null
+++ b/arch/mips/lantiq/machtypes.h
@@ -0,0 +1,20 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LANTIQ_MACH_H__
10#define _LANTIQ_MACH_H__
11
12#include <asm/mips_machine.h>
13
14enum lantiq_mach_type {
15 LTQ_MACH_GENERIC = 0,
16 LTQ_MACH_EASY50712, /* Danube evaluation board */
17 LTQ_MACH_EASY50601, /* Amazon SE evaluation board */
18};
19
20#endif
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
new file mode 100644
index 000000000000..56ba007bf1e5
--- /dev/null
+++ b/arch/mips/lantiq/prom.c
@@ -0,0 +1,71 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/module.h>
10#include <linux/clk.h>
11#include <asm/bootinfo.h>
12#include <asm/time.h>
13
14#include <lantiq.h>
15
16#include "prom.h"
17#include "clk.h"
18
19static struct ltq_soc_info soc_info;
20
21unsigned int ltq_get_cpu_ver(void)
22{
23 return soc_info.rev;
24}
25EXPORT_SYMBOL(ltq_get_cpu_ver);
26
27unsigned int ltq_get_soc_type(void)
28{
29 return soc_info.type;
30}
31EXPORT_SYMBOL(ltq_get_soc_type);
32
33const char *get_system_type(void)
34{
35 return soc_info.sys_type;
36}
37
38void prom_free_prom_memory(void)
39{
40}
41
42static void __init prom_init_cmdline(void)
43{
44 int argc = fw_arg0;
45 char **argv = (char **) KSEG1ADDR(fw_arg1);
46 int i;
47
48 for (i = 0; i < argc; i++) {
49 char *p = (char *) KSEG1ADDR(argv[i]);
50
51 if (p && *p) {
52 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
53 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
54 }
55 }
56}
57
58void __init prom_init(void)
59{
60 struct clk *clk;
61
62 ltq_soc_detect(&soc_info);
63 clk_init();
64 clk = clk_get(0, "cpu");
65 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
66 soc_info.name, soc_info.rev);
67 clk_put(clk);
68 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
69 pr_info("SoC: %s\n", soc_info.sys_type);
70 prom_init_cmdline();
71}
diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
new file mode 100644
index 000000000000..b4229d94280f
--- /dev/null
+++ b/arch/mips/lantiq/prom.h
@@ -0,0 +1,25 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_PROM_H__
10#define _LTQ_PROM_H__
11
12#define LTQ_SYS_TYPE_LEN 0x100
13
14struct ltq_soc_info {
15 unsigned char *name;
16 unsigned int rev;
17 unsigned int partnum;
18 unsigned int type;
19 unsigned char sys_type[LTQ_SYS_TYPE_LEN];
20};
21
22extern void ltq_soc_detect(struct ltq_soc_info *i);
23extern void ltq_soc_setup(void);
24
25#endif
diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c
new file mode 100644
index 000000000000..9b8af77ed0f9
--- /dev/null
+++ b/arch/mips/lantiq/setup.c
@@ -0,0 +1,66 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <asm/bootinfo.h>
14
15#include <lantiq_soc.h>
16
17#include "machtypes.h"
18#include "devices.h"
19#include "prom.h"
20
21void __init plat_mem_setup(void)
22{
23 /* assume 16M as default incase uboot fails to pass proper ramsize */
24 unsigned long memsize = 16;
25 char **envp = (char **) KSEG1ADDR(fw_arg2);
26
27 ioport_resource.start = IOPORT_RESOURCE_START;
28 ioport_resource.end = IOPORT_RESOURCE_END;
29 iomem_resource.start = IOMEM_RESOURCE_START;
30 iomem_resource.end = IOMEM_RESOURCE_END;
31
32 set_io_port_base((unsigned long) KSEG1);
33
34 while (*envp) {
35 char *e = (char *)KSEG1ADDR(*envp);
36 if (!strncmp(e, "memsize=", 8)) {
37 e += 8;
38 if (strict_strtoul(e, 0, &memsize))
39 pr_warn("bad memsize specified\n");
40 }
41 envp++;
42 }
43 memsize *= 1024 * 1024;
44 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
45}
46
47static int __init
48lantiq_setup(void)
49{
50 ltq_soc_setup();
51 mips_machine_setup();
52 return 0;
53}
54
55arch_initcall(lantiq_setup);
56
57static void __init
58lantiq_generic_init(void)
59{
60 /* Nothing to do */
61}
62
63MIPS_MACHINE(LTQ_MACH_GENERIC,
64 "Generic",
65 "Generic Lantiq based board",
66 lantiq_generic_init);
diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig
new file mode 100644
index 000000000000..2b857de36620
--- /dev/null
+++ b/arch/mips/lantiq/xway/Kconfig
@@ -0,0 +1,23 @@
1if SOC_XWAY
2
3menu "MIPS Machine"
4
5config LANTIQ_MACH_EASY50712
6 bool "Easy50712 - Danube"
7 default y
8
9endmenu
10
11endif
12
13if SOC_AMAZON_SE
14
15menu "MIPS Machine"
16
17config LANTIQ_MACH_EASY50601
18 bool "Easy50601 - Amazon SE"
19 default y
20
21endmenu
22
23endif
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
new file mode 100644
index 000000000000..c517f2e77563
--- /dev/null
+++ b/arch/mips/lantiq/xway/Makefile
@@ -0,0 +1,7 @@
1obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
2
3obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
4obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
5
6obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
7obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
new file mode 100644
index 000000000000..22d823acd536
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk-ase.c
@@ -0,0 +1,48 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/clk.h>
13
14#include <asm/time.h>
15#include <asm/irq.h>
16#include <asm/div64.h>
17
18#include <lantiq_soc.h>
19
20/* cgu registers */
21#define LTQ_CGU_SYS 0x0010
22
23unsigned int ltq_get_io_region_clock(void)
24{
25 return CLOCK_133M;
26}
27EXPORT_SYMBOL(ltq_get_io_region_clock);
28
29unsigned int ltq_get_fpi_bus_clock(int fpi)
30{
31 return CLOCK_133M;
32}
33EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
34
35unsigned int ltq_get_cpu_hz(void)
36{
37 if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
38 return CLOCK_266M;
39 else
40 return CLOCK_133M;
41}
42EXPORT_SYMBOL(ltq_get_cpu_hz);
43
44unsigned int ltq_get_fpi_hz(void)
45{
46 return CLOCK_133M;
47}
48EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
new file mode 100644
index 000000000000..ddd39593c581
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk-xway.c
@@ -0,0 +1,223 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/clk.h>
13
14#include <asm/time.h>
15#include <asm/irq.h>
16#include <asm/div64.h>
17
18#include <lantiq_soc.h>
19
20static unsigned int ltq_ram_clocks[] = {
21 CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
22#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
23
24#define BASIC_FREQUENCY_1 35328000
25#define BASIC_FREQUENCY_2 36000000
26#define BASIS_REQUENCY_USB 12000000
27
28#define GET_BITS(x, msb, lsb) \
29 (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
30
31#define LTQ_CGU_PLL0_CFG 0x0004
32#define LTQ_CGU_PLL1_CFG 0x0008
33#define LTQ_CGU_PLL2_CFG 0x000C
34#define LTQ_CGU_SYS 0x0010
35#define LTQ_CGU_UPDATE 0x0014
36#define LTQ_CGU_IF_CLK 0x0018
37#define LTQ_CGU_OSC_CON 0x001C
38#define LTQ_CGU_SMD 0x0020
39#define LTQ_CGU_CT1SR 0x0028
40#define LTQ_CGU_CT2SR 0x002C
41#define LTQ_CGU_PCMCR 0x0030
42#define LTQ_CGU_PCI_CR 0x0034
43#define LTQ_CGU_PD_PC 0x0038
44#define LTQ_CGU_FMR 0x003C
45
46#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
47 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
48#define CGU_PLL0_BYPASS \
49 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
50#define CGU_PLL0_CFG_DSMSEL \
51 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
52#define CGU_PLL0_CFG_FRAC_EN \
53 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
54#define CGU_PLL1_SRC \
55 (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
56#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
57 (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
58#define CGU_SYS_FPI_SEL (1 << 6)
59#define CGU_SYS_DDR_SEL 0x3
60#define CGU_PLL0_SRC (1 << 29)
61
62#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
63#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
64#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
65#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
66#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
67
68static unsigned int ltq_get_pll0_fdiv(void);
69
70static inline unsigned int get_input_clock(int pll)
71{
72 switch (pll) {
73 case 0:
74 if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
75 return BASIS_REQUENCY_USB;
76 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
77 return BASIC_FREQUENCY_1;
78 else
79 return BASIC_FREQUENCY_2;
80 case 1:
81 if (CGU_PLL1_SRC)
82 return BASIS_REQUENCY_USB;
83 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
84 return BASIC_FREQUENCY_1;
85 else
86 return BASIC_FREQUENCY_2;
87 case 2:
88 switch (CGU_PLL2_SRC) {
89 case 0:
90 return ltq_get_pll0_fdiv();
91 case 1:
92 return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
93 BASIC_FREQUENCY_1 :
94 BASIC_FREQUENCY_2;
95 case 2:
96 return BASIS_REQUENCY_USB;
97 }
98 default:
99 return 0;
100 }
101}
102
103static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
104{
105 u64 res, clock = get_input_clock(pll);
106
107 res = num * clock;
108 do_div(res, den);
109 return res;
110}
111
112static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
113 unsigned int K)
114{
115 unsigned int num = ((N + 1) << 10) + K;
116 unsigned int den = (M + 1) << 10;
117
118 return cal_dsm(pll, num, den);
119}
120
121static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
122 unsigned int K)
123{
124 unsigned int num = ((N + 1) << 11) + K + 512;
125 unsigned int den = (M + 1) << 11;
126
127 return cal_dsm(pll, num, den);
128}
129
130static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
131 unsigned int K)
132{
133 unsigned int num = K >= 512 ?
134 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
135 unsigned int den = (M + 1) << 12;
136
137 return cal_dsm(pll, num, den);
138}
139
140static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
141 unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
142{
143 if (!dsmsel)
144 return mash_dsm(pll, M, N, K);
145 else if (!phase_div_en)
146 return mash_dsm(pll, M, N, K);
147 else
148 return ssff_dsm_2(pll, M, N, K);
149}
150
151static inline unsigned int ltq_get_pll0_fosc(void)
152{
153 if (CGU_PLL0_BYPASS)
154 return get_input_clock(0);
155 else
156 return !CGU_PLL0_CFG_FRAC_EN
157 ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
158 CGU_PLL0_CFG_DSMSEL,
159 CGU_PLL0_PHASE_DIVIDER_ENABLE)
160 : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
161 CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
162 CGU_PLL0_PHASE_DIVIDER_ENABLE);
163}
164
165static unsigned int ltq_get_pll0_fdiv(void)
166{
167 unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
168
169 return (ltq_get_pll0_fosc() + (div >> 1)) / div;
170}
171
172unsigned int ltq_get_io_region_clock(void)
173{
174 unsigned int ret = ltq_get_pll0_fosc();
175
176 switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
177 default:
178 case 0:
179 return (ret + 1) / 2;
180 case 1:
181 return (ret * 2 + 2) / 5;
182 case 2:
183 return (ret + 1) / 3;
184 case 3:
185 return (ret + 2) / 4;
186 }
187}
188EXPORT_SYMBOL(ltq_get_io_region_clock);
189
190unsigned int ltq_get_fpi_bus_clock(int fpi)
191{
192 unsigned int ret = ltq_get_io_region_clock();
193
194 if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
195 ret >>= 1;
196 return ret;
197}
198EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
199
200unsigned int ltq_get_cpu_hz(void)
201{
202 switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
203 case 0:
204 return CLOCK_333M;
205 case 4:
206 return DDR_HZ;
207 case 8:
208 return DDR_HZ << 1;
209 default:
210 return DDR_HZ >> 1;
211 }
212}
213EXPORT_SYMBOL(ltq_get_cpu_hz);
214
215unsigned int ltq_get_fpi_hz(void)
216{
217 unsigned int ddr_clock = DDR_HZ;
218
219 if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
220 return ddr_clock >> 1;
221 return ddr_clock;
222}
223EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
new file mode 100644
index 000000000000..e09e789dfc27
--- /dev/null
+++ b/arch/mips/lantiq/xway/devices.c
@@ -0,0 +1,121 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/string.h>
13#include <linux/mtd/physmap.h>
14#include <linux/kernel.h>
15#include <linux/reboot.h>
16#include <linux/platform_device.h>
17#include <linux/leds.h>
18#include <linux/etherdevice.h>
19#include <linux/reboot.h>
20#include <linux/time.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/leds.h>
24
25#include <asm/bootinfo.h>
26#include <asm/irq.h>
27
28#include <lantiq_soc.h>
29#include <lantiq_irq.h>
30#include <lantiq_platform.h>
31
32#include "devices.h"
33
34/* gpio */
35static struct resource ltq_gpio_resource[] = {
36 {
37 .name = "gpio0",
38 .start = LTQ_GPIO0_BASE_ADDR,
39 .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
40 .flags = IORESOURCE_MEM,
41 }, {
42 .name = "gpio1",
43 .start = LTQ_GPIO1_BASE_ADDR,
44 .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
45 .flags = IORESOURCE_MEM,
46 }, {
47 .name = "gpio2",
48 .start = LTQ_GPIO2_BASE_ADDR,
49 .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
50 .flags = IORESOURCE_MEM,
51 }
52};
53
54void __init ltq_register_gpio(void)
55{
56 platform_device_register_simple("ltq_gpio", 0,
57 &ltq_gpio_resource[0], 1);
58 platform_device_register_simple("ltq_gpio", 1,
59 &ltq_gpio_resource[1], 1);
60
61 /* AR9 and VR9 have an extra gpio block */
62 if (ltq_is_ar9() || ltq_is_vr9()) {
63 platform_device_register_simple("ltq_gpio", 2,
64 &ltq_gpio_resource[2], 1);
65 }
66}
67
68/* serial to parallel conversion */
69static struct resource ltq_stp_resource = {
70 .name = "stp",
71 .start = LTQ_STP_BASE_ADDR,
72 .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
73 .flags = IORESOURCE_MEM,
74};
75
76void __init ltq_register_gpio_stp(void)
77{
78 platform_device_register_simple("ltq_stp", 0, &ltq_stp_resource, 1);
79}
80
81/* asc ports - amazon se has its own serial mapping */
82static struct resource ltq_ase_asc_resources[] = {
83 {
84 .name = "asc0",
85 .start = LTQ_ASC1_BASE_ADDR,
86 .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 IRQ_RES(tx, LTQ_ASC_ASE_TIR),
90 IRQ_RES(rx, LTQ_ASC_ASE_RIR),
91 IRQ_RES(err, LTQ_ASC_ASE_EIR),
92};
93
94void __init ltq_register_ase_asc(void)
95{
96 platform_device_register_simple("ltq_asc", 0,
97 ltq_ase_asc_resources, ARRAY_SIZE(ltq_ase_asc_resources));
98}
99
100/* ethernet */
101static struct resource ltq_etop_resources = {
102 .name = "etop",
103 .start = LTQ_ETOP_BASE_ADDR,
104 .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
105 .flags = IORESOURCE_MEM,
106};
107
108static struct platform_device ltq_etop = {
109 .name = "ltq_etop",
110 .resource = &ltq_etop_resources,
111 .num_resources = 1,
112};
113
114void __init
115ltq_register_etop(struct ltq_eth_data *eth)
116{
117 if (eth) {
118 ltq_etop.dev.platform_data = eth;
119 platform_device_register(&ltq_etop);
120 }
121}
diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h
new file mode 100644
index 000000000000..e90493471bc1
--- /dev/null
+++ b/arch/mips/lantiq/xway/devices.h
@@ -0,0 +1,20 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_DEVICES_XWAY_H__
10#define _LTQ_DEVICES_XWAY_H__
11
12#include "../devices.h"
13#include <linux/phy.h>
14
15extern void ltq_register_gpio(void);
16extern void ltq_register_gpio_stp(void);
17extern void ltq_register_ase_asc(void);
18extern void ltq_register_etop(struct ltq_eth_data *eth);
19
20#endif
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
new file mode 100644
index 000000000000..4278a459d6c4
--- /dev/null
+++ b/arch/mips/lantiq/xway/dma.c
@@ -0,0 +1,253 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
16 */
17
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/dma-mapping.h>
22
23#include <lantiq_soc.h>
24#include <xway_dma.h>
25
26#define LTQ_DMA_CTRL 0x10
27#define LTQ_DMA_CPOLL 0x14
28#define LTQ_DMA_CS 0x18
29#define LTQ_DMA_CCTRL 0x1C
30#define LTQ_DMA_CDBA 0x20
31#define LTQ_DMA_CDLEN 0x24
32#define LTQ_DMA_CIS 0x28
33#define LTQ_DMA_CIE 0x2C
34#define LTQ_DMA_PS 0x40
35#define LTQ_DMA_PCTRL 0x44
36#define LTQ_DMA_IRNEN 0xf4
37
38#define DMA_DESCPT BIT(3) /* descriptor complete irq */
39#define DMA_TX BIT(8) /* TX channel direction */
40#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
41#define DMA_PDEN BIT(6) /* enable packet drop */
42#define DMA_CHAN_RST BIT(1) /* channel on / off bit */
43#define DMA_RESET BIT(0) /* channel on / off bit */
44#define DMA_IRQ_ACK 0x7e /* IRQ status register */
45#define DMA_POLL BIT(31) /* turn on channel polling */
46#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
47#define DMA_2W_BURST BIT(1) /* 2 word burst length */
48#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
49#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */
50#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
51
52#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
53#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
54#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
55 ltq_dma_membase + (z))
56
57static struct resource ltq_dma_resource = {
58 .name = "dma",
59 .start = LTQ_DMA_BASE_ADDR,
60 .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
61 .flags = IORESOURCE_MEM,
62};
63
64static void __iomem *ltq_dma_membase;
65
66void
67ltq_dma_enable_irq(struct ltq_dma_channel *ch)
68{
69 unsigned long flags;
70
71 local_irq_save(flags);
72 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
73 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
74 local_irq_restore(flags);
75}
76EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
77
78void
79ltq_dma_disable_irq(struct ltq_dma_channel *ch)
80{
81 unsigned long flags;
82
83 local_irq_save(flags);
84 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
85 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
86 local_irq_restore(flags);
87}
88EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
89
90void
91ltq_dma_ack_irq(struct ltq_dma_channel *ch)
92{
93 unsigned long flags;
94
95 local_irq_save(flags);
96 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
97 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
98 local_irq_restore(flags);
99}
100EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
101
102void
103ltq_dma_open(struct ltq_dma_channel *ch)
104{
105 unsigned long flag;
106
107 local_irq_save(flag);
108 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
109 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
110 ltq_dma_enable_irq(ch);
111 local_irq_restore(flag);
112}
113EXPORT_SYMBOL_GPL(ltq_dma_open);
114
115void
116ltq_dma_close(struct ltq_dma_channel *ch)
117{
118 unsigned long flag;
119
120 local_irq_save(flag);
121 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
122 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
123 ltq_dma_disable_irq(ch);
124 local_irq_restore(flag);
125}
126EXPORT_SYMBOL_GPL(ltq_dma_close);
127
128static void
129ltq_dma_alloc(struct ltq_dma_channel *ch)
130{
131 unsigned long flags;
132
133 ch->desc = 0;
134 ch->desc_base = dma_alloc_coherent(NULL,
135 LTQ_DESC_NUM * LTQ_DESC_SIZE,
136 &ch->phys, GFP_ATOMIC);
137 memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
138
139 local_irq_save(flags);
140 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
141 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
142 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
143 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
144 wmb();
145 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
146 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
147 ;
148 local_irq_restore(flags);
149}
150
151void
152ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
153{
154 unsigned long flags;
155
156 ltq_dma_alloc(ch);
157
158 local_irq_save(flags);
159 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
160 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
161 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
162 local_irq_restore(flags);
163}
164EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
165
166void
167ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
168{
169 unsigned long flags;
170
171 ltq_dma_alloc(ch);
172
173 local_irq_save(flags);
174 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
175 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
176 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
177 local_irq_restore(flags);
178}
179EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
180
181void
182ltq_dma_free(struct ltq_dma_channel *ch)
183{
184 if (!ch->desc_base)
185 return;
186 ltq_dma_close(ch);
187 dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE,
188 ch->desc_base, ch->phys);
189}
190EXPORT_SYMBOL_GPL(ltq_dma_free);
191
192void
193ltq_dma_init_port(int p)
194{
195 ltq_dma_w32(p, LTQ_DMA_PS);
196 switch (p) {
197 case DMA_PORT_ETOP:
198 /*
199 * Tell the DMA engine to swap the endianess of data frames and
200 * drop packets if the channel arbitration fails.
201 */
202 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN,
203 LTQ_DMA_PCTRL);
204 break;
205
206 case DMA_PORT_DEU:
207 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
208 LTQ_DMA_PCTRL);
209 break;
210
211 default:
212 break;
213 }
214}
215EXPORT_SYMBOL_GPL(ltq_dma_init_port);
216
217int __init
218ltq_dma_init(void)
219{
220 int i;
221
222 /* insert and request the memory region */
223 if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
224 panic("Failed to insert dma memory\n");
225
226 if (request_mem_region(ltq_dma_resource.start,
227 resource_size(&ltq_dma_resource), "dma") < 0)
228 panic("Failed to request dma memory\n");
229
230 /* remap dma register range */
231 ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
232 resource_size(&ltq_dma_resource));
233 if (!ltq_dma_membase)
234 panic("Failed to remap dma memory\n");
235
236 /* power up and reset the dma engine */
237 ltq_pmu_enable(PMU_DMA);
238 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
239
240 /* disable all interrupts */
241 ltq_dma_w32(0, LTQ_DMA_IRNEN);
242
243 /* reset/configure each channel */
244 for (i = 0; i < DMA_MAX_CHANNEL; i++) {
245 ltq_dma_w32(i, LTQ_DMA_CS);
246 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
247 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
248 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
249 }
250 return 0;
251}
252
253postcore_initcall(ltq_dma_init);
diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
new file mode 100644
index 000000000000..66eb52fa50a1
--- /dev/null
+++ b/arch/mips/lantiq/xway/ebu.c
@@ -0,0 +1,53 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * EBU - the external bus unit attaches PCI, NOR and NAND
7 *
8 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/version.h>
14#include <linux/ioport.h>
15
16#include <lantiq_soc.h>
17
18/* all access to the ebu must be locked */
19DEFINE_SPINLOCK(ebu_lock);
20EXPORT_SYMBOL_GPL(ebu_lock);
21
22static struct resource ltq_ebu_resource = {
23 .name = "ebu",
24 .start = LTQ_EBU_BASE_ADDR,
25 .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
26 .flags = IORESOURCE_MEM,
27};
28
29/* remapped base addr of the clock unit and external bus unit */
30void __iomem *ltq_ebu_membase;
31
32static int __init lantiq_ebu_init(void)
33{
34 /* insert and request the memory region */
35 if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
36 panic("Failed to insert ebu memory\n");
37
38 if (request_mem_region(ltq_ebu_resource.start,
39 resource_size(&ltq_ebu_resource), "ebu") < 0)
40 panic("Failed to request ebu memory\n");
41
42 /* remap ebu register range */
43 ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
44 resource_size(&ltq_ebu_resource));
45 if (!ltq_ebu_membase)
46 panic("Failed to remap ebu memory\n");
47
48 /* make sure to unprotect the memory region where flash is located */
49 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
50 return 0;
51}
52
53postcore_initcall(lantiq_ebu_init);
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
new file mode 100644
index 000000000000..a321451a5455
--- /dev/null
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -0,0 +1,195 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/gpio.h>
13#include <linux/ioport.h>
14#include <linux/io.h>
15
16#include <lantiq_soc.h>
17
18#define LTQ_GPIO_OUT 0x00
19#define LTQ_GPIO_IN 0x04
20#define LTQ_GPIO_DIR 0x08
21#define LTQ_GPIO_ALTSEL0 0x0C
22#define LTQ_GPIO_ALTSEL1 0x10
23#define LTQ_GPIO_OD 0x14
24
25#define PINS_PER_PORT 16
26#define MAX_PORTS 3
27
28#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
29#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r)
30#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r)
31
32struct ltq_gpio {
33 void __iomem *membase;
34 struct gpio_chip chip;
35};
36
37static struct ltq_gpio ltq_gpio_port[MAX_PORTS];
38
39int gpio_to_irq(unsigned int gpio)
40{
41 return -EINVAL;
42}
43EXPORT_SYMBOL(gpio_to_irq);
44
45int irq_to_gpio(unsigned int gpio)
46{
47 return -EINVAL;
48}
49EXPORT_SYMBOL(irq_to_gpio);
50
51int ltq_gpio_request(unsigned int pin, unsigned int alt0,
52 unsigned int alt1, unsigned int dir, const char *name)
53{
54 int id = 0;
55
56 if (pin >= (MAX_PORTS * PINS_PER_PORT))
57 return -EINVAL;
58 if (gpio_request(pin, name)) {
59 pr_err("failed to setup lantiq gpio: %s\n", name);
60 return -EBUSY;
61 }
62 if (dir)
63 gpio_direction_output(pin, 1);
64 else
65 gpio_direction_input(pin);
66 while (pin >= PINS_PER_PORT) {
67 pin -= PINS_PER_PORT;
68 id++;
69 }
70 if (alt0)
71 ltq_gpio_setbit(ltq_gpio_port[id].membase,
72 LTQ_GPIO_ALTSEL0, pin);
73 else
74 ltq_gpio_clearbit(ltq_gpio_port[id].membase,
75 LTQ_GPIO_ALTSEL0, pin);
76 if (alt1)
77 ltq_gpio_setbit(ltq_gpio_port[id].membase,
78 LTQ_GPIO_ALTSEL1, pin);
79 else
80 ltq_gpio_clearbit(ltq_gpio_port[id].membase,
81 LTQ_GPIO_ALTSEL1, pin);
82 return 0;
83}
84EXPORT_SYMBOL(ltq_gpio_request);
85
86static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
87{
88 struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
89
90 if (value)
91 ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
92 else
93 ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
94}
95
96static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset)
97{
98 struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
99
100 return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset);
101}
102
103static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
104{
105 struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
106
107 ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
108 ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
109
110 return 0;
111}
112
113static int ltq_gpio_direction_output(struct gpio_chip *chip,
114 unsigned int offset, int value)
115{
116 struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
117
118 ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
119 ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
120 ltq_gpio_set(chip, offset, value);
121
122 return 0;
123}
124
125static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
126{
127 struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
128
129 ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
130 ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
131 return 0;
132}
133
134static int ltq_gpio_probe(struct platform_device *pdev)
135{
136 struct resource *res;
137
138 if (pdev->id >= MAX_PORTS) {
139 dev_err(&pdev->dev, "invalid gpio port %d\n",
140 pdev->id);
141 return -EINVAL;
142 }
143 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
144 if (!res) {
145 dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
146 pdev->id);
147 return -ENOENT;
148 }
149 res = devm_request_mem_region(&pdev->dev, res->start,
150 resource_size(res), dev_name(&pdev->dev));
151 if (!res) {
152 dev_err(&pdev->dev,
153 "failed to request memory for gpio port %d\n",
154 pdev->id);
155 return -EBUSY;
156 }
157 ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev,
158 res->start, resource_size(res));
159 if (!ltq_gpio_port[pdev->id].membase) {
160 dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n",
161 pdev->id);
162 return -ENOMEM;
163 }
164 ltq_gpio_port[pdev->id].chip.label = "ltq_gpio";
165 ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input;
166 ltq_gpio_port[pdev->id].chip.direction_output =
167 ltq_gpio_direction_output;
168 ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get;
169 ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
170 ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
171 ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
172 ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
173 platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
174 return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
175}
176
177static struct platform_driver
178ltq_gpio_driver = {
179 .probe = ltq_gpio_probe,
180 .driver = {
181 .name = "ltq_gpio",
182 .owner = THIS_MODULE,
183 },
184};
185
186int __init ltq_gpio_init(void)
187{
188 int ret = platform_driver_register(&ltq_gpio_driver);
189
190 if (ret)
191 pr_info("ltq_gpio : Error registering platfom driver!");
192 return ret;
193}
194
195postcore_initcall(ltq_gpio_init);
diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c
new file mode 100644
index 000000000000..a479355abdb9
--- /dev/null
+++ b/arch/mips/lantiq/xway/gpio_ebu.c
@@ -0,0 +1,126 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/platform_device.h>
13#include <linux/mutex.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16
17#include <lantiq_soc.h>
18
19/*
20 * By attaching hardware latches to the EBU it is possible to create output
21 * only gpios. This driver configures a special memory address, which when
22 * written to outputs 16 bit to the latches.
23 */
24
25#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */
26#define LTQ_EBU_WP 0x80000000 /* write protect bit */
27
28/* we keep a shadow value of the last value written to the ebu */
29static int ltq_ebu_gpio_shadow = 0x0;
30static void __iomem *ltq_ebu_gpio_membase;
31
32static void ltq_ebu_apply(void)
33{
34 unsigned long flags;
35
36 spin_lock_irqsave(&ebu_lock, flags);
37 ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
38 *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow;
39 ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
40 spin_unlock_irqrestore(&ebu_lock, flags);
41}
42
43static void ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
44{
45 if (value)
46 ltq_ebu_gpio_shadow |= (1 << offset);
47 else
48 ltq_ebu_gpio_shadow &= ~(1 << offset);
49 ltq_ebu_apply();
50}
51
52static int ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset,
53 int value)
54{
55 ltq_ebu_set(chip, offset, value);
56
57 return 0;
58}
59
60static struct gpio_chip ltq_ebu_chip = {
61 .label = "ltq_ebu",
62 .direction_output = ltq_ebu_direction_output,
63 .set = ltq_ebu_set,
64 .base = 72,
65 .ngpio = 16,
66 .can_sleep = 1,
67 .owner = THIS_MODULE,
68};
69
70static int ltq_ebu_probe(struct platform_device *pdev)
71{
72 int ret = 0;
73 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
74
75 if (!res) {
76 dev_err(&pdev->dev, "failed to get memory resource\n");
77 return -ENOENT;
78 }
79
80 res = devm_request_mem_region(&pdev->dev, res->start,
81 resource_size(res), dev_name(&pdev->dev));
82 if (!res) {
83 dev_err(&pdev->dev, "failed to request memory resource\n");
84 return -EBUSY;
85 }
86
87 ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start,
88 resource_size(res));
89 if (!ltq_ebu_gpio_membase) {
90 dev_err(&pdev->dev, "Failed to ioremap mem region\n");
91 return -ENOMEM;
92 }
93
94 /* grab the default shadow value passed form the platform code */
95 ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data;
96
97 /* tell the ebu controller which memory address we will be using */
98 ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1);
99
100 /* write protect the region */
101 ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
102
103 ret = gpiochip_add(&ltq_ebu_chip);
104 if (!ret)
105 ltq_ebu_apply();
106 return ret;
107}
108
109static struct platform_driver ltq_ebu_driver = {
110 .probe = ltq_ebu_probe,
111 .driver = {
112 .name = "ltq_ebu",
113 .owner = THIS_MODULE,
114 },
115};
116
117static int __init ltq_ebu_init(void)
118{
119 int ret = platform_driver_register(&ltq_ebu_driver);
120
121 if (ret)
122 pr_info("ltq_ebu : Error registering platfom driver!");
123 return ret;
124}
125
126postcore_initcall(ltq_ebu_init);
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
new file mode 100644
index 000000000000..67d59d690340
--- /dev/null
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -0,0 +1,157 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
7 *
8 */
9
10#include <linux/slab.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/platform_device.h>
15#include <linux/mutex.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <lantiq_soc.h>
20
21#define LTQ_STP_CON0 0x00
22#define LTQ_STP_CON1 0x04
23#define LTQ_STP_CPU0 0x08
24#define LTQ_STP_CPU1 0x0C
25#define LTQ_STP_AR 0x10
26
27#define LTQ_STP_CON_SWU (1 << 31)
28#define LTQ_STP_2HZ 0
29#define LTQ_STP_4HZ (1 << 23)
30#define LTQ_STP_8HZ (2 << 23)
31#define LTQ_STP_10HZ (3 << 23)
32#define LTQ_STP_SPEED_MASK (0xf << 23)
33#define LTQ_STP_UPD_FPI (1 << 31)
34#define LTQ_STP_UPD_MASK (3 << 30)
35#define LTQ_STP_ADSL_SRC (3 << 24)
36
37#define LTQ_STP_GROUP0 (1 << 0)
38
39#define LTQ_STP_RISING 0
40#define LTQ_STP_FALLING (1 << 26)
41#define LTQ_STP_EDGE_MASK (1 << 26)
42
43#define ltq_stp_r32(reg) __raw_readl(ltq_stp_membase + reg)
44#define ltq_stp_w32(val, reg) __raw_writel(val, ltq_stp_membase + reg)
45#define ltq_stp_w32_mask(clear, set, reg) \
46 ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \
47 ltq_stp_membase + (reg))
48
49static int ltq_stp_shadow = 0xffff;
50static void __iomem *ltq_stp_membase;
51
52static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
53{
54 if (value)
55 ltq_stp_shadow |= (1 << offset);
56 else
57 ltq_stp_shadow &= ~(1 << offset);
58 ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
59}
60
61static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
62 int value)
63{
64 ltq_stp_set(chip, offset, value);
65
66 return 0;
67}
68
69static struct gpio_chip ltq_stp_chip = {
70 .label = "ltq_stp",
71 .direction_output = ltq_stp_direction_output,
72 .set = ltq_stp_set,
73 .base = 48,
74 .ngpio = 24,
75 .can_sleep = 1,
76 .owner = THIS_MODULE,
77};
78
79static int ltq_stp_hw_init(void)
80{
81 /* the 3 pins used to control the external stp */
82 ltq_gpio_request(4, 1, 0, 1, "stp-st");
83 ltq_gpio_request(5, 1, 0, 1, "stp-d");
84 ltq_gpio_request(6, 1, 0, 1, "stp-sh");
85
86 /* sane defaults */
87 ltq_stp_w32(0, LTQ_STP_AR);
88 ltq_stp_w32(0, LTQ_STP_CPU0);
89 ltq_stp_w32(0, LTQ_STP_CPU1);
90 ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0);
91 ltq_stp_w32(0, LTQ_STP_CON1);
92
93 /* rising or falling edge */
94 ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
95
96 /* per default stp 15-0 are set */
97 ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
98
99 /* stp are update periodically by the FPI bus */
100 ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
101
102 /* set stp update speed */
103 ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
104
105 /* tell the hardware that pin (led) 0 and 1 are controlled
106 * by the dsl arc
107 */
108 ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
109
110 ltq_pmu_enable(PMU_LED);
111 return 0;
112}
113
114static int __devinit ltq_stp_probe(struct platform_device *pdev)
115{
116 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
117 int ret = 0;
118
119 if (!res)
120 return -ENOENT;
121 res = devm_request_mem_region(&pdev->dev, res->start,
122 resource_size(res), dev_name(&pdev->dev));
123 if (!res) {
124 dev_err(&pdev->dev, "failed to request STP memory\n");
125 return -EBUSY;
126 }
127 ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start,
128 resource_size(res));
129 if (!ltq_stp_membase) {
130 dev_err(&pdev->dev, "failed to remap STP memory\n");
131 return -ENOMEM;
132 }
133 ret = gpiochip_add(&ltq_stp_chip);
134 if (!ret)
135 ret = ltq_stp_hw_init();
136
137 return ret;
138}
139
140static struct platform_driver ltq_stp_driver = {
141 .probe = ltq_stp_probe,
142 .driver = {
143 .name = "ltq_stp",
144 .owner = THIS_MODULE,
145 },
146};
147
148int __init ltq_stp_init(void)
149{
150 int ret = platform_driver_register(&ltq_stp_driver);
151
152 if (ret)
153 pr_info("ltq_stp: error registering platfom driver");
154 return ret;
155}
156
157postcore_initcall(ltq_stp_init);
diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c
new file mode 100644
index 000000000000..d5aaf637ab19
--- /dev/null
+++ b/arch/mips/lantiq/xway/mach-easy50601.c
@@ -0,0 +1,57 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/input.h>
15
16#include <lantiq.h>
17
18#include "../machtypes.h"
19#include "devices.h"
20
21static struct mtd_partition easy50601_partitions[] = {
22 {
23 .name = "uboot",
24 .offset = 0x0,
25 .size = 0x10000,
26 },
27 {
28 .name = "uboot_env",
29 .offset = 0x10000,
30 .size = 0x10000,
31 },
32 {
33 .name = "linux",
34 .offset = 0x20000,
35 .size = 0xE0000,
36 },
37 {
38 .name = "rootfs",
39 .offset = 0x100000,
40 .size = 0x300000,
41 },
42};
43
44static struct physmap_flash_data easy50601_flash_data = {
45 .nr_parts = ARRAY_SIZE(easy50601_partitions),
46 .parts = easy50601_partitions,
47};
48
49static void __init easy50601_init(void)
50{
51 ltq_register_nor(&easy50601_flash_data);
52}
53
54MIPS_MACHINE(LTQ_MACH_EASY50601,
55 "EASY50601",
56 "EASY50601 Eval Board",
57 easy50601_init);
diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c
new file mode 100644
index 000000000000..ea5027b3239d
--- /dev/null
+++ b/arch/mips/lantiq/xway/mach-easy50712.c
@@ -0,0 +1,74 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/input.h>
15#include <linux/phy.h>
16
17#include <lantiq_soc.h>
18#include <irq.h>
19
20#include "../machtypes.h"
21#include "devices.h"
22
23static struct mtd_partition easy50712_partitions[] = {
24 {
25 .name = "uboot",
26 .offset = 0x0,
27 .size = 0x10000,
28 },
29 {
30 .name = "uboot_env",
31 .offset = 0x10000,
32 .size = 0x10000,
33 },
34 {
35 .name = "linux",
36 .offset = 0x20000,
37 .size = 0xe0000,
38 },
39 {
40 .name = "rootfs",
41 .offset = 0x100000,
42 .size = 0x300000,
43 },
44};
45
46static struct physmap_flash_data easy50712_flash_data = {
47 .nr_parts = ARRAY_SIZE(easy50712_partitions),
48 .parts = easy50712_partitions,
49};
50
51static struct ltq_pci_data ltq_pci_data = {
52 .clock = PCI_CLOCK_INT,
53 .gpio = PCI_GNT1 | PCI_REQ1,
54 .irq = {
55 [14] = INT_NUM_IM0_IRL0 + 22,
56 },
57};
58
59static struct ltq_eth_data ltq_eth_data = {
60 .mii_mode = PHY_INTERFACE_MODE_MII,
61};
62
63static void __init easy50712_init(void)
64{
65 ltq_register_gpio_stp();
66 ltq_register_nor(&easy50712_flash_data);
67 ltq_register_pci(&ltq_pci_data);
68 ltq_register_etop(&ltq_eth_data);
69}
70
71MIPS_MACHINE(LTQ_MACH_EASY50712,
72 "EASY50712",
73 "EASY50712 Eval Board",
74 easy50712_init);
diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
new file mode 100644
index 000000000000..9d69f01e352b
--- /dev/null
+++ b/arch/mips/lantiq/xway/pmu.c
@@ -0,0 +1,70 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/version.h>
12#include <linux/ioport.h>
13
14#include <lantiq_soc.h>
15
16/* PMU - the power management unit allows us to turn part of the core
17 * on and off
18 */
19
20/* the enable / disable registers */
21#define LTQ_PMU_PWDCR 0x1C
22#define LTQ_PMU_PWDSR 0x20
23
24#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
25#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
26
27static struct resource ltq_pmu_resource = {
28 .name = "pmu",
29 .start = LTQ_PMU_BASE_ADDR,
30 .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
31 .flags = IORESOURCE_MEM,
32};
33
34static void __iomem *ltq_pmu_membase;
35
36void ltq_pmu_enable(unsigned int module)
37{
38 int err = 1000000;
39
40 ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
41 do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
42
43 if (!err)
44 panic("activating PMU module failed!\n");
45}
46EXPORT_SYMBOL(ltq_pmu_enable);
47
48void ltq_pmu_disable(unsigned int module)
49{
50 ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
51}
52EXPORT_SYMBOL(ltq_pmu_disable);
53
54int __init ltq_pmu_init(void)
55{
56 if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
57 panic("Failed to insert pmu memory\n");
58
59 if (request_mem_region(ltq_pmu_resource.start,
60 resource_size(&ltq_pmu_resource), "pmu") < 0)
61 panic("Failed to request pmu memory\n");
62
63 ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
64 resource_size(&ltq_pmu_resource));
65 if (!ltq_pmu_membase)
66 panic("Failed to remap pmu memory\n");
67 return 0;
68}
69
70core_initcall(ltq_pmu_init);
diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
new file mode 100644
index 000000000000..abe49f4db57f
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom-ase.c
@@ -0,0 +1,39 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/module.h>
10#include <linux/clk.h>
11#include <asm/bootinfo.h>
12#include <asm/time.h>
13
14#include <lantiq_soc.h>
15
16#include "../prom.h"
17
18#define SOC_AMAZON_SE "Amazon_SE"
19
20#define PART_SHIFT 12
21#define PART_MASK 0x0FFFFFFF
22#define REV_SHIFT 28
23#define REV_MASK 0xF0000000
24
25void __init ltq_soc_detect(struct ltq_soc_info *i)
26{
27 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
28 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
29 switch (i->partnum) {
30 case SOC_ID_AMAZON_SE:
31 i->name = SOC_AMAZON_SE;
32 i->type = SOC_TYPE_AMAZON_SE;
33 break;
34
35 default:
36 unreachable();
37 break;
38 }
39}
diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
new file mode 100644
index 000000000000..1686692ac24d
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom-xway.c
@@ -0,0 +1,54 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/module.h>
10#include <linux/clk.h>
11#include <asm/bootinfo.h>
12#include <asm/time.h>
13
14#include <lantiq_soc.h>
15
16#include "../prom.h"
17
18#define SOC_DANUBE "Danube"
19#define SOC_TWINPASS "Twinpass"
20#define SOC_AR9 "AR9"
21
22#define PART_SHIFT 12
23#define PART_MASK 0x0FFFFFFF
24#define REV_SHIFT 28
25#define REV_MASK 0xF0000000
26
27void __init ltq_soc_detect(struct ltq_soc_info *i)
28{
29 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
30 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
31 switch (i->partnum) {
32 case SOC_ID_DANUBE1:
33 case SOC_ID_DANUBE2:
34 i->name = SOC_DANUBE;
35 i->type = SOC_TYPE_DANUBE;
36 break;
37
38 case SOC_ID_TWINPASS:
39 i->name = SOC_TWINPASS;
40 i->type = SOC_TYPE_DANUBE;
41 break;
42
43 case SOC_ID_ARX188:
44 case SOC_ID_ARX168:
45 case SOC_ID_ARX182:
46 i->name = SOC_AR9;
47 i->type = SOC_TYPE_AR9;
48 break;
49
50 default:
51 unreachable();
52 break;
53 }
54}
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
new file mode 100644
index 000000000000..a1be36d0e490
--- /dev/null
+++ b/arch/mips/lantiq/xway/reset.c
@@ -0,0 +1,91 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/ioport.h>
12#include <linux/pm.h>
13#include <linux/module.h>
14#include <asm/reboot.h>
15
16#include <lantiq_soc.h>
17
18#define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y))
19#define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x))
20
21/* register definitions */
22#define LTQ_RCU_RST 0x0010
23#define LTQ_RCU_RST_ALL 0x40000000
24
25#define LTQ_RCU_RST_STAT 0x0014
26#define LTQ_RCU_STAT_SHIFT 26
27
28static struct resource ltq_rcu_resource = {
29 .name = "rcu",
30 .start = LTQ_RCU_BASE_ADDR,
31 .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
32 .flags = IORESOURCE_MEM,
33};
34
35/* remapped base addr of the reset control unit */
36static void __iomem *ltq_rcu_membase;
37
38/* This function is used by the watchdog driver */
39int ltq_reset_cause(void)
40{
41 u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT);
42 return val >> LTQ_RCU_STAT_SHIFT;
43}
44EXPORT_SYMBOL_GPL(ltq_reset_cause);
45
46static void ltq_machine_restart(char *command)
47{
48 pr_notice("System restart\n");
49 local_irq_disable();
50 ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST);
51 unreachable();
52}
53
54static void ltq_machine_halt(void)
55{
56 pr_notice("System halted.\n");
57 local_irq_disable();
58 unreachable();
59}
60
61static void ltq_machine_power_off(void)
62{
63 pr_notice("Please turn off the power now.\n");
64 local_irq_disable();
65 unreachable();
66}
67
68static int __init mips_reboot_setup(void)
69{
70 /* insert and request the memory region */
71 if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
72 panic("Failed to insert rcu memory\n");
73
74 if (request_mem_region(ltq_rcu_resource.start,
75 resource_size(&ltq_rcu_resource), "rcu") < 0)
76 panic("Failed to request rcu memory\n");
77
78 /* remap rcu register range */
79 ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
80 resource_size(&ltq_rcu_resource));
81 if (!ltq_rcu_membase)
82 panic("Failed to remap rcu memory\n");
83
84 _machine_restart = ltq_machine_restart;
85 _machine_halt = ltq_machine_halt;
86 pm_power_off = ltq_machine_power_off;
87
88 return 0;
89}
90
91arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
new file mode 100644
index 000000000000..f6f326798a39
--- /dev/null
+++ b/arch/mips/lantiq/xway/setup-ase.c
@@ -0,0 +1,19 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
7 */
8
9#include <lantiq_soc.h>
10
11#include "../prom.h"
12#include "devices.h"
13
14void __init ltq_soc_setup(void)
15{
16 ltq_register_ase_asc();
17 ltq_register_gpio();
18 ltq_register_wdt();
19}
diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
new file mode 100644
index 000000000000..c292f643a858
--- /dev/null
+++ b/arch/mips/lantiq/xway/setup-xway.c
@@ -0,0 +1,20 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
7 */
8
9#include <lantiq_soc.h>
10
11#include "../prom.h"
12#include "devices.h"
13
14void __init ltq_soc_setup(void)
15{
16 ltq_register_asc(0);
17 ltq_register_asc(1);
18 ltq_register_gpio();
19 ltq_register_wdt();
20}
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 2adead5a8a37..b2cad4fd5fc4 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
28obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o 28obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o 29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o 30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
31obj-$(CONFIG_CPU_XLR) += dump_tlb.o
31 32
32# libgcc-style stuff needed in the kernel 33# libgcc-style stuff needed in the kernel
33obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o 34obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index 11b193f848f8..d93830ad6113 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -29,9 +29,10 @@ unsigned long memsize, highmemsize;
29 29
30#define parse_even_earlier(res, option, p) \ 30#define parse_even_earlier(res, option, p) \
31do { \ 31do { \
32 int ret; \ 32 unsigned int tmp __maybe_unused; \
33 \
33 if (strncmp(option, (char *)p, strlen(option)) == 0) \ 34 if (strncmp(option, (char *)p, strlen(option)) == 0) \
34 ret = strict_strtol((char *)p + strlen(option"="), 10, &res); \ 35 tmp = strict_strtol((char *)p + strlen(option"="), 10, &res); \
35} while (0) 36} while (0)
36 37
37void __init prom_init_env(void) 38void __init prom_init_env(void)
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index d679c772d082..4d8c1623eee2 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -3,7 +3,8 @@
3# 3#
4 4
5obj-y += cache.o dma-default.o extable.o fault.o \ 5obj-y += cache.o dma-default.o extable.o fault.o \
6 init.o tlbex.o tlbex-fault.o uasm.o page.o 6 init.o mmap.o tlbex.o tlbex-fault.o uasm.o \
7 page.o
7 8
8obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o 9obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
9obj-$(CONFIG_64BIT) += pgtable-64.o 10obj-$(CONFIG_64BIT) += pgtable-64.o
@@ -29,6 +30,7 @@ obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
29obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o 30obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
30obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o 31obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
31obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o 32obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
33obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o
32 34
33obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 35obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
34obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 36obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index b4923a75cb4b..d9bc5d3593b6 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1006,6 +1006,7 @@ static void __cpuinit probe_pcache(void)
1006 case CPU_25KF: 1006 case CPU_25KF:
1007 case CPU_SB1: 1007 case CPU_SB1:
1008 case CPU_SB1A: 1008 case CPU_SB1A:
1009 case CPU_XLR:
1009 c->dcache.flags |= MIPS_CACHE_PINDEX; 1010 c->dcache.flags |= MIPS_CACHE_PINDEX;
1010 break; 1011 break;
1011 1012
@@ -1075,7 +1076,6 @@ static int __cpuinit probe_scache(void)
1075 unsigned long flags, addr, begin, end, pow2; 1076 unsigned long flags, addr, begin, end, pow2;
1076 unsigned int config = read_c0_config(); 1077 unsigned int config = read_c0_config();
1077 struct cpuinfo_mips *c = &current_cpu_data; 1078 struct cpuinfo_mips *c = &current_cpu_data;
1078 int tmp;
1079 1079
1080 if (config & CONF_SC) 1080 if (config & CONF_SC)
1081 return 0; 1081 return 0;
@@ -1108,7 +1108,6 @@ static int __cpuinit probe_scache(void)
1108 1108
1109 /* Now search for the wrap around point. */ 1109 /* Now search for the wrap around point. */
1110 pow2 = (128 * 1024); 1110 pow2 = (128 * 1024);
1111 tmp = 0;
1112 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1111 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1113 cache_op(Index_Load_Tag_SD, addr); 1112 cache_op(Index_Load_Tag_SD, addr);
1114 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1113 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
diff --git a/arch/mips/mm/mmap.c b/arch/mips/mm/mmap.c
new file mode 100644
index 000000000000..ae3c20a9556e
--- /dev/null
+++ b/arch/mips/mm/mmap.c
@@ -0,0 +1,122 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#include <linux/errno.h>
10#include <linux/mm.h>
11#include <linux/mman.h>
12#include <linux/module.h>
13#include <linux/random.h>
14#include <linux/sched.h>
15
16unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
17
18EXPORT_SYMBOL(shm_align_mask);
19
20#define COLOUR_ALIGN(addr,pgoff) \
21 ((((addr) + shm_align_mask) & ~shm_align_mask) + \
22 (((pgoff) << PAGE_SHIFT) & shm_align_mask))
23
24unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
25 unsigned long len, unsigned long pgoff, unsigned long flags)
26{
27 struct vm_area_struct * vmm;
28 int do_color_align;
29
30 if (len > TASK_SIZE)
31 return -ENOMEM;
32
33 if (flags & MAP_FIXED) {
34 /* Even MAP_FIXED mappings must reside within TASK_SIZE. */
35 if (TASK_SIZE - len < addr)
36 return -EINVAL;
37
38 /*
39 * We do not accept a shared mapping if it would violate
40 * cache aliasing constraints.
41 */
42 if ((flags & MAP_SHARED) &&
43 ((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
44 return -EINVAL;
45 return addr;
46 }
47
48 do_color_align = 0;
49 if (filp || (flags & MAP_SHARED))
50 do_color_align = 1;
51 if (addr) {
52 if (do_color_align)
53 addr = COLOUR_ALIGN(addr, pgoff);
54 else
55 addr = PAGE_ALIGN(addr);
56 vmm = find_vma(current->mm, addr);
57 if (TASK_SIZE - len >= addr &&
58 (!vmm || addr + len <= vmm->vm_start))
59 return addr;
60 }
61 addr = current->mm->mmap_base;
62 if (do_color_align)
63 addr = COLOUR_ALIGN(addr, pgoff);
64 else
65 addr = PAGE_ALIGN(addr);
66
67 for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) {
68 /* At this point: (!vmm || addr < vmm->vm_end). */
69 if (TASK_SIZE - len < addr)
70 return -ENOMEM;
71 if (!vmm || addr + len <= vmm->vm_start)
72 return addr;
73 addr = vmm->vm_end;
74 if (do_color_align)
75 addr = COLOUR_ALIGN(addr, pgoff);
76 }
77}
78
79void arch_pick_mmap_layout(struct mm_struct *mm)
80{
81 unsigned long random_factor = 0UL;
82
83 if (current->flags & PF_RANDOMIZE) {
84 random_factor = get_random_int();
85 random_factor = random_factor << PAGE_SHIFT;
86 if (TASK_IS_32BIT_ADDR)
87 random_factor &= 0xfffffful;
88 else
89 random_factor &= 0xffffffful;
90 }
91
92 mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
93 mm->get_unmapped_area = arch_get_unmapped_area;
94 mm->unmap_area = arch_unmap_area;
95}
96
97static inline unsigned long brk_rnd(void)
98{
99 unsigned long rnd = get_random_int();
100
101 rnd = rnd << PAGE_SHIFT;
102 /* 8MB for 32bit, 256MB for 64bit */
103 if (TASK_IS_32BIT_ADDR)
104 rnd = rnd & 0x7ffffful;
105 else
106 rnd = rnd & 0xffffffful;
107
108 return rnd;
109}
110
111unsigned long arch_randomize_brk(struct mm_struct *mm)
112{
113 unsigned long base = mm->brk;
114 unsigned long ret;
115
116 ret = PAGE_ALIGN(base + brk_rnd());
117
118 if (ret < mm->brk)
119 return mm->brk;
120
121 return ret;
122}
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 5ef294fbb6e7..424ed4b92e6d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
404 case CPU_5KC: 404 case CPU_5KC:
405 case CPU_TX49XX: 405 case CPU_TX49XX:
406 case CPU_PR4450: 406 case CPU_PR4450:
407 case CPU_XLR:
407 uasm_i_nop(p); 408 uasm_i_nop(p);
408 tlbw(p); 409 tlbw(p);
409 break; 410 break;
@@ -1151,8 +1152,8 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
1151 struct uasm_reloc *r = relocs; 1152 struct uasm_reloc *r = relocs;
1152 u32 *f; 1153 u32 *f;
1153 unsigned int final_len; 1154 unsigned int final_len;
1154 struct mips_huge_tlb_info htlb_info; 1155 struct mips_huge_tlb_info htlb_info __maybe_unused;
1155 enum vmalloc64_mode vmalloc_mode; 1156 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1156 1157
1157 memset(tlb_handler, 0, sizeof(tlb_handler)); 1158 memset(tlb_handler, 0, sizeof(tlb_handler));
1158 memset(labels, 0, sizeof(labels)); 1159 memset(labels, 0, sizeof(labels));
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index 414f0c99b196..31180c321a1a 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -193,8 +193,6 @@ extern struct plat_smp_ops msmtc_smp_ops;
193 193
194void __init prom_init(void) 194void __init prom_init(void)
195{ 195{
196 int result;
197
198 prom_argc = fw_arg0; 196 prom_argc = fw_arg0;
199 _prom_argv = (int *) fw_arg1; 197 _prom_argv = (int *) fw_arg1;
200 _prom_envp = (int *) fw_arg2; 198 _prom_envp = (int *) fw_arg2;
@@ -360,20 +358,14 @@ void __init prom_init(void)
360#ifdef CONFIG_SERIAL_8250_CONSOLE 358#ifdef CONFIG_SERIAL_8250_CONSOLE
361 console_config(); 359 console_config();
362#endif 360#endif
363 /* Early detection of CMP support */
364 result = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
365
366#ifdef CONFIG_MIPS_CMP 361#ifdef CONFIG_MIPS_CMP
367 if (result) 362 /* Early detection of CMP support */
363 if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ))
368 register_smp_ops(&cmp_smp_ops); 364 register_smp_ops(&cmp_smp_ops);
365 else
369#endif 366#endif
370#ifdef CONFIG_MIPS_MT_SMP 367#ifdef CONFIG_MIPS_MT_SMP
371#ifdef CONFIG_MIPS_CMP
372 if (!result)
373 register_smp_ops(&vsmp_smp_ops); 368 register_smp_ops(&vsmp_smp_ops);
374#else
375 register_smp_ops(&vsmp_smp_ops);
376#endif
377#endif 369#endif
378#ifdef CONFIG_MIPS_MT_SMTC 370#ifdef CONFIG_MIPS_MT_SMTC
379 register_smp_ops(&msmtc_smp_ops); 371 register_smp_ops(&msmtc_smp_ops);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 9027061f0ead..1d36c511a7a5 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -56,7 +56,6 @@ static DEFINE_RAW_SPINLOCK(mips_irq_lock);
56static inline int mips_pcibios_iack(void) 56static inline int mips_pcibios_iack(void)
57{ 57{
58 int irq; 58 int irq;
59 u32 dummy;
60 59
61 /* 60 /*
62 * Determine highest priority pending interrupt by performing 61 * Determine highest priority pending interrupt by performing
@@ -83,7 +82,7 @@ static inline int mips_pcibios_iack(void)
83 BONITO_PCIMAP_CFG = 0x20000; 82 BONITO_PCIMAP_CFG = 0x20000;
84 83
85 /* Flush Bonito register block */ 84 /* Flush Bonito register block */
86 dummy = BONITO_PCIMAP_CFG; 85 (void) BONITO_PCIMAP_CFG;
87 iob(); /* sync */ 86 iob(); /* sync */
88 87
89 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); 88 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
@@ -309,6 +308,8 @@ static void ipi_call_dispatch(void)
309 308
310static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 309static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
311{ 310{
311 scheduler_ipi();
312
312 return IRQ_HANDLED; 313 return IRQ_HANDLED;
313} 314}
314 315
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
new file mode 100644
index 000000000000..a5ca743613f2
--- /dev/null
+++ b/arch/mips/netlogic/Kconfig
@@ -0,0 +1,5 @@
1config NLM_COMMON
2 bool
3
4config NLM_XLR
5 bool
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
new file mode 100644
index 000000000000..9bd3f731f62e
--- /dev/null
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -0,0 +1,5 @@
1obj-y += setup.o platform.o irq.o setup.o time.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o
3obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
4
5EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
new file mode 100644
index 000000000000..1446d58e364c
--- /dev/null
+++ b/arch/mips/netlogic/xlr/irq.c
@@ -0,0 +1,300 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41
42#include <asm/mipsregs.h>
43
44#include <asm/netlogic/xlr/iomap.h>
45#include <asm/netlogic/xlr/pic.h>
46#include <asm/netlogic/xlr/xlr.h>
47
48#include <asm/netlogic/interrupt.h>
49#include <asm/netlogic/mips-extns.h>
50
51static u64 nlm_irq_mask;
52static DEFINE_SPINLOCK(nlm_pic_lock);
53
54static void xlr_pic_enable(struct irq_data *d)
55{
56 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
57 unsigned long flags;
58 nlm_reg_t reg;
59 int irq = d->irq;
60
61 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
62
63 spin_lock_irqsave(&nlm_pic_lock, flags);
64 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
65 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
66 reg | (1 << 6) | (1 << 30) | (1 << 31));
67 spin_unlock_irqrestore(&nlm_pic_lock, flags);
68}
69
70static void xlr_pic_mask(struct irq_data *d)
71{
72 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
73 unsigned long flags;
74 nlm_reg_t reg;
75 int irq = d->irq;
76
77 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
78
79 spin_lock_irqsave(&nlm_pic_lock, flags);
80 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
81 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
82 reg | (1 << 6) | (1 << 30) | (0 << 31));
83 spin_unlock_irqrestore(&nlm_pic_lock, flags);
84}
85
86#ifdef CONFIG_PCI
87/* Extra ACK needed for XLR on chip PCI controller */
88static void xlr_pci_ack(struct irq_data *d)
89{
90 nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
91
92 netlogic_read_reg(pci_mmio, (0x140 >> 2));
93}
94
95/* Extra ACK needed for XLS on chip PCIe controller */
96static void xls_pcie_ack(struct irq_data *d)
97{
98 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
99
100 switch (d->irq) {
101 case PIC_PCIE_LINK0_IRQ:
102 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
103 break;
104 case PIC_PCIE_LINK1_IRQ:
105 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
106 break;
107 case PIC_PCIE_LINK2_IRQ:
108 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
109 break;
110 case PIC_PCIE_LINK3_IRQ:
111 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
112 break;
113 }
114}
115
116/* For XLS B silicon, the 3,4 PCI interrupts are different */
117static void xls_pcie_ack_b(struct irq_data *d)
118{
119 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
120
121 switch (d->irq) {
122 case PIC_PCIE_LINK0_IRQ:
123 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
124 break;
125 case PIC_PCIE_LINK1_IRQ:
126 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
127 break;
128 case PIC_PCIE_XLSB0_LINK2_IRQ:
129 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
130 break;
131 case PIC_PCIE_XLSB0_LINK3_IRQ:
132 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
133 break;
134 }
135}
136#endif
137
138static void xlr_pic_ack(struct irq_data *d)
139{
140 unsigned long flags;
141 nlm_reg_t *mmio;
142 int irq = d->irq;
143 void *hd = irq_data_get_irq_handler_data(d);
144
145 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
146
147 if (hd) {
148 void (*extra_ack)(void *) = hd;
149 extra_ack(d);
150 }
151 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
152 spin_lock_irqsave(&nlm_pic_lock, flags);
153 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
154 spin_unlock_irqrestore(&nlm_pic_lock, flags);
155}
156
157/*
158 * This chip definition handles interrupts routed thru the XLR
159 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
160 * 0-31 wired the XLR PIC
161 */
162static struct irq_chip xlr_pic = {
163 .name = "XLR-PIC",
164 .irq_enable = xlr_pic_enable,
165 .irq_mask = xlr_pic_mask,
166 .irq_ack = xlr_pic_ack,
167};
168
169static void rsvd_irq_handler(struct irq_data *d)
170{
171 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
172}
173
174/*
175 * Chip definition for CPU originated interrupts(timer, msg) and
176 * IPIs
177 */
178struct irq_chip nlm_cpu_intr = {
179 .name = "XLR-CPU-INTR",
180 .irq_enable = rsvd_irq_handler,
181 .irq_mask = rsvd_irq_handler,
182 .irq_ack = rsvd_irq_handler,
183};
184
185void __init init_xlr_irqs(void)
186{
187 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
188 uint32_t thread_mask = 1;
189 int level, i;
190
191 pr_info("Interrupt thread mask [%x]\n", thread_mask);
192 for (i = 0; i < PIC_NUM_IRTS; i++) {
193 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
194
195 /* Bind all PIC irqs to boot cpu */
196 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
197
198 /*
199 * Use local scheduling and high polarity for all IRTs
200 * Invalidate all IRTs, by default
201 */
202 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
203 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
204 }
205
206 /* Make all IRQs as level triggered by default */
207 for (i = 0; i < NR_IRQS; i++) {
208 if (PIC_IRQ_IS_IRT(i))
209 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
210 else
211 irq_set_chip_and_handler(i, &nlm_cpu_intr,
212 handle_level_irq);
213 }
214#ifdef CONFIG_SMP
215 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
216 nlm_smp_function_ipi_handler);
217 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
218 nlm_smp_resched_ipi_handler);
219 nlm_irq_mask |=
220 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
221#endif
222
223#ifdef CONFIG_PCI
224 /*
225 * For PCI interrupts, we need to ack the PIC controller too, overload
226 * irq handler data to do this
227 */
228 if (nlm_chip_is_xls()) {
229 if (nlm_chip_is_xls_b()) {
230 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
231 xls_pcie_ack_b);
232 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
233 xls_pcie_ack_b);
234 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
235 xls_pcie_ack_b);
236 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
237 xls_pcie_ack_b);
238 } else {
239 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
240 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
241 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
242 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
243 }
244 } else {
245 /* XLR PCI controller ACK */
246 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
247 }
248#endif
249 /* unmask all PIC related interrupts. If no handler is installed by the
250 * drivers, it'll just ack the interrupt and return
251 */
252 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
253 nlm_irq_mask |= (1ULL << i);
254
255 nlm_irq_mask |= (1ULL << IRQ_TIMER);
256}
257
258void __init arch_init_irq(void)
259{
260 /* Initialize the irq descriptors */
261 init_xlr_irqs();
262 write_c0_eimr(nlm_irq_mask);
263}
264
265void __cpuinit nlm_smp_irq_init(void)
266{
267 /* set interrupt mask for non-zero cpus */
268 write_c0_eimr(nlm_irq_mask);
269}
270
271asmlinkage void plat_irq_dispatch(void)
272{
273 uint64_t eirr;
274 int i;
275
276 eirr = read_c0_eirr() & read_c0_eimr();
277 if (!eirr)
278 return;
279
280 /* no need of EIRR here, writing compare clears interrupt */
281 if (eirr & (1 << IRQ_TIMER)) {
282 do_IRQ(IRQ_TIMER);
283 return;
284 }
285
286 /* use dcltz: optimize below code */
287 for (i = 63; i != -1; i--) {
288 if (eirr & (1ULL << i))
289 break;
290 }
291 if (i == -1) {
292 pr_err("no interrupt !!\n");
293 return;
294 }
295
296 /* Ack eirr */
297 write_c0_eirr(1ULL << i);
298
299 do_IRQ(i);
300}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
new file mode 100644
index 000000000000..609ec2534642
--- /dev/null
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright 2011, Netlogic Microsystems.
3 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/resource.h>
15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h>
17
18#include <asm/netlogic/xlr/iomap.h>
19#include <asm/netlogic/xlr/pic.h>
20#include <asm/netlogic/xlr/xlr.h>
21
22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
23{
24 nlm_reg_t *mmio;
25 unsigned int value;
26
27 /* XLR uart does not need any mapping of regs */
28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
29 value = netlogic_read_reg(mmio, 0);
30
31 /* See XLR/XLS errata */
32 if (offset == UART_MSR)
33 value ^= 0xF0;
34 else if (offset == UART_MCR)
35 value ^= 0x3;
36
37 return value;
38}
39
40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
41{
42 nlm_reg_t *mmio;
43
44 /* XLR uart does not need any mapping of regs */
45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
46
47 /* See XLR/XLS errata */
48 if (offset == UART_MSR)
49 value ^= 0xF0;
50 else if (offset == UART_MCR)
51 value ^= 0x3;
52
53 netlogic_write_reg(mmio, 0, value);
54}
55
56#define PORT(_irq) \
57 { \
58 .irq = _irq, \
59 .regshift = 2, \
60 .iotype = UPIO_MEM32, \
61 .flags = (UPF_SKIP_TEST | \
62 UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\
63 .uartclk = PIC_CLKS_PER_SEC, \
64 .type = PORT_16550A, \
65 .serial_in = nlm_xlr_uart_in, \
66 .serial_out = nlm_xlr_uart_out, \
67 }
68
69static struct plat_serial8250_port xlr_uart_data[] = {
70 PORT(PIC_UART_0_IRQ),
71 PORT(PIC_UART_1_IRQ),
72 {},
73};
74
75static struct platform_device uart_device = {
76 .name = "serial8250",
77 .id = PLAT8250_DEV_PLATFORM,
78 .dev = {
79 .platform_data = xlr_uart_data,
80 },
81};
82
83static int __init nlm_uart_init(void)
84{
85 nlm_reg_t *mmio;
86
87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
88 xlr_uart_data[0].membase = (void __iomem *)mmio;
89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio);
90
91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET);
92 xlr_uart_data[1].membase = (void __iomem *)mmio;
93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio);
94
95 return platform_device_register(&uart_device);
96}
97
98arch_initcall(nlm_uart_init);
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
new file mode 100644
index 000000000000..482802569e74
--- /dev/null
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -0,0 +1,188 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/serial_8250.h>
37#include <linux/pm.h>
38
39#include <asm/reboot.h>
40#include <asm/time.h>
41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
43
44#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/psb-bootinfo.h>
46
47#include <asm/netlogic/xlr/xlr.h>
48#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h>
50#include <asm/netlogic/xlr/gpio.h>
51
52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE);
53unsigned long nlm_common_ebase = 0x0;
54struct psb_info nlm_prom_info;
55
56static void nlm_early_serial_setup(void)
57{
58 struct uart_port s;
59 nlm_reg_t *uart_base;
60
61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
62 memset(&s, 0, sizeof(s));
63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
64 s.iotype = UPIO_MEM32;
65 s.regshift = 2;
66 s.irq = PIC_UART_0_IRQ;
67 s.uartclk = PIC_CLKS_PER_SEC;
68 s.serial_in = nlm_xlr_uart_in;
69 s.serial_out = nlm_xlr_uart_out;
70 s.mapbase = (unsigned long)uart_base;
71 s.membase = (unsigned char __iomem *)uart_base;
72 early_serial_setup(&s);
73}
74
75static void nlm_linux_exit(void)
76{
77 nlm_reg_t *mmio;
78
79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET);
80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1);
82 for ( ; ; )
83 cpu_wait();
84}
85
86void __init plat_mem_setup(void)
87{
88 panic_timeout = 5;
89 _machine_restart = (void (*)(char *))nlm_linux_exit;
90 _machine_halt = nlm_linux_exit;
91 pm_power_off = nlm_linux_exit;
92}
93
94const char *get_system_type(void)
95{
96 return "Netlogic XLR/XLS Series";
97}
98
99void __init prom_free_prom_memory(void)
100{
101 /* Nothing yet */
102}
103
104static void build_arcs_cmdline(int *argv)
105{
106 int i, remain, len;
107 char *arg;
108
109 remain = sizeof(arcs_cmdline) - 1;
110 arcs_cmdline[0] = '\0';
111 for (i = 0; argv[i] != 0; i++) {
112 arg = (char *)(long)argv[i];
113 len = strlen(arg);
114 if (len + 1 > remain)
115 break;
116 strcat(arcs_cmdline, arg);
117 strcat(arcs_cmdline, " ");
118 remain -= len + 1;
119 }
120
121 /* Add the default options here */
122 if ((strstr(arcs_cmdline, "console=")) == NULL) {
123 arg = "console=ttyS0,38400 ";
124 len = strlen(arg);
125 if (len > remain)
126 goto fail;
127 strcat(arcs_cmdline, arg);
128 remain -= len;
129 }
130#ifdef CONFIG_BLK_DEV_INITRD
131 if ((strstr(arcs_cmdline, "rdinit=")) == NULL) {
132 arg = "rdinit=/sbin/init ";
133 len = strlen(arg);
134 if (len > remain)
135 goto fail;
136 strcat(arcs_cmdline, arg);
137 remain -= len;
138 }
139#endif
140 return;
141fail:
142 panic("Cannot add %s, command line too big!", arg);
143}
144
145static void prom_add_memory(void)
146{
147 struct nlm_boot_mem_map *bootm;
148 u64 start, size;
149 u64 pref_backup = 512; /* avoid pref walking beyond end */
150 int i;
151
152 bootm = (void *)(long)nlm_prom_info.psb_mem_map;
153 for (i = 0; i < bootm->nr_map; i++) {
154 if (bootm->map[i].type != BOOT_MEM_RAM)
155 continue;
156 start = bootm->map[i].addr;
157 size = bootm->map[i].size;
158
159 /* Work around for using bootloader mem */
160 if (i == 0 && start == 0 && size == 0x0c000000)
161 size = 0x0ff00000;
162
163 add_memory_region(start, size - pref_backup, BOOT_MEM_RAM);
164 }
165}
166
167void __init prom_init(void)
168{
169 int *argv, *envp; /* passed as 32 bit ptrs */
170 struct psb_info *prom_infop;
171
172 /* truncate to 32 bit and sign extend all args */
173 argv = (int *)(long)(int)fw_arg1;
174 envp = (int *)(long)(int)fw_arg2;
175 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
176
177 nlm_prom_info = *prom_infop;
178
179 nlm_early_serial_setup();
180 build_arcs_cmdline(argv);
181 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
182 prom_add_memory();
183
184#ifdef CONFIG_SMP
185 nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map);
186 register_smp_ops(&nlm_smp_ops);
187#endif
188}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c
new file mode 100644
index 000000000000..b495a7f1433b
--- /dev/null
+++ b/arch/mips/netlogic/xlr/smp.c
@@ -0,0 +1,225 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/smp.h>
39#include <linux/irq.h>
40
41#include <asm/mmu_context.h>
42
43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h>
45
46#include <asm/netlogic/xlr/iomap.h>
47#include <asm/netlogic/xlr/pic.h>
48#include <asm/netlogic/xlr/xlr.h>
49
50void core_send_ipi(int logical_cpu, unsigned int action)
51{
52 int cpu = cpu_logical_map(logical_cpu);
53 u32 tid = cpu & 0x3;
54 u32 pid = (cpu >> 2) & 0x07;
55 u32 ipi = (tid << 16) | (pid << 20);
56
57 if (action & SMP_CALL_FUNCTION)
58 ipi |= IRQ_IPI_SMP_FUNCTION;
59 else if (action & SMP_RESCHEDULE_YOURSELF)
60 ipi |= IRQ_IPI_SMP_RESCHEDULE;
61 else
62 return;
63
64 pic_send_ipi(ipi);
65}
66
67void nlm_send_ipi_single(int cpu, unsigned int action)
68{
69 core_send_ipi(cpu, action);
70}
71
72void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
73{
74 int cpu;
75
76 for_each_cpu(cpu, mask) {
77 core_send_ipi(cpu, action);
78 }
79}
80
81/* IRQ_IPI_SMP_FUNCTION Handler */
82void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
83{
84 smp_call_function_interrupt();
85}
86
87/* IRQ_IPI_SMP_RESCHEDULE handler */
88void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
89{
90 set_need_resched();
91}
92
93void nlm_common_ipi_handler(int irq, struct pt_regs *regs)
94{
95 if (irq == IRQ_IPI_SMP_FUNCTION) {
96 smp_call_function_interrupt();
97 } else {
98 /* Announce that we are for reschduling */
99 set_need_resched();
100 }
101}
102
103/*
104 * Called before going into mips code, early cpu init
105 */
106void nlm_early_init_secondary(void)
107{
108 write_c0_ebase((uint32_t)nlm_common_ebase);
109 /* TLB partition here later */
110}
111
112/*
113 * Code to run on secondary just after probing the CPU
114 */
115static void __cpuinit nlm_init_secondary(void)
116{
117 nlm_smp_irq_init();
118}
119
120void nlm_smp_finish(void)
121{
122#ifdef notyet
123 nlm_common_msgring_cpu_init();
124#endif
125}
126
127void nlm_cpus_done(void)
128{
129}
130
131/*
132 * Boot all other cpus in the system, initialize them, and bring them into
133 * the boot function
134 */
135int nlm_cpu_unblock[NR_CPUS];
136int nlm_cpu_ready[NR_CPUS];
137unsigned long nlm_next_gp;
138unsigned long nlm_next_sp;
139cpumask_t phys_cpu_present_map;
140
141void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
142{
143 unsigned long gp = (unsigned long)task_thread_info(idle);
144 unsigned long sp = (unsigned long)__KSTK_TOS(idle);
145 int cpu = cpu_logical_map(logical_cpu);
146
147 nlm_next_sp = sp;
148 nlm_next_gp = gp;
149
150 /* barrier */
151 __sync();
152 nlm_cpu_unblock[cpu] = 1;
153}
154
155void __init nlm_smp_setup(void)
156{
157 unsigned int boot_cpu;
158 int num_cpus, i;
159
160 boot_cpu = hard_smp_processor_id();
161 cpus_clear(phys_cpu_present_map);
162
163 cpu_set(boot_cpu, phys_cpu_present_map);
164 __cpu_number_map[boot_cpu] = 0;
165 __cpu_logical_map[0] = boot_cpu;
166 cpu_set(0, cpu_possible_map);
167
168 num_cpus = 1;
169 for (i = 0; i < NR_CPUS; i++) {
170 if (nlm_cpu_ready[i]) {
171 cpu_set(i, phys_cpu_present_map);
172 __cpu_number_map[i] = num_cpus;
173 __cpu_logical_map[num_cpus] = i;
174 cpu_set(num_cpus, cpu_possible_map);
175 ++num_cpus;
176 }
177 }
178
179 pr_info("Phys CPU present map: %lx, possible map %lx\n",
180 (unsigned long)phys_cpu_present_map.bits[0],
181 (unsigned long)cpu_possible_map.bits[0]);
182
183 pr_info("Detected %i Slave CPU(s)\n", num_cpus);
184}
185
186void nlm_prepare_cpus(unsigned int max_cpus)
187{
188}
189
190struct plat_smp_ops nlm_smp_ops = {
191 .send_ipi_single = nlm_send_ipi_single,
192 .send_ipi_mask = nlm_send_ipi_mask,
193 .init_secondary = nlm_init_secondary,
194 .smp_finish = nlm_smp_finish,
195 .cpus_done = nlm_cpus_done,
196 .boot_secondary = nlm_boot_secondary,
197 .smp_setup = nlm_smp_setup,
198 .prepare_cpus = nlm_prepare_cpus,
199};
200
201unsigned long secondary_entry_point;
202
203int nlm_wakeup_secondary_cpus(u32 wakeup_mask)
204{
205 unsigned int tid, pid, ipi, i, boot_cpu;
206 void *reset_vec;
207
208 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
209 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
210 memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
211 boot_cpu = hard_smp_processor_id();
212
213 for (i = 0; i < NR_CPUS; i++) {
214 if (i == boot_cpu)
215 continue;
216 if (wakeup_mask & (1u << i)) {
217 tid = i & 0x3;
218 pid = (i >> 2) & 0x7;
219 ipi = (tid << 16) | (pid << 20) | (1 << 8);
220 pic_send_ipi(ipi);
221 }
222 }
223
224 return 0;
225}
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S
new file mode 100644
index 000000000000..b8e074402c99
--- /dev/null
+++ b/arch/mips/netlogic/xlr/smpboot.S
@@ -0,0 +1,94 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <asm/asm.h>
36#include <asm/asm-offsets.h>
37#include <asm/regdef.h>
38#include <asm/mipsregs.h>
39
40
41/* Don't jump to linux function from Bootloader stack. Change it
42 * here. Kernel might allocate bootloader memory before all the CPUs are
43 * brought up (eg: Inode cache region) and we better don't overwrite this
44 * memory
45 */
46NESTED(prom_pre_boot_secondary_cpus, 16, sp)
47 .set mips64
48 mfc0 t0, $15, 1 # read ebase
49 andi t0, 0x1f # t0 has the processor_id()
50 sll t0, 2 # offset in cpu array
51
52 PTR_LA t1, nlm_cpu_ready # mark CPU ready
53 PTR_ADDU t1, t0
54 li t2, 1
55 sw t2, 0(t1)
56
57 PTR_LA t1, nlm_cpu_unblock
58 PTR_ADDU t1, t0
591: lw t2, 0(t1) # wait till unblocked
60 beqz t2, 1b
61 nop
62
63 PTR_LA t1, nlm_next_sp
64 PTR_L sp, 0(t1)
65 PTR_LA t1, nlm_next_gp
66 PTR_L gp, 0(t1)
67
68 PTR_LA t0, nlm_early_init_secondary
69 jalr t0
70 nop
71
72 PTR_LA t0, smp_bootstrap
73 jr t0
74 nop
75END(prom_pre_boot_secondary_cpus)
76
77NESTED(nlm_boot_smp_nmi, 0, sp)
78 .set push
79 .set noat
80 .set mips64
81 .set noreorder
82
83 /* Clear the NMI and BEV bits */
84 MFC0 k0, CP0_STATUS
85 li k1, 0xffb7ffff
86 and k0, k0, k1
87 MTC0 k0, CP0_STATUS
88
89 PTR_LA k1, secondary_entry_point
90 PTR_L k0, 0(k1)
91 jr k0
92 nop
93 .set pop
94END(nlm_boot_smp_nmi)
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c
new file mode 100644
index 000000000000..0d81b262593c
--- /dev/null
+++ b/arch/mips/netlogic/xlr/time.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/time.h>
38#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/psb-bootinfo.h>
40
41unsigned int __cpuinit get_c0_compare_int(void)
42{
43 return IRQ_TIMER;
44}
45
46void __init plat_time_init(void)
47{
48 mips_hpt_frequency = nlm_prom_info.cpu_frequency;
49 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency);
51}
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c
new file mode 100644
index 000000000000..759df0692201
--- /dev/null
+++ b/arch/mips/netlogic/xlr/xlr_console.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <asm/netlogic/xlr/iomap.h>
37
38void prom_putchar(char c)
39{
40 nlm_reg_t *mmio;
41
42 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
43 while (netlogic_read_reg(mmio, 0x5) == 0)
44 ;
45 netlogic_write_reg(mmio, 0x0, c);
46}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c9209ca6c8e7..4df879937446 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
41obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o 41obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
42obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o 42obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
43obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o 43obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
44obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o
44obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 45obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
45obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 46obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
46obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 47obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
@@ -55,6 +56,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
55obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 56obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
56obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 57obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
57obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o 58obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
59obj-$(CONFIG_NLM_XLR) += pci-xlr.o
58 60
59ifdef CONFIG_PCI_MSI 61ifdef CONFIG_PCI_MSI
60obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o 62obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
new file mode 100644
index 000000000000..1f2afb55cc71
--- /dev/null
+++ b/arch/mips/pci/ops-lantiq.c
@@ -0,0 +1,116 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <asm/addrspace.h>
16#include <linux/vmalloc.h>
17
18#include <lantiq_soc.h>
19
20#include "pci-lantiq.h"
21
22#define LTQ_PCI_CFG_BUSNUM_SHF 16
23#define LTQ_PCI_CFG_DEVNUM_SHF 11
24#define LTQ_PCI_CFG_FUNNUM_SHF 8
25
26#define PCI_ACCESS_READ 0
27#define PCI_ACCESS_WRITE 1
28
29static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
30 unsigned int devfn, unsigned int where, u32 *data)
31{
32 unsigned long cfg_base;
33 unsigned long flags;
34 u32 temp;
35
36 /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
37 SoC itself */
38 if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
39 || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
40 return 1;
41
42 spin_lock_irqsave(&ebu_lock, flags);
43
44 cfg_base = (unsigned long) ltq_pci_mapped_cfg;
45 cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
46 LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
47
48 /* Perform access */
49 if (access_type == PCI_ACCESS_WRITE) {
50 ltq_w32(swab32(*data), ((u32 *)cfg_base));
51 } else {
52 *data = ltq_r32(((u32 *)(cfg_base)));
53 *data = swab32(*data);
54 }
55 wmb();
56
57 /* clean possible Master abort */
58 cfg_base = (unsigned long) ltq_pci_mapped_cfg;
59 cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
60 temp = ltq_r32(((u32 *)(cfg_base)));
61 temp = swab32(temp);
62 cfg_base = (unsigned long) ltq_pci_mapped_cfg;
63 cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
64 ltq_w32(temp, ((u32 *)cfg_base));
65
66 spin_unlock_irqrestore(&ebu_lock, flags);
67
68 if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
69 return 1;
70
71 return 0;
72}
73
74int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
75 int where, int size, u32 *val)
76{
77 u32 data = 0;
78
79 if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
80 return PCIBIOS_DEVICE_NOT_FOUND;
81
82 if (size == 1)
83 *val = (data >> ((where & 3) << 3)) & 0xff;
84 else if (size == 2)
85 *val = (data >> ((where & 3) << 3)) & 0xffff;
86 else
87 *val = data;
88
89 return PCIBIOS_SUCCESSFUL;
90}
91
92int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
93 int where, int size, u32 val)
94{
95 u32 data = 0;
96
97 if (size == 4) {
98 data = val;
99 } else {
100 if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
101 devfn, where, &data))
102 return PCIBIOS_DEVICE_NOT_FOUND;
103
104 if (size == 1)
105 data = (data & ~(0xff << ((where & 3) << 3))) |
106 (val << ((where & 3) << 3));
107 else if (size == 2)
108 data = (data & ~(0xffff << ((where & 3) << 3))) |
109 (val << ((where & 3) << 3));
110 }
111
112 if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
113 return PCIBIOS_DEVICE_NOT_FOUND;
114
115 return PCIBIOS_SUCCESSFUL;
116}
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
new file mode 100644
index 000000000000..603d7493e966
--- /dev/null
+++ b/arch/mips/pci/pci-lantiq.c
@@ -0,0 +1,297 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <linux/vmalloc.h>
16#include <linux/platform_device.h>
17
18#include <asm/pci.h>
19#include <asm/gpio.h>
20#include <asm/addrspace.h>
21
22#include <lantiq_soc.h>
23#include <lantiq_irq.h>
24#include <lantiq_platform.h>
25
26#include "pci-lantiq.h"
27
28#define LTQ_PCI_CFG_BASE 0x17000000
29#define LTQ_PCI_CFG_SIZE 0x00008000
30#define LTQ_PCI_MEM_BASE 0x18000000
31#define LTQ_PCI_MEM_SIZE 0x02000000
32#define LTQ_PCI_IO_BASE 0x1AE00000
33#define LTQ_PCI_IO_SIZE 0x00200000
34
35#define PCI_CR_FCI_ADDR_MAP0 0x00C0
36#define PCI_CR_FCI_ADDR_MAP1 0x00C4
37#define PCI_CR_FCI_ADDR_MAP2 0x00C8
38#define PCI_CR_FCI_ADDR_MAP3 0x00CC
39#define PCI_CR_FCI_ADDR_MAP4 0x00D0
40#define PCI_CR_FCI_ADDR_MAP5 0x00D4
41#define PCI_CR_FCI_ADDR_MAP6 0x00D8
42#define PCI_CR_FCI_ADDR_MAP7 0x00DC
43#define PCI_CR_CLK_CTRL 0x0000
44#define PCI_CR_PCI_MOD 0x0030
45#define PCI_CR_PC_ARB 0x0080
46#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
47#define PCI_CR_BAR11MASK 0x0044
48#define PCI_CR_BAR12MASK 0x0048
49#define PCI_CR_BAR13MASK 0x004C
50#define PCI_CS_BASE_ADDR1 0x0010
51#define PCI_CR_PCI_ADDR_MAP11 0x0064
52#define PCI_CR_FCI_BURST_LENGTH 0x00E8
53#define PCI_CR_PCI_EOI 0x002C
54#define PCI_CS_STS_CMD 0x0004
55
56#define PCI_MASTER0_REQ_MASK_2BITS 8
57#define PCI_MASTER1_REQ_MASK_2BITS 10
58#define PCI_MASTER2_REQ_MASK_2BITS 12
59#define INTERNAL_ARB_ENABLE_BIT 0
60
61#define LTQ_CGU_IFCCR 0x0018
62#define LTQ_CGU_PCICR 0x0034
63
64#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
65#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
66
67#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
68#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
69
70struct ltq_pci_gpio_map {
71 int pin;
72 int alt0;
73 int alt1;
74 int dir;
75 char *name;
76};
77
78/* the pci core can make use of the following gpios */
79static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
80 { 0, 1, 0, 0, "pci-exin0" },
81 { 1, 1, 0, 0, "pci-exin1" },
82 { 2, 1, 0, 0, "pci-exin2" },
83 { 39, 1, 0, 0, "pci-exin3" },
84 { 10, 1, 0, 0, "pci-exin4" },
85 { 9, 1, 0, 0, "pci-exin5" },
86 { 30, 1, 0, 1, "pci-gnt1" },
87 { 23, 1, 0, 1, "pci-gnt2" },
88 { 19, 1, 0, 1, "pci-gnt3" },
89 { 38, 1, 0, 1, "pci-gnt4" },
90 { 29, 1, 0, 0, "pci-req1" },
91 { 31, 1, 0, 0, "pci-req2" },
92 { 3, 1, 0, 0, "pci-req3" },
93 { 37, 1, 0, 0, "pci-req4" },
94};
95
96__iomem void *ltq_pci_mapped_cfg;
97static __iomem void *ltq_pci_membase;
98
99int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
100
101/* Since the PCI REQ pins can be reused for other functionality, make it
102 possible to exclude those from interpretation by the PCI controller */
103static int ltq_pci_req_mask = 0xf;
104
105static int *ltq_pci_irq_map;
106
107struct pci_ops ltq_pci_ops = {
108 .read = ltq_pci_read_config_dword,
109 .write = ltq_pci_write_config_dword
110};
111
112static struct resource pci_io_resource = {
113 .name = "pci io space",
114 .start = LTQ_PCI_IO_BASE,
115 .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1,
116 .flags = IORESOURCE_IO
117};
118
119static struct resource pci_mem_resource = {
120 .name = "pci memory space",
121 .start = LTQ_PCI_MEM_BASE,
122 .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1,
123 .flags = IORESOURCE_MEM
124};
125
126static struct pci_controller ltq_pci_controller = {
127 .pci_ops = &ltq_pci_ops,
128 .mem_resource = &pci_mem_resource,
129 .mem_offset = 0x00000000UL,
130 .io_resource = &pci_io_resource,
131 .io_offset = 0x00000000UL,
132};
133
134int pcibios_plat_dev_init(struct pci_dev *dev)
135{
136 if (ltqpci_plat_dev_init)
137 return ltqpci_plat_dev_init(dev);
138
139 return 0;
140}
141
142static u32 ltq_calc_bar11mask(void)
143{
144 u32 mem, bar11mask;
145
146 /* BAR11MASK value depends on available memory on system. */
147 mem = num_physpages * PAGE_SIZE;
148 bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
149
150 return bar11mask;
151}
152
153static void ltq_pci_setup_gpio(int gpio)
154{
155 int i;
156 for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
157 if (gpio & (1 << i)) {
158 ltq_gpio_request(ltq_pci_gpio_map[i].pin,
159 ltq_pci_gpio_map[i].alt0,
160 ltq_pci_gpio_map[i].alt1,
161 ltq_pci_gpio_map[i].dir,
162 ltq_pci_gpio_map[i].name);
163 }
164 }
165 ltq_gpio_request(21, 0, 0, 1, "pci-reset");
166 ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
167}
168
169static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
170{
171 u32 temp_buffer;
172
173 /* set clock to 33Mhz */
174 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
175 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
176
177 /* external or internal clock ? */
178 if (conf->clock) {
179 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16),
180 LTQ_CGU_IFCCR);
181 ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR);
182 } else {
183 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16),
184 LTQ_CGU_IFCCR);
185 ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR);
186 }
187
188 /* setup pci clock and gpis used by pci */
189 ltq_pci_setup_gpio(conf->gpio);
190
191 /* enable auto-switching between PCI and EBU */
192 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
193
194 /* busy, i.e. configuration is not done, PCI access has to be retried */
195 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
196 wmb();
197 /* BUS Master/IO/MEM access */
198 ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
199
200 /* enable external 2 PCI masters */
201 temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
202 temp_buffer &= (~(ltq_pci_req_mask << 16));
203 /* enable internal arbiter */
204 temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
205 /* enable internal PCI master reqest */
206 temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
207
208 /* enable EBU request */
209 temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
210
211 /* enable all external masters request */
212 temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
213 ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
214 wmb();
215
216 /* setup BAR memory regions */
217 ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
218 ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
219 ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
220 ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
221 ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
222 ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
223 ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
224 ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
225 ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
226 ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
227 ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
228 ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
229 /* both TX and RX endian swap are enabled */
230 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
231 wmb();
232 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
233 PCI_CR_BAR12MASK);
234 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
235 PCI_CR_BAR13MASK);
236 /*use 8 dw burst length */
237 ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
238 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
239 wmb();
240
241 /* setup irq line */
242 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
243 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
244
245 /* toggle reset pin */
246 __gpio_set_value(21, 0);
247 wmb();
248 mdelay(1);
249 __gpio_set_value(21, 1);
250 return 0;
251}
252
253int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
254{
255 if (ltq_pci_irq_map[slot])
256 return ltq_pci_irq_map[slot];
257 printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
258 slot);
259
260 return 0;
261}
262
263static int __devinit ltq_pci_probe(struct platform_device *pdev)
264{
265 struct ltq_pci_data *ltq_pci_data =
266 (struct ltq_pci_data *) pdev->dev.platform_data;
267 pci_probe_only = 0;
268 ltq_pci_irq_map = ltq_pci_data->irq;
269 ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
270 ltq_pci_mapped_cfg =
271 ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
272 ltq_pci_controller.io_map_base =
273 (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
274 ltq_pci_startup(ltq_pci_data);
275 register_pci_controller(&ltq_pci_controller);
276
277 return 0;
278}
279
280static struct platform_driver
281ltq_pci_driver = {
282 .probe = ltq_pci_probe,
283 .driver = {
284 .name = "ltq_pci",
285 .owner = THIS_MODULE,
286 },
287};
288
289int __init pcibios_init(void)
290{
291 int ret = platform_driver_register(&ltq_pci_driver);
292 if (ret)
293 printk(KERN_INFO "ltq_pci: Error registering platfom driver!");
294 return ret;
295}
296
297arch_initcall(pcibios_init);
diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h
new file mode 100644
index 000000000000..66bf6cd6be3c
--- /dev/null
+++ b/arch/mips/pci/pci-lantiq.h
@@ -0,0 +1,18 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_PCI_H__
10#define _LTQ_PCI_H__
11
12extern __iomem void *ltq_pci_mapped_cfg;
13extern int ltq_pci_read_config_dword(struct pci_bus *bus,
14 unsigned int devfn, int where, int size, u32 *val);
15extern int ltq_pci_write_config_dword(struct pci_bus *bus,
16 unsigned int devfn, int where, int size, u32 val);
17
18#endif
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
new file mode 100644
index 000000000000..38fece16c435
--- /dev/null
+++ b/arch/mips/pci/pci-xlr.c
@@ -0,0 +1,214 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/mm.h>
40#include <linux/console.h>
41
42#include <asm/io.h>
43
44#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/xlr/iomap.h>
46#include <asm/netlogic/xlr/pic.h>
47#include <asm/netlogic/xlr/xlr.h>
48
49static void *pci_config_base;
50
51#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
52
53/* PCI ops */
54static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
55 int where)
56{
57 u32 data;
58 u32 *cfgaddr;
59
60 cfgaddr = (u32 *)(pci_config_base +
61 pci_cfg_addr(bus->number, devfn, where & ~3));
62 data = *cfgaddr;
63 return cpu_to_le32(data);
64}
65
66static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
67 int where, u32 data)
68{
69 u32 *cfgaddr;
70
71 cfgaddr = (u32 *)(pci_config_base +
72 pci_cfg_addr(bus->number, devfn, where & ~3));
73 *cfgaddr = cpu_to_le32(data);
74}
75
76static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
77 int where, int size, u32 *val)
78{
79 u32 data;
80
81 if ((size == 2) && (where & 1))
82 return PCIBIOS_BAD_REGISTER_NUMBER;
83 else if ((size == 4) && (where & 3))
84 return PCIBIOS_BAD_REGISTER_NUMBER;
85
86 data = pci_cfg_read_32bit(bus, devfn, where);
87
88 if (size == 1)
89 *val = (data >> ((where & 3) << 3)) & 0xff;
90 else if (size == 2)
91 *val = (data >> ((where & 3) << 3)) & 0xffff;
92 else
93 *val = data;
94
95 return PCIBIOS_SUCCESSFUL;
96}
97
98
99static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
100 int where, int size, u32 val)
101{
102 u32 data;
103
104 if ((size == 2) && (where & 1))
105 return PCIBIOS_BAD_REGISTER_NUMBER;
106 else if ((size == 4) && (where & 3))
107 return PCIBIOS_BAD_REGISTER_NUMBER;
108
109 data = pci_cfg_read_32bit(bus, devfn, where);
110
111 if (size == 1)
112 data = (data & ~(0xff << ((where & 3) << 3))) |
113 (val << ((where & 3) << 3));
114 else if (size == 2)
115 data = (data & ~(0xffff << ((where & 3) << 3))) |
116 (val << ((where & 3) << 3));
117 else
118 data = val;
119
120 pci_cfg_write_32bit(bus, devfn, where, data);
121
122 return PCIBIOS_SUCCESSFUL;
123}
124
125struct pci_ops nlm_pci_ops = {
126 .read = nlm_pcibios_read,
127 .write = nlm_pcibios_write
128};
129
130static struct resource nlm_pci_mem_resource = {
131 .name = "XLR PCI MEM",
132 .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
133 .end = 0xdfffffffUL,
134 .flags = IORESOURCE_MEM,
135};
136
137static struct resource nlm_pci_io_resource = {
138 .name = "XLR IO MEM",
139 .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
140 .end = 0x100fffffUL,
141 .flags = IORESOURCE_IO,
142};
143
144struct pci_controller nlm_pci_controller = {
145 .index = 0,
146 .pci_ops = &nlm_pci_ops,
147 .mem_resource = &nlm_pci_mem_resource,
148 .mem_offset = 0x00000000UL,
149 .io_resource = &nlm_pci_io_resource,
150 .io_offset = 0x00000000UL,
151};
152
153int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
154{
155 if (!nlm_chip_is_xls())
156 return PIC_PCIX_IRQ; /* for XLR just one IRQ*/
157
158 /*
159 * For XLS PCIe, there is an IRQ per Link, find out which
160 * link the device is on to assign interrupts
161 */
162 if (dev->bus->self == NULL)
163 return 0;
164
165 switch (dev->bus->self->devfn) {
166 case 0x0:
167 return PIC_PCIE_LINK0_IRQ;
168 case 0x8:
169 return PIC_PCIE_LINK1_IRQ;
170 case 0x10:
171 if (nlm_chip_is_xls_b())
172 return PIC_PCIE_XLSB0_LINK2_IRQ;
173 else
174 return PIC_PCIE_LINK2_IRQ;
175 case 0x18:
176 if (nlm_chip_is_xls_b())
177 return PIC_PCIE_XLSB0_LINK3_IRQ;
178 else
179 return PIC_PCIE_LINK3_IRQ;
180 }
181 WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
182 return 0;
183}
184
185/* Do platform specific device initialization at pci_enable_device() time */
186int pcibios_plat_dev_init(struct pci_dev *dev)
187{
188 return 0;
189}
190
191static int __init pcibios_init(void)
192{
193 /* PSB assigns PCI resources */
194 pci_probe_only = 1;
195 pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
196
197 /* Extend IO port for memory mapped io */
198 ioport_resource.start = 0;
199 ioport_resource.end = ~0;
200
201 set_io_port_base(CKSEG1);
202 nlm_pci_controller.io_map_base = CKSEG1;
203
204 pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
205 register_pci_controller(&nlm_pci_controller);
206
207 return 0;
208}
209
210arch_initcall(pcibios_init);
211
212struct pci_fixup pcibios_fixups[] = {
213 {0}
214};
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
index f9b9dcdfa9dd..98fd0099d964 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
@@ -97,7 +97,7 @@ static int msp_per_irq_set_affinity(struct irq_data *d,
97 97
98static struct irq_chip msp_per_irq_controller = { 98static struct irq_chip msp_per_irq_controller = {
99 .name = "MSP_PER", 99 .name = "MSP_PER",
100 .irq_enable = unmask_per_irq. 100 .irq_enable = unmask_per_irq,
101 .irq_disable = mask_per_irq, 101 .irq_disable = mask_per_irq,
102 .irq_ack = msp_per_irq_ack, 102 .irq_ack = msp_per_irq_ack,
103#ifdef CONFIG_SMP 103#ifdef CONFIG_SMP
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index efc9e889b349..2608752898c0 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -55,6 +55,8 @@ void titan_mailbox_irq(void)
55 55
56 if (status & 0x2) 56 if (status & 0x2)
57 smp_call_function_interrupt(); 57 smp_call_function_interrupt();
58 if (status & 0x4)
59 scheduler_ipi();
58 break; 60 break;
59 61
60 case 1: 62 case 1:
@@ -63,6 +65,8 @@ void titan_mailbox_irq(void)
63 65
64 if (status & 0x2) 66 if (status & 0x2)
65 smp_call_function_interrupt(); 67 smp_call_function_interrupt();
68 if (status & 0x4)
69 scheduler_ipi();
66 break; 70 break;
67 } 71 }
68} 72}
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index dbb5c7b4b70f..f8a751c03282 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -35,7 +35,7 @@ LEAF(swsusp_arch_resume)
350: 350:
36 PTR_L t1, PBE_ADDRESS(t0) /* source */ 36 PTR_L t1, PBE_ADDRESS(t0) /* source */
37 PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ 37 PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
38 PTR_ADDIU t3, t1, PAGE_SIZE 38 PTR_ADDU t3, t1, PAGE_SIZE
391: 391:
40 REG_L t8, (t1) 40 REG_L t8, (t1)
41 REG_S t8, (t2) 41 REG_S t8, (t2)
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 37de05d595e7..6c47dfeb7be3 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -185,7 +185,7 @@ int __init rb532_gpio_init(void)
185 struct resource *r; 185 struct resource *r;
186 186
187 r = rb532_gpio_reg0_res; 187 r = rb532_gpio_reg0_res;
188 rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start); 188 rb532_gpio_chip->regbase = ioremap_nocache(r->start, resource_size(r));
189 189
190 if (!rb532_gpio_chip->regbase) { 190 if (!rb532_gpio_chip->regbase) {
191 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); 191 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c
index deddbf0ebe5c..698904daf901 100644
--- a/arch/mips/sgi-ip22/ip22-platform.c
+++ b/arch/mips/sgi-ip22/ip22-platform.c
@@ -132,7 +132,7 @@ static struct platform_device eth1_device = {
132 */ 132 */
133static int __init sgiseeq_devinit(void) 133static int __init sgiseeq_devinit(void)
134{ 134{
135 unsigned int tmp; 135 unsigned int pbdma __maybe_unused;
136 int res, i; 136 int res, i;
137 137
138 eth0_pd.hpc = hpc3c0; 138 eth0_pd.hpc = hpc3c0;
@@ -151,7 +151,7 @@ static int __init sgiseeq_devinit(void)
151 151
152 /* Second HPC is missing? */ 152 /* Second HPC is missing? */
153 if (ip22_is_fullhouse() || 153 if (ip22_is_fullhouse() ||
154 get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1])) 154 get_dbe(pbdma, (unsigned int *)&hpc3c1->pbdma[1]))
155 return 0; 155 return 0;
156 156
157 sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | SGIMC_GIOPAR_EXP164 | 157 sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | SGIMC_GIOPAR_EXP164 |
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index 603fc91c1030..1a94c9894188 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -32,7 +32,7 @@
32static unsigned long dosample(void) 32static unsigned long dosample(void)
33{ 33{
34 u32 ct0, ct1; 34 u32 ct0, ct1;
35 u8 msb, lsb; 35 u8 msb;
36 36
37 /* Start the counter. */ 37 /* Start the counter. */
38 sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | 38 sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
@@ -46,7 +46,7 @@ static unsigned long dosample(void)
46 /* Latch and spin until top byte of counter2 is zero */ 46 /* Latch and spin until top byte of counter2 is zero */
47 do { 47 do {
48 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword); 48 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword);
49 lsb = readb(&sgint->tcnt2); 49 (void) readb(&sgint->tcnt2);
50 msb = readb(&sgint->tcnt2); 50 msb = readb(&sgint->tcnt2);
51 ct1 = read_c0_count(); 51 ct1 = read_c0_count();
52 } while (msb); 52 } while (msb);
diff --git a/arch/mips/sgi-ip27/ip27-hubio.c b/arch/mips/sgi-ip27/ip27-hubio.c
index a1fa4abb3f6a..cd0d5b06cd83 100644
--- a/arch/mips/sgi-ip27/ip27-hubio.c
+++ b/arch/mips/sgi-ip27/ip27-hubio.c
@@ -29,7 +29,6 @@ unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
29 unsigned long xtalk_addr, size_t size) 29 unsigned long xtalk_addr, size_t size)
30{ 30{
31 nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); 31 nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode);
32 volatile hubreg_t junk;
33 unsigned i; 32 unsigned i;
34 33
35 /* use small-window mapping if possible */ 34 /* use small-window mapping if possible */
@@ -64,7 +63,7 @@ unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
64 * after we write it. 63 * after we write it.
65 */ 64 */
66 IIO_ITTE_PUT(nasid, i, HUB_PIO_MAP_TO_MEM, widget, xtalk_addr); 65 IIO_ITTE_PUT(nasid, i, HUB_PIO_MAP_TO_MEM, widget, xtalk_addr);
67 junk = HUB_L(IIO_ITTE_GET(nasid, i)); 66 (void) HUB_L(IIO_ITTE_GET(nasid, i));
68 67
69 return NODE_BWIN_BASE(nasid, widget) + (xtalk_addr % BWIN_SIZE); 68 return NODE_BWIN_BASE(nasid, widget) + (xtalk_addr % BWIN_SIZE);
70 } 69 }
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 0a04603d577c..b18b04e48577 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -147,8 +147,10 @@ static void ip27_do_irq_mask0(void)
147#ifdef CONFIG_SMP 147#ifdef CONFIG_SMP
148 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) { 148 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
149 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); 149 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
150 scheduler_ipi();
150 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) { 151 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
151 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); 152 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
153 scheduler_ipi();
152 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) { 154 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
153 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); 155 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
154 smp_call_function_interrupt(); 156 smp_call_function_interrupt();
diff --git a/arch/mips/sgi-ip27/ip27-klnuma.c b/arch/mips/sgi-ip27/ip27-klnuma.c
index c3d30a88daf3..1d1919a44e88 100644
--- a/arch/mips/sgi-ip27/ip27-klnuma.c
+++ b/arch/mips/sgi-ip27/ip27-klnuma.c
@@ -54,11 +54,8 @@ void __init setup_replication_mask(void)
54 54
55static __init void set_ktext_source(nasid_t client_nasid, nasid_t server_nasid) 55static __init void set_ktext_source(nasid_t client_nasid, nasid_t server_nasid)
56{ 56{
57 cnodeid_t client_cnode;
58 kern_vars_t *kvp; 57 kern_vars_t *kvp;
59 58
60 client_cnode = NASID_TO_COMPACT_NODEID(client_nasid);
61
62 kvp = &hub_data(client_nasid)->kern_vars; 59 kvp = &hub_data(client_nasid)->kern_vars;
63 60
64 KERN_VARS_ADDR(client_nasid) = (unsigned long)kvp; 61 KERN_VARS_ADDR(client_nasid) = (unsigned long)kvp;
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 8d0d2690e962..ef74f3267f91 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -66,18 +66,7 @@ static int rt_next_event(unsigned long delta, struct clock_event_device *evt)
66static void rt_set_mode(enum clock_event_mode mode, 66static void rt_set_mode(enum clock_event_mode mode,
67 struct clock_event_device *evt) 67 struct clock_event_device *evt)
68{ 68{
69 switch (mode) { 69 /* Nothing to do ... */
70 case CLOCK_EVT_MODE_ONESHOT:
71 /* The only mode supported */
72 break;
73
74 case CLOCK_EVT_MODE_PERIODIC:
75 case CLOCK_EVT_MODE_UNUSED:
76 case CLOCK_EVT_MODE_SHUTDOWN:
77 case CLOCK_EVT_MODE_RESUME:
78 /* Nothing to do */
79 break;
80 }
81} 70}
82 71
83int rt_timer_irq; 72int rt_timer_irq;
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index 47b347c992ea..d667875be564 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -20,6 +20,7 @@
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/kernel_stat.h> 22#include <linux/kernel_stat.h>
23#include <linux/sched.h>
23 24
24#include <asm/mmu_context.h> 25#include <asm/mmu_context.h>
25#include <asm/io.h> 26#include <asm/io.h>
@@ -189,10 +190,8 @@ void bcm1480_mailbox_interrupt(void)
189 /* Clear the mailbox to clear the interrupt */ 190 /* Clear the mailbox to clear the interrupt */
190 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); 191 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
191 192
192 /* 193 if (action & SMP_RESCHEDULE_YOURSELF)
193 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the 194 scheduler_ipi();
194 * interrupt will do the reschedule for us
195 */
196 195
197 if (action & SMP_CALL_FUNCTION) 196 if (action & SMP_CALL_FUNCTION)
198 smp_call_function_interrupt(); 197 smp_call_function_interrupt();
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index c00a5cb1128d..38e7f6bd7922 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -21,6 +21,7 @@
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23#include <linux/kernel_stat.h> 23#include <linux/kernel_stat.h>
24#include <linux/sched.h>
24 25
25#include <asm/mmu_context.h> 26#include <asm/mmu_context.h>
26#include <asm/io.h> 27#include <asm/io.h>
@@ -177,10 +178,8 @@ void sb1250_mailbox_interrupt(void)
177 /* Clear the mailbox to clear the interrupt */ 178 /* Clear the mailbox to clear the interrupt */
178 ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); 179 ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
179 180
180 /* 181 if (action & SMP_RESCHEDULE_YOURSELF)
181 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the 182 scheduler_ipi();
182 * interrupt will do the reschedule for us
183 */
184 183
185 if (action & SMP_CALL_FUNCTION) 184 if (action & SMP_CALL_FUNCTION)
186 smp_call_function_interrupt(); 185 smp_call_function_interrupt();
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index c76151b56568..0904d4d30cb3 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -95,7 +95,7 @@ static void __init sni_a20r_timer_setup(void)
95static __init unsigned long dosample(void) 95static __init unsigned long dosample(void)
96{ 96{
97 u32 ct0, ct1; 97 u32 ct0, ct1;
98 volatile u8 msb, lsb; 98 volatile u8 msb;
99 99
100 /* Start the counter. */ 100 /* Start the counter. */
101 outb_p(0x34, 0x43); 101 outb_p(0x34, 0x43);
@@ -108,7 +108,7 @@ static __init unsigned long dosample(void)
108 /* Latch and spin until top byte of counter0 is zero */ 108 /* Latch and spin until top byte of counter0 is zero */
109 do { 109 do {
110 outb(0x00, 0x43); 110 outb(0x00, 0x43);
111 lsb = inb(0x40); 111 (void) inb(0x40);
112 msb = inb(0x40); 112 msb = inb(0x40);
113 ct1 = read_c0_count(); 113 ct1 = read_c0_count();
114 } while (msb); 114 } while (msb);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 20:25:45 -0500