Merge branch 'timers-clocksource-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'timers-clocksource-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  clocksource: convert mips to generic i8253 clocksource
  clocksource: convert x86 to generic i8253 clocksource
  clocksource: convert footbridge to generic i8253 clocksource
  clocksource: add common i8253 PIT clocksource
  blackfin: convert to clocksource_register_hz
  mips: convert to clocksource_register_hz/khz
  sparc: convert to clocksource_register_hz/khz
  alpha: convert to clocksource_register_hz
  microblaze: convert to clocksource_register_hz/khz
  ia64: convert to clocksource_register_hz/khz
  x86: Convert remaining x86 clocksources to clocksource_register_hz/khz
  Make clocksource name const

15 files changed, 20 insertions, 139 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2d1cf9740953..cef1a854487d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2395,6 +2395,7 @@ config MMU
 
 config I8253
         bool
+        select CLKSRC_I8253
         select MIPS_EXTERNAL_TIMER
 
 config ZONE_DMA32
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 2aecb2fdf982..d5da6adbf634 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -141,8 +141,7 @@ static int __init alchemy_time_init(unsigned int m2int)
                 goto cntr_err;
 
         /* register counter1 clocksource and event device */
-        clocksource_set_clock(&au1x_counter1_clocksource, 32768);
-        clocksource_register(&au1x_counter1_clocksource);
+        clocksource_register_hz(&au1x_counter1_clocksource, 32768);
 
         cd->shift = 32;
         cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 26bf71130bf8..29d56afbb02d 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -105,8 +105,7 @@ unsigned long long notrace sched_clock(void)
 void __init plat_time_init(void)
 {
         clocksource_mips.rating = 300;
-        clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate());
-        clocksource_register(&clocksource_mips);
+        clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
 }
 
 static u64 octeon_udelay_factor;
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
index 48bb82372994..9ad011366f73 100644
--- a/arch/mips/include/asm/i8253.h
+++ b/arch/mips/include/asm/i8253.h
@@ -12,8 +12,13 @@
 #define PIT_CH0                 0x40
 #define PIT_CH2                 0x42
 
+#define PIT_LATCH               LATCH
+
 extern raw_spinlock_t i8253_lock;
 
 extern void setup_pit_timer(void);
 
+#define inb_pit inb_p
+#define outb_pit outb_p
+
 #endif /* __ASM_I8253_H */
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index c7f1bfef1574..bc14447e69b5 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -84,12 +84,6 @@ static inline int init_mips_clocksource(void)
 #endif
 }
 
-static inline void clocksource_set_clock(struct clocksource *cs,
-                                         unsigned int clock)
-{
-        clocksource_calc_mult_shift(cs, clock, 4);
-}
-
 static inline void clockevent_set_clock(struct clock_event_device *cd,
                                         unsigned int clock)
 {
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index eaa853a54af6..f83c2dd07a27 100644
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -121,8 +121,7 @@ void __init plat_time_init(void)
 
         clockevents_register_device(&jz4740_clockevent);
 
-        clocksource_set_clock(&jz4740_clocksource, clk_rate);
-        ret = clocksource_register(&jz4740_clocksource);
+        ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
 
         if (ret)
                 printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 0b7377361e22..f0ab92a1b057 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -51,8 +51,7 @@ void __init txx9_clocksource_init(unsigned long baseaddr,
 {
         struct txx9_tmr_reg __iomem *tmrptr;
 
-        clocksource_set_clock(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
-        clocksource_register(&txx9_clocksource.cs);
+        clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
 
         tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
         __raw_writel(TCR_BASE, &tmrptr->tcr);
diff --git a/arch/mips/kernel/csrc-bcm1480.c b/arch/mips/kernel/csrc-bcm1480.c
index 51489f8a825e..f96f99c794a3 100644
--- a/arch/mips/kernel/csrc-bcm1480.c
+++ b/arch/mips/kernel/csrc-bcm1480.c
@@ -49,6 +49,5 @@ void __init sb1480_clocksource_init(void)
 
         plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
         zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000);
-        clocksource_set_clock(cs, zbbus);
-        clocksource_register(cs);
+        clocksource_register_hz(cs, zbbus);
 }
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 23da108506b0..46bd7fa98d6c 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -59,7 +59,5 @@ void __init dec_ioasic_clocksource_init(void)
         printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
 
         clocksource_dec.rating = 200 + freq / 10000000;
-        clocksource_set_clock(&clocksource_dec, freq);
-
-        clocksource_register(&clocksource_dec);
+        clocksource_register_hz(&clocksource_dec, freq);
 }
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
index a27c16c8690e..2e7c5232da8d 100644
--- a/arch/mips/kernel/csrc-powertv.c
+++ b/arch/mips/kernel/csrc-powertv.c
@@ -78,9 +78,7 @@ static void __init powertv_c0_hpt_clocksource_init(void)
 
         clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
 
-        clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
-
-        clocksource_register(&clocksource_mips);
+        clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
 }
 
 /**
@@ -130,43 +128,16 @@ static struct clocksource clocksource_tim_c = {
 /**
  * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
  *
- * The hard part here is coming up with a constant k and shift s such that
- * the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
- * when shifted right by s, yields the corresponding number of nanoseconds.
  * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
- * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
- * number of nanoseconds. Since the TIM_C value has 48 bits and the math is
- * done in 64 bits, avoiding an overflow means that k must be less than
- * 64 - 48 = 16 bits.
+ * 1 / (27,000,000/8) seconds.
  */
 static void __init powertv_tim_c_clocksource_init(void)
 {
-        int                     prescale;
-        unsigned long           dividend;
-        unsigned long           k;
-        int                     s;
-        const int               max_k_bits = (64 - 48) - 1;
-        const unsigned long     billion = 1000000000;
         const unsigned long     counts_per_second = 27000000 / 8;
 
-        prescale = BITS_PER_LONG - ilog2(billion) - 1;
-        dividend = billion << prescale;
-        k = dividend / counts_per_second;
-        s = ilog2(k) - max_k_bits;
-
-        if (s < 0)
-                s = prescale;
-
-        else {
-                k >>= s;
-                s += prescale;
-        }
-
-        clocksource_tim_c.mult = k;
-        clocksource_tim_c.shift = s;
         clocksource_tim_c.rating = 200;
 
-        clocksource_register(&clocksource_tim_c);
+        clocksource_register_hz(&clocksource_tim_c, counts_per_second);
         tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
 }
 
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index e95a3cd48eea..decd1fa38d55 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -30,9 +30,7 @@ int __init init_r4k_clocksource(void)
         /* Calculate a somewhat reasonable rating value */
         clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
 
-        clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
-
-        clocksource_register(&clocksource_mips);
+        clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
 
         return 0;
 }
diff --git a/arch/mips/kernel/csrc-sb1250.c b/arch/mips/kernel/csrc-sb1250.c
index d14d3d1907fa..e9606d907685 100644
--- a/arch/mips/kernel/csrc-sb1250.c
+++ b/arch/mips/kernel/csrc-sb1250.c
@@ -65,6 +65,5 @@ void __init sb1250_clocksource_init(void)
                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
                                                  R_SCD_TIMER_CFG)));
 
-        clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
-        clocksource_register(cs);
+        clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
 }
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index 2392a7a296d4..391221b6a6aa 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -125,87 +125,11 @@ void __init setup_pit_timer(void)
         setup_irq(0, &irq0);
 }
 
-/*
- * Since the PIT overflows every tick, its not very useful
- * to just read by itself. So use jiffies to emulate a free
- * running counter:
- */
-static cycle_t pit_read(struct clocksource *cs)
-{
-        unsigned long flags;
-        int count;
-        u32 jifs;
-        static int old_count;
-        static u32 old_jifs;
-
-        raw_spin_lock_irqsave(&i8253_lock, flags);
-        /*
-         * Although our caller may have the read side of xtime_lock,
-         * this is now a seqlock, and we are cheating in this routine
-         * by having side effects on state that we cannot undo if
-         * there is a collision on the seqlock and our caller has to
-         * retry.  (Namely, old_jifs and old_count.)  So we must treat
-         * jiffies as volatile despite the lock.  We read jiffies
-         * before latching the timer count to guarantee that although
-         * the jiffies value might be older than the count (that is,
-         * the counter may underflow between the last point where
-         * jiffies was incremented and the point where we latch the
-         * count), it cannot be newer.
-         */
-        jifs = jiffies;
-        outb_p(0x00, PIT_MODE); /* latch the count ASAP */
-        count = inb_p(PIT_CH0); /* read the latched count */
-        count |= inb_p(PIT_CH0) << 8;
-
-        /* VIA686a test code... reset the latch if count > max + 1 */
-        if (count > LATCH) {
-                outb_p(0x34, PIT_MODE);
-                outb_p(LATCH & 0xff, PIT_CH0);
-                outb(LATCH >> 8, PIT_CH0);
-                count = LATCH - 1;
-        }
-
-        /*
-         * It's possible for count to appear to go the wrong way for a
-         * couple of reasons:
-         *
-         *  1. The timer counter underflows, but we haven't handled the
-         *     resulting interrupt and incremented jiffies yet.
-         *  2. Hardware problem with the timer, not giving us continuous time,
-         *     the counter does small "jumps" upwards on some Pentium systems,
-         *     (see c't 95/10 page 335 for Neptun bug.)
-         *
-         * Previous attempts to handle these cases intelligently were
-         * buggy, so we just do the simple thing now.
-         */
-        if (count > old_count && jifs == old_jifs) {
-                count = old_count;
-        }
-        old_count = count;
-        old_jifs = jifs;
-
-        raw_spin_unlock_irqrestore(&i8253_lock, flags);
-
-        count = (LATCH - 1) - count;
-
-        return (cycle_t)(jifs * LATCH) + count;
-}
-
-static struct clocksource clocksource_pit = {
-        .name   = "pit",
-        .rating = 110,
-        .read   = pit_read,
-        .mask   = CLOCKSOURCE_MASK(32),
-        .mult   = 0,
-        .shift  = 20,
-};
-
 static int __init init_pit_clocksource(void)
 {
         if (num_possible_cpus() > 1) /* PIT does not scale! */
                 return 0;
 
-        clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
-        return clocksource_register(&clocksource_pit);
+        return clocksource_i8253_init();
 }
 arch_initcall(init_pit_clocksource);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
index 8c807c965199..0cb1b9760e34 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -201,8 +201,6 @@ static struct clocksource clocksource_mfgpt = {
         .rating = 120, /* Functional for real use, but not desired */
         .read = mfgpt_read,
         .mask = CLOCKSOURCE_MASK(32),
-        .mult = 0,
-        .shift = 22,
 };
 
 int __init init_mfgpt_clocksource(void)
@@ -210,8 +208,7 @@ int __init init_mfgpt_clocksource(void)
         if (num_possible_cpus() > 1)    /* MFGPT does not scale! */
                 return 0;
 
-        clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
-        return clocksource_register(&clocksource_mfgpt);
+        return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
 }
 
 arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 3f810c9cbf83..ef74f3267f91 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -163,8 +163,7 @@ static void __init hub_rt_clocksource_init(void)
 {
         struct clocksource *cs = &hub_rt_clocksource;
 
-        clocksource_set_clock(cs, CYCLES_PER_SEC);
-        clocksource_register(cs);
+        clocksource_register_hz(cs, CYCLES_PER_SEC);
 }
 
 void __init plat_time_init(void)