diff options
Diffstat (limited to 'arch/mips/vr41xx/common/icu.c')
-rw-r--r-- | arch/mips/vr41xx/common/icu.c | 92 |
1 files changed, 46 insertions, 46 deletions
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 6d39e222b170..6153b6a05ccf 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c | |||
@@ -159,9 +159,9 @@ void vr41xx_enable_piuint(uint16_t mask) | |||
159 | 159 | ||
160 | if (current_cpu_type() == CPU_VR4111 || | 160 | if (current_cpu_type() == CPU_VR4111 || |
161 | current_cpu_type() == CPU_VR4121) { | 161 | current_cpu_type() == CPU_VR4121) { |
162 | spin_lock_irqsave(&desc->lock, flags); | 162 | raw_spin_lock_irqsave(&desc->lock, flags); |
163 | icu1_set(MPIUINTREG, mask); | 163 | icu1_set(MPIUINTREG, mask); |
164 | spin_unlock_irqrestore(&desc->lock, flags); | 164 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
165 | } | 165 | } |
166 | } | 166 | } |
167 | 167 | ||
@@ -174,9 +174,9 @@ void vr41xx_disable_piuint(uint16_t mask) | |||
174 | 174 | ||
175 | if (current_cpu_type() == CPU_VR4111 || | 175 | if (current_cpu_type() == CPU_VR4111 || |
176 | current_cpu_type() == CPU_VR4121) { | 176 | current_cpu_type() == CPU_VR4121) { |
177 | spin_lock_irqsave(&desc->lock, flags); | 177 | raw_spin_lock_irqsave(&desc->lock, flags); |
178 | icu1_clear(MPIUINTREG, mask); | 178 | icu1_clear(MPIUINTREG, mask); |
179 | spin_unlock_irqrestore(&desc->lock, flags); | 179 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
180 | } | 180 | } |
181 | } | 181 | } |
182 | 182 | ||
@@ -189,9 +189,9 @@ void vr41xx_enable_aiuint(uint16_t mask) | |||
189 | 189 | ||
190 | if (current_cpu_type() == CPU_VR4111 || | 190 | if (current_cpu_type() == CPU_VR4111 || |
191 | current_cpu_type() == CPU_VR4121) { | 191 | current_cpu_type() == CPU_VR4121) { |
192 | spin_lock_irqsave(&desc->lock, flags); | 192 | raw_spin_lock_irqsave(&desc->lock, flags); |
193 | icu1_set(MAIUINTREG, mask); | 193 | icu1_set(MAIUINTREG, mask); |
194 | spin_unlock_irqrestore(&desc->lock, flags); | 194 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
195 | } | 195 | } |
196 | } | 196 | } |
197 | 197 | ||
@@ -204,9 +204,9 @@ void vr41xx_disable_aiuint(uint16_t mask) | |||
204 | 204 | ||
205 | if (current_cpu_type() == CPU_VR4111 || | 205 | if (current_cpu_type() == CPU_VR4111 || |
206 | current_cpu_type() == CPU_VR4121) { | 206 | current_cpu_type() == CPU_VR4121) { |
207 | spin_lock_irqsave(&desc->lock, flags); | 207 | raw_spin_lock_irqsave(&desc->lock, flags); |
208 | icu1_clear(MAIUINTREG, mask); | 208 | icu1_clear(MAIUINTREG, mask); |
209 | spin_unlock_irqrestore(&desc->lock, flags); | 209 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
210 | } | 210 | } |
211 | } | 211 | } |
212 | 212 | ||
@@ -219,9 +219,9 @@ void vr41xx_enable_kiuint(uint16_t mask) | |||
219 | 219 | ||
220 | if (current_cpu_type() == CPU_VR4111 || | 220 | if (current_cpu_type() == CPU_VR4111 || |
221 | current_cpu_type() == CPU_VR4121) { | 221 | current_cpu_type() == CPU_VR4121) { |
222 | spin_lock_irqsave(&desc->lock, flags); | 222 | raw_spin_lock_irqsave(&desc->lock, flags); |
223 | icu1_set(MKIUINTREG, mask); | 223 | icu1_set(MKIUINTREG, mask); |
224 | spin_unlock_irqrestore(&desc->lock, flags); | 224 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
225 | } | 225 | } |
226 | } | 226 | } |
227 | 227 | ||
@@ -234,9 +234,9 @@ void vr41xx_disable_kiuint(uint16_t mask) | |||
234 | 234 | ||
235 | if (current_cpu_type() == CPU_VR4111 || | 235 | if (current_cpu_type() == CPU_VR4111 || |
236 | current_cpu_type() == CPU_VR4121) { | 236 | current_cpu_type() == CPU_VR4121) { |
237 | spin_lock_irqsave(&desc->lock, flags); | 237 | raw_spin_lock_irqsave(&desc->lock, flags); |
238 | icu1_clear(MKIUINTREG, mask); | 238 | icu1_clear(MKIUINTREG, mask); |
239 | spin_unlock_irqrestore(&desc->lock, flags); | 239 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
240 | } | 240 | } |
241 | } | 241 | } |
242 | 242 | ||
@@ -247,9 +247,9 @@ void vr41xx_enable_macint(uint16_t mask) | |||
247 | struct irq_desc *desc = irq_desc + ETHERNET_IRQ; | 247 | struct irq_desc *desc = irq_desc + ETHERNET_IRQ; |
248 | unsigned long flags; | 248 | unsigned long flags; |
249 | 249 | ||
250 | spin_lock_irqsave(&desc->lock, flags); | 250 | raw_spin_lock_irqsave(&desc->lock, flags); |
251 | icu1_set(MMACINTREG, mask); | 251 | icu1_set(MMACINTREG, mask); |
252 | spin_unlock_irqrestore(&desc->lock, flags); | 252 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
253 | } | 253 | } |
254 | 254 | ||
255 | EXPORT_SYMBOL(vr41xx_enable_macint); | 255 | EXPORT_SYMBOL(vr41xx_enable_macint); |
@@ -259,9 +259,9 @@ void vr41xx_disable_macint(uint16_t mask) | |||
259 | struct irq_desc *desc = irq_desc + ETHERNET_IRQ; | 259 | struct irq_desc *desc = irq_desc + ETHERNET_IRQ; |
260 | unsigned long flags; | 260 | unsigned long flags; |
261 | 261 | ||
262 | spin_lock_irqsave(&desc->lock, flags); | 262 | raw_spin_lock_irqsave(&desc->lock, flags); |
263 | icu1_clear(MMACINTREG, mask); | 263 | icu1_clear(MMACINTREG, mask); |
264 | spin_unlock_irqrestore(&desc->lock, flags); | 264 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
265 | } | 265 | } |
266 | 266 | ||
267 | EXPORT_SYMBOL(vr41xx_disable_macint); | 267 | EXPORT_SYMBOL(vr41xx_disable_macint); |
@@ -271,9 +271,9 @@ void vr41xx_enable_dsiuint(uint16_t mask) | |||
271 | struct irq_desc *desc = irq_desc + DSIU_IRQ; | 271 | struct irq_desc *desc = irq_desc + DSIU_IRQ; |
272 | unsigned long flags; | 272 | unsigned long flags; |
273 | 273 | ||
274 | spin_lock_irqsave(&desc->lock, flags); | 274 | raw_spin_lock_irqsave(&desc->lock, flags); |
275 | icu1_set(MDSIUINTREG, mask); | 275 | icu1_set(MDSIUINTREG, mask); |
276 | spin_unlock_irqrestore(&desc->lock, flags); | 276 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
277 | } | 277 | } |
278 | 278 | ||
279 | EXPORT_SYMBOL(vr41xx_enable_dsiuint); | 279 | EXPORT_SYMBOL(vr41xx_enable_dsiuint); |
@@ -283,9 +283,9 @@ void vr41xx_disable_dsiuint(uint16_t mask) | |||
283 | struct irq_desc *desc = irq_desc + DSIU_IRQ; | 283 | struct irq_desc *desc = irq_desc + DSIU_IRQ; |
284 | unsigned long flags; | 284 | unsigned long flags; |
285 | 285 | ||
286 | spin_lock_irqsave(&desc->lock, flags); | 286 | raw_spin_lock_irqsave(&desc->lock, flags); |
287 | icu1_clear(MDSIUINTREG, mask); | 287 | icu1_clear(MDSIUINTREG, mask); |
288 | spin_unlock_irqrestore(&desc->lock, flags); | 288 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
289 | } | 289 | } |
290 | 290 | ||
291 | EXPORT_SYMBOL(vr41xx_disable_dsiuint); | 291 | EXPORT_SYMBOL(vr41xx_disable_dsiuint); |
@@ -295,9 +295,9 @@ void vr41xx_enable_firint(uint16_t mask) | |||
295 | struct irq_desc *desc = irq_desc + FIR_IRQ; | 295 | struct irq_desc *desc = irq_desc + FIR_IRQ; |
296 | unsigned long flags; | 296 | unsigned long flags; |
297 | 297 | ||
298 | spin_lock_irqsave(&desc->lock, flags); | 298 | raw_spin_lock_irqsave(&desc->lock, flags); |
299 | icu2_set(MFIRINTREG, mask); | 299 | icu2_set(MFIRINTREG, mask); |
300 | spin_unlock_irqrestore(&desc->lock, flags); | 300 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
301 | } | 301 | } |
302 | 302 | ||
303 | EXPORT_SYMBOL(vr41xx_enable_firint); | 303 | EXPORT_SYMBOL(vr41xx_enable_firint); |
@@ -307,9 +307,9 @@ void vr41xx_disable_firint(uint16_t mask) | |||
307 | struct irq_desc *desc = irq_desc + FIR_IRQ; | 307 | struct irq_desc *desc = irq_desc + FIR_IRQ; |
308 | unsigned long flags; | 308 | unsigned long flags; |
309 | 309 | ||
310 | spin_lock_irqsave(&desc->lock, flags); | 310 | raw_spin_lock_irqsave(&desc->lock, flags); |
311 | icu2_clear(MFIRINTREG, mask); | 311 | icu2_clear(MFIRINTREG, mask); |
312 | spin_unlock_irqrestore(&desc->lock, flags); | 312 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
313 | } | 313 | } |
314 | 314 | ||
315 | EXPORT_SYMBOL(vr41xx_disable_firint); | 315 | EXPORT_SYMBOL(vr41xx_disable_firint); |
@@ -322,9 +322,9 @@ void vr41xx_enable_pciint(void) | |||
322 | if (current_cpu_type() == CPU_VR4122 || | 322 | if (current_cpu_type() == CPU_VR4122 || |
323 | current_cpu_type() == CPU_VR4131 || | 323 | current_cpu_type() == CPU_VR4131 || |
324 | current_cpu_type() == CPU_VR4133) { | 324 | current_cpu_type() == CPU_VR4133) { |
325 | spin_lock_irqsave(&desc->lock, flags); | 325 | raw_spin_lock_irqsave(&desc->lock, flags); |
326 | icu2_write(MPCIINTREG, PCIINT0); | 326 | icu2_write(MPCIINTREG, PCIINT0); |
327 | spin_unlock_irqrestore(&desc->lock, flags); | 327 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
328 | } | 328 | } |
329 | } | 329 | } |
330 | 330 | ||
@@ -338,9 +338,9 @@ void vr41xx_disable_pciint(void) | |||
338 | if (current_cpu_type() == CPU_VR4122 || | 338 | if (current_cpu_type() == CPU_VR4122 || |
339 | current_cpu_type() == CPU_VR4131 || | 339 | current_cpu_type() == CPU_VR4131 || |
340 | current_cpu_type() == CPU_VR4133) { | 340 | current_cpu_type() == CPU_VR4133) { |
341 | spin_lock_irqsave(&desc->lock, flags); | 341 | raw_spin_lock_irqsave(&desc->lock, flags); |
342 | icu2_write(MPCIINTREG, 0); | 342 | icu2_write(MPCIINTREG, 0); |
343 | spin_unlock_irqrestore(&desc->lock, flags); | 343 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
344 | } | 344 | } |
345 | } | 345 | } |
346 | 346 | ||
@@ -354,9 +354,9 @@ void vr41xx_enable_scuint(void) | |||
354 | if (current_cpu_type() == CPU_VR4122 || | 354 | if (current_cpu_type() == CPU_VR4122 || |
355 | current_cpu_type() == CPU_VR4131 || | 355 | current_cpu_type() == CPU_VR4131 || |
356 | current_cpu_type() == CPU_VR4133) { | 356 | current_cpu_type() == CPU_VR4133) { |
357 | spin_lock_irqsave(&desc->lock, flags); | 357 | raw_spin_lock_irqsave(&desc->lock, flags); |
358 | icu2_write(MSCUINTREG, SCUINT0); | 358 | icu2_write(MSCUINTREG, SCUINT0); |
359 | spin_unlock_irqrestore(&desc->lock, flags); | 359 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
360 | } | 360 | } |
361 | } | 361 | } |
362 | 362 | ||
@@ -370,9 +370,9 @@ void vr41xx_disable_scuint(void) | |||
370 | if (current_cpu_type() == CPU_VR4122 || | 370 | if (current_cpu_type() == CPU_VR4122 || |
371 | current_cpu_type() == CPU_VR4131 || | 371 | current_cpu_type() == CPU_VR4131 || |
372 | current_cpu_type() == CPU_VR4133) { | 372 | current_cpu_type() == CPU_VR4133) { |
373 | spin_lock_irqsave(&desc->lock, flags); | 373 | raw_spin_lock_irqsave(&desc->lock, flags); |
374 | icu2_write(MSCUINTREG, 0); | 374 | icu2_write(MSCUINTREG, 0); |
375 | spin_unlock_irqrestore(&desc->lock, flags); | 375 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
376 | } | 376 | } |
377 | } | 377 | } |
378 | 378 | ||
@@ -386,9 +386,9 @@ void vr41xx_enable_csiint(uint16_t mask) | |||
386 | if (current_cpu_type() == CPU_VR4122 || | 386 | if (current_cpu_type() == CPU_VR4122 || |
387 | current_cpu_type() == CPU_VR4131 || | 387 | current_cpu_type() == CPU_VR4131 || |
388 | current_cpu_type() == CPU_VR4133) { | 388 | current_cpu_type() == CPU_VR4133) { |
389 | spin_lock_irqsave(&desc->lock, flags); | 389 | raw_spin_lock_irqsave(&desc->lock, flags); |
390 | icu2_set(MCSIINTREG, mask); | 390 | icu2_set(MCSIINTREG, mask); |
391 | spin_unlock_irqrestore(&desc->lock, flags); | 391 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
392 | } | 392 | } |
393 | } | 393 | } |
394 | 394 | ||
@@ -402,9 +402,9 @@ void vr41xx_disable_csiint(uint16_t mask) | |||
402 | if (current_cpu_type() == CPU_VR4122 || | 402 | if (current_cpu_type() == CPU_VR4122 || |
403 | current_cpu_type() == CPU_VR4131 || | 403 | current_cpu_type() == CPU_VR4131 || |
404 | current_cpu_type() == CPU_VR4133) { | 404 | current_cpu_type() == CPU_VR4133) { |
405 | spin_lock_irqsave(&desc->lock, flags); | 405 | raw_spin_lock_irqsave(&desc->lock, flags); |
406 | icu2_clear(MCSIINTREG, mask); | 406 | icu2_clear(MCSIINTREG, mask); |
407 | spin_unlock_irqrestore(&desc->lock, flags); | 407 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
408 | } | 408 | } |
409 | } | 409 | } |
410 | 410 | ||
@@ -418,9 +418,9 @@ void vr41xx_enable_bcuint(void) | |||
418 | if (current_cpu_type() == CPU_VR4122 || | 418 | if (current_cpu_type() == CPU_VR4122 || |
419 | current_cpu_type() == CPU_VR4131 || | 419 | current_cpu_type() == CPU_VR4131 || |
420 | current_cpu_type() == CPU_VR4133) { | 420 | current_cpu_type() == CPU_VR4133) { |
421 | spin_lock_irqsave(&desc->lock, flags); | 421 | raw_spin_lock_irqsave(&desc->lock, flags); |
422 | icu2_write(MBCUINTREG, BCUINTR); | 422 | icu2_write(MBCUINTREG, BCUINTR); |
423 | spin_unlock_irqrestore(&desc->lock, flags); | 423 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
424 | } | 424 | } |
425 | } | 425 | } |
426 | 426 | ||
@@ -434,9 +434,9 @@ void vr41xx_disable_bcuint(void) | |||
434 | if (current_cpu_type() == CPU_VR4122 || | 434 | if (current_cpu_type() == CPU_VR4122 || |
435 | current_cpu_type() == CPU_VR4131 || | 435 | current_cpu_type() == CPU_VR4131 || |
436 | current_cpu_type() == CPU_VR4133) { | 436 | current_cpu_type() == CPU_VR4133) { |
437 | spin_lock_irqsave(&desc->lock, flags); | 437 | raw_spin_lock_irqsave(&desc->lock, flags); |
438 | icu2_write(MBCUINTREG, 0); | 438 | icu2_write(MBCUINTREG, 0); |
439 | spin_unlock_irqrestore(&desc->lock, flags); | 439 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
440 | } | 440 | } |
441 | } | 441 | } |
442 | 442 | ||
@@ -486,7 +486,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) | |||
486 | 486 | ||
487 | pin = SYSINT1_IRQ_TO_PIN(irq); | 487 | pin = SYSINT1_IRQ_TO_PIN(irq); |
488 | 488 | ||
489 | spin_lock_irq(&desc->lock); | 489 | raw_spin_lock_irq(&desc->lock); |
490 | 490 | ||
491 | intassign0 = icu1_read(INTASSIGN0); | 491 | intassign0 = icu1_read(INTASSIGN0); |
492 | intassign1 = icu1_read(INTASSIGN1); | 492 | intassign1 = icu1_read(INTASSIGN1); |
@@ -525,7 +525,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) | |||
525 | intassign1 |= (uint16_t)assign << 9; | 525 | intassign1 |= (uint16_t)assign << 9; |
526 | break; | 526 | break; |
527 | default: | 527 | default: |
528 | spin_unlock_irq(&desc->lock); | 528 | raw_spin_unlock_irq(&desc->lock); |
529 | return -EINVAL; | 529 | return -EINVAL; |
530 | } | 530 | } |
531 | 531 | ||
@@ -533,7 +533,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) | |||
533 | icu1_write(INTASSIGN0, intassign0); | 533 | icu1_write(INTASSIGN0, intassign0); |
534 | icu1_write(INTASSIGN1, intassign1); | 534 | icu1_write(INTASSIGN1, intassign1); |
535 | 535 | ||
536 | spin_unlock_irq(&desc->lock); | 536 | raw_spin_unlock_irq(&desc->lock); |
537 | 537 | ||
538 | return 0; | 538 | return 0; |
539 | } | 539 | } |
@@ -546,7 +546,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) | |||
546 | 546 | ||
547 | pin = SYSINT2_IRQ_TO_PIN(irq); | 547 | pin = SYSINT2_IRQ_TO_PIN(irq); |
548 | 548 | ||
549 | spin_lock_irq(&desc->lock); | 549 | raw_spin_lock_irq(&desc->lock); |
550 | 550 | ||
551 | intassign2 = icu1_read(INTASSIGN2); | 551 | intassign2 = icu1_read(INTASSIGN2); |
552 | intassign3 = icu1_read(INTASSIGN3); | 552 | intassign3 = icu1_read(INTASSIGN3); |
@@ -593,7 +593,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) | |||
593 | intassign3 |= (uint16_t)assign << 12; | 593 | intassign3 |= (uint16_t)assign << 12; |
594 | break; | 594 | break; |
595 | default: | 595 | default: |
596 | spin_unlock_irq(&desc->lock); | 596 | raw_spin_unlock_irq(&desc->lock); |
597 | return -EINVAL; | 597 | return -EINVAL; |
598 | } | 598 | } |
599 | 599 | ||
@@ -601,7 +601,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) | |||
601 | icu1_write(INTASSIGN2, intassign2); | 601 | icu1_write(INTASSIGN2, intassign2); |
602 | icu1_write(INTASSIGN3, intassign3); | 602 | icu1_write(INTASSIGN3, intassign3); |
603 | 603 | ||
604 | spin_unlock_irq(&desc->lock); | 604 | raw_spin_unlock_irq(&desc->lock); |
605 | 605 | ||
606 | return 0; | 606 | return 0; |
607 | } | 607 | } |