aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/powertv/asic
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/powertv/asic')
-rw-r--r--arch/mips/powertv/asic/asic-calliope.c2
-rw-r--r--arch/mips/powertv/asic/asic-cronus.c4
-rw-r--r--arch/mips/powertv/asic/asic-zeus.c2
-rw-r--r--arch/mips/powertv/asic/asic_devices.c6
4 files changed, 7 insertions, 7 deletions
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 1ae6623444b2..0a170e0ffeaa 100644
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -77,7 +77,7 @@ const struct register_map calliope_register_map __initdata = {
77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)}, 77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
78 78
79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)}, 79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
80 .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)}, 80 .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)},
81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)}, 81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)}, 82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)}, 83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index 5bb64bfb508b..bbc0c122be5e 100644
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -77,13 +77,13 @@ const struct register_map cronus_register_map __initdata = {
77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)}, 77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
78 78
79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)}, 79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
80 .usb_fs = {.phys = CRONUS_ADDR(0x1C0018)}, 80 .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)},
81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)}, 81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)}, 82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)}, 83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)}, 84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)}, 85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)}, 86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)},
87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)}, 87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)}, 88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)}, 89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
index 095cbe10ebb9..4a05bb096476 100644
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -77,7 +77,7 @@ const struct register_map zeus_register_map __initdata = {
77 .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)}, 77 .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
78 78
79 .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)}, 79 .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
80 .usb_fs = {.phys = ZEUS_ADDR(0x1a0018)}, 80 .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)},
81 .test_bus = {.phys = ZEUS_ADDR(0x1a0238)}, 81 .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
82 .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)}, 82 .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
83 .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)}, 83 .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index c81dd497ed7b..006285c30648 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -180,9 +180,9 @@ static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
180 val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) | 180 val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
181 (nsb<<1) | (disable_div_by_3<<5)); 181 (nsb<<1) | (disable_div_by_3<<5));
182 182
183 asic_write(val, usb_fs); 183 asic_write(val, fs432x4b4_usb_ctl);
184 asic_write(val | (en_prg<<4), usb_fs); 184 asic_write(val | (en_prg<<4), fs432x4b4_usb_ctl);
185 asic_write(val | (en_prg<<4) | pwr, usb_fs); 185 asic_write(val | (en_prg<<4) | pwr, fs432x4b4_usb_ctl);
186} 186}
187 187
188/* 188/*