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Diffstat (limited to 'arch/mips/powertv/asic/asic-cronus.c')
-rw-r--r--arch/mips/powertv/asic/asic-cronus.c131
1 files changed, 67 insertions, 64 deletions
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index 5f4589c9f83d..5bb64bfb508b 100644
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -23,76 +23,79 @@
23 * Description: Defines the platform resources for the SA settop. 23 * Description: Defines the platform resources for the SA settop.
24 */ 24 */
25 25
26#include <linux/init.h>
26#include <asm/mach-powertv/asic.h> 27#include <asm/mach-powertv/asic.h>
27 28
28const struct register_map cronus_register_map = { 29#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
29 .eic_slow0_strt_add = 0x000000,
30 .eic_cfg_bits = 0x000038,
31 .eic_ready_status = 0x00004C,
32 30
33 .chipver3 = 0x2A0800, 31const struct register_map cronus_register_map __initdata = {
34 .chipver2 = 0x2A0804, 32 .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
35 .chipver1 = 0x2A0808, 33 .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
36 .chipver0 = 0x2A080C, 34 .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
35
36 .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)},
37 .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)},
38 .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)},
39 .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)},
37 40
38 /* The registers of IRBlaster */ 41 /* The registers of IRBlaster */
39 .uart1_intstat = 0x2A1800, 42 .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)},
40 .uart1_inten = 0x2A1804, 43 .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)},
41 .uart1_config1 = 0x2A1808, 44 .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)},
42 .uart1_config2 = 0x2A180C, 45 .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)},
43 .uart1_divisorhi = 0x2A1810, 46 .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)},
44 .uart1_divisorlo = 0x2A1814, 47 .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)},
45 .uart1_data = 0x2A1818, 48 .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)},
46 .uart1_status = 0x2A181C, 49 .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)},
47 50
48 .int_stat_3 = 0x2A2800, 51 .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)},
49 .int_stat_2 = 0x2A2804, 52 .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)},
50 .int_stat_1 = 0x2A2808, 53 .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)},
51 .int_stat_0 = 0x2A280C, 54 .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)},
52 .int_config = 0x2A2810, 55 .int_config = {.phys = CRONUS_ADDR(0x2A2810)},
53 .int_int_scan = 0x2A2818, 56 .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)},
54 .ien_int_3 = 0x2A2830, 57 .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)},
55 .ien_int_2 = 0x2A2834, 58 .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)},
56 .ien_int_1 = 0x2A2838, 59 .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)},
57 .ien_int_0 = 0x2A283C, 60 .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)},
58 .int_level_3_3 = 0x2A2880, 61 .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)},
59 .int_level_3_2 = 0x2A2884, 62 .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)},
60 .int_level_3_1 = 0x2A2888, 63 .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)},
61 .int_level_3_0 = 0x2A288C, 64 .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)},
62 .int_level_2_3 = 0x2A2890, 65 .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)},
63 .int_level_2_2 = 0x2A2894, 66 .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)},
64 .int_level_2_1 = 0x2A2898, 67 .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)},
65 .int_level_2_0 = 0x2A289C, 68 .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)},
66 .int_level_1_3 = 0x2A28A0, 69 .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)},
67 .int_level_1_2 = 0x2A28A4, 70 .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)},
68 .int_level_1_1 = 0x2A28A8, 71 .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)},
69 .int_level_1_0 = 0x2A28AC, 72 .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)},
70 .int_level_0_3 = 0x2A28B0, 73 .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)},
71 .int_level_0_2 = 0x2A28B4, 74 .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)},
72 .int_level_0_1 = 0x2A28B8, 75 .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)},
73 .int_level_0_0 = 0x2A28BC, 76 .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)},
74 .int_docsis_en = 0x2A28F4, 77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
75 78
76 .mips_pll_setup = 0x1C0000, 79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
77 .usb_fs = 0x1C0018, 80 .usb_fs = {.phys = CRONUS_ADDR(0x1C0018)},
78 .test_bus = 0x1C00CC, 81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
79 .crt_spare = 0x1c00d4, 82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
80 .usb2_ohci_int_mask = 0x20000C, 83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
81 .usb2_strap = 0x200014, 84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
82 .ehci_hcapbase = 0x21FE00, 85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
83 .ohci_hc_revision = 0x1E0000, 86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)},
84 .bcm1_bs_lmi_steer = 0x2E0008, 87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
85 .usb2_control = 0x2E004C, 88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
86 .usb2_stbus_obc = 0x21FF00, 89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
87 .usb2_stbus_mess_size = 0x21FF04, 90 .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)},
88 .usb2_stbus_chunk_size = 0x21FF08, 91 .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)},
89 92
90 .pcie_regs = 0x220000, 93 .pcie_regs = {.phys = CRONUS_ADDR(0x220000)},
91 .tim_ch = 0x2A2C10, 94 .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)},
92 .tim_cl = 0x2A2C14, 95 .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)},
93 .gpio_dout = 0x2A2C20, 96 .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)},
94 .gpio_din = 0x2A2C24, 97 .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)},
95 .gpio_dir = 0x2A2C2C, 98 .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)},
96 .watchdog = 0x2A2C30, 99 .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)},
97 .front_panel = 0x2A3800, 100 .front_panel = {.phys = CRONUS_ADDR(0x2A3800)},
98}; 101};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-02 20:28:07 -0400