diff options
Diffstat (limited to 'arch/mips/philips/pnx8550/common/int.c')
-rw-r--r-- | arch/mips/philips/pnx8550/common/int.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c index 39ee6314f627..8f18764a2359 100644 --- a/arch/mips/philips/pnx8550/common/int.c +++ b/arch/mips/philips/pnx8550/common/int.c | |||
@@ -236,7 +236,7 @@ void __init arch_init_irq(void) | |||
236 | int configPR; | 236 | int configPR; |
237 | 237 | ||
238 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { | 238 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { |
239 | irq_desc[i].handler = &level_irq_type; | 239 | irq_desc[i].chip = &level_irq_type; |
240 | pnx8550_ack(i); /* mask the irq just in case */ | 240 | pnx8550_ack(i); /* mask the irq just in case */ |
241 | } | 241 | } |
242 | 242 | ||
@@ -273,7 +273,7 @@ void __init arch_init_irq(void) | |||
273 | /* mask/priority is still 0 so we will not get any | 273 | /* mask/priority is still 0 so we will not get any |
274 | * interrupts until it is unmasked */ | 274 | * interrupts until it is unmasked */ |
275 | 275 | ||
276 | irq_desc[i].handler = &level_irq_type; | 276 | irq_desc[i].chip = &level_irq_type; |
277 | } | 277 | } |
278 | 278 | ||
279 | /* Priority level 0 */ | 279 | /* Priority level 0 */ |
@@ -282,12 +282,12 @@ void __init arch_init_irq(void) | |||
282 | /* Set int vector table address */ | 282 | /* Set int vector table address */ |
283 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; | 283 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; |
284 | 284 | ||
285 | irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type; | 285 | irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; |
286 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); | 286 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); |
287 | 287 | ||
288 | /* init of Timer interrupts */ | 288 | /* init of Timer interrupts */ |
289 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { | 289 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { |
290 | irq_desc[i].handler = &level_irq_type; | 290 | irq_desc[i].chip = &level_irq_type; |
291 | } | 291 | } |
292 | 292 | ||
293 | /* Stop Timer 1-3 */ | 293 | /* Stop Timer 1-3 */ |
@@ -295,7 +295,7 @@ void __init arch_init_irq(void) | |||
295 | configPR |= 0x00000038; | 295 | configPR |= 0x00000038; |
296 | write_c0_config7(configPR); | 296 | write_c0_config7(configPR); |
297 | 297 | ||
298 | irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type; | 298 | irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; |
299 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); | 299 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); |
300 | } | 300 | } |
301 | 301 | ||