8 files changed, 17 insertions, 31 deletions

diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
index fba5aad00d51..0d9ccf4dfc5a 100644
--- a/arch/mips/pci/fixup-emma2rh.c
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -1,7 +1,4 @@
 /*
- *  arch/mips/pci/fixup-emma2rh.c
- *      This file defines the PCI configration.
- *
  *  Copyright (C) NEC Electronics Corporation 2004-2006
  *
  *  This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c
index 0ad39e53f7b1..f0bb9146e6c0 100644
--- a/arch/mips/pci/fixup-sb1250.c
+++ b/arch/mips/pci/fixup-sb1250.c
@@ -1,6 +1,4 @@
 /*
- *      arch/mips/pci/fixup-sb1250.c
- *
  *      Copyright (C) 2004, 2006  MIPS Technologies, Inc.  All rights reserved.
  *          Author:     Maciej W. Rozycki <macro@mips.com>
  *
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c
index 5947a70b0b7f..710aef5c070e 100644
--- a/arch/mips/pci/ops-emma2rh.c
+++ b/arch/mips/pci/ops-emma2rh.c
@@ -1,7 +1,4 @@
 /*
- *  arch/mips/pci/ops-emma2rh.c
- *      This file defines the PCI operation for EMMA2RH.
- *
  *  Copyright (C) NEC Electronics Corporation 2004-2006
  *
  *  This file is based on the arch/mips/pci/ops-vr41xx.c
diff --git a/arch/mips/pci/pci-emma2rh.c b/arch/mips/pci/pci-emma2rh.c
index 2df4190232cd..773e34ff4d1c 100644
--- a/arch/mips/pci/pci-emma2rh.c
+++ b/arch/mips/pci/pci-emma2rh.c
@@ -1,7 +1,4 @@
 /*
- *  arch/mips/pci/pci-emma2rh.c
- *      This file defines the PCI configration.
- *
  *  Copyright (C) NEC Electronics Corporation 2004-2006
  *
  *  This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
index aaa900596792..a5807406a7f1 100644
--- a/arch/mips/pci/pci-tx4927.c
+++ b/arch/mips/pci/pci-tx4927.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/mips/pci/pci-tx4927.c
- *
  * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
  *          and RBTX49xx patch from CELF patch archive.
  *
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
index 1ea257bc3b8f..20e45f30b2ef 100644
--- a/arch/mips/pci/pci-tx4938.c
+++ b/arch/mips/pci/pci-tx4938.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/mips/pci/pci-tx4938.c
- *
  * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
  *          and RBTX49xx patch from CELF patch archive.
  *
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
index 5fecf1cdc325..9ef840693baf 100644
--- a/arch/mips/pci/pci-tx4939.c
+++ b/arch/mips/pci/pci-tx4939.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/mips/pci/pci-tx4939.c
- *
  * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
  *          and RBTX49xx patch from CELF patch archive.
  *
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 75262247f3e4..6aa5c542d52d 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -1040,19 +1040,29 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
         int bus_number = bus->number;
 
         /*
-         * We need to force the bus number to be zero on the root
-         * bus. Linux numbers the 2nd root bus to start after all
-         * buses on root 0.
+         * For the top level bus make sure our hardware bus number
+         * matches the software one.
          */
-        if (bus->parent == NULL)
-                bus_number = 0;
+        if (bus->parent == NULL) {
+                union cvmx_pciercx_cfg006 pciercx_cfg006;
+                pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
+                        CVMX_PCIERCX_CFG006(pcie_port));
+                if (pciercx_cfg006.s.pbnum != bus_number) {
+                        pciercx_cfg006.s.pbnum = bus_number;
+                        pciercx_cfg006.s.sbnum = bus_number;
+                        pciercx_cfg006.s.subbnum = bus_number;
+                        cvmx_pcie_cfgx_write(pcie_port,
+                                CVMX_PCIERCX_CFG006(pcie_port),
+                                pciercx_cfg006.u32);
+                }
+        }
 
         /*
          * PCIe only has a single device connected to Octeon. It is
          * always device ID 0. Don't bother doing reads for other
          * device IDs on the first segment.
          */
-        if ((bus_number == 0) && (devfn >> 3 != 0))
+        if ((bus->parent == NULL) && (devfn >> 3 != 0))
                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 
         /*
@@ -1070,7 +1080,7 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
                  * bridge only respondes to device ID 0, function
                  * 0-1
                  */
-                if ((bus_number == 0) && (devfn >= 2))
+                if ((bus->parent == NULL) && (devfn >= 2))
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
                 /*
                  * The PCI-X slots are device ID 2,3. Choose one of
@@ -1167,13 +1177,6 @@ static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
                                            int size, u32 val)
 {
         int bus_number = bus->number;
-        /*
-         * We need to force the bus number to be zero on the root
-         * bus. Linux numbers the 2nd root bus to start after all
-         * busses on root 0.
-         */
-        if (bus->parent == NULL)
-                bus_number = 0;
 
         switch (size) {
         case 4: