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-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/fixup-atlas.c41
-rw-r--r--arch/mips/pci/fixup-au1000.c78
-rw-r--r--arch/mips/pci/fixup-cobalt.c55
-rw-r--r--arch/mips/pci/fixup-pnx8550.c57
-rw-r--r--arch/mips/pci/fixup-tx4938.c92
-rw-r--r--arch/mips/pci/ops-au1000.c14
-rw-r--r--arch/mips/pci/ops-bonito64.c14
-rw-r--r--arch/mips/pci/ops-gt64111.c10
-rw-r--r--arch/mips/pci/ops-gt64120.c10
-rw-r--r--arch/mips/pci/ops-msc.c31
-rw-r--r--arch/mips/pci/ops-nile4.c2
-rw-r--r--arch/mips/pci/ops-pnx8550.c284
-rw-r--r--arch/mips/pci/ops-tx4938.c198
-rw-r--r--arch/mips/pci/pci-bcm1480.c265
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c224
-rw-r--r--arch/mips/pci/pci-ip27.c7
-rw-r--r--arch/mips/pci/pci-ip32.c4
-rw-r--r--arch/mips/pci/pci-lasat.c56
-rw-r--r--arch/mips/pci/pci.c19
20 files changed, 1277 insertions, 187 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 83d81c9cdc2b..7b7468304022 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o
34obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o 34obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o
35obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 35obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
36obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 36obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
37obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
37obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 38obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
38obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o 39obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o
39obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o 40obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
@@ -45,11 +46,13 @@ obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
45obj-$(CONFIG_SGI_IP27) += pci-ip27.o 46obj-$(CONFIG_SGI_IP27) += pci-ip27.o
46obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o 47obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
47obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 48obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
49obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
48obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o 50obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o
49obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 51obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
50obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 52obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
51obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 53obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
52obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o 54obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o
53obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o 55obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
56obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
54obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 57obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
55obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 58obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
index 2406835833d6..87920b245931 100644
--- a/arch/mips/pci/fixup-atlas.c
+++ b/arch/mips/pci/fixup-atlas.c
@@ -1,14 +1,37 @@
1/*
2 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
3 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
4 * Author: Maciej W. Rozycki <macro@mips.com>
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
1#include <linux/config.h> 19#include <linux/config.h>
2#include <linux/init.h> 20#include <linux/init.h>
3#include <linux/pci.h> 21#include <linux/pci.h>
22
4#include <asm/mips-boards/atlasint.h> 23#include <asm/mips-boards/atlasint.h>
5 24
6#define INTD ATLASINT_INTD 25#define PCIA ATLASINT_PCIA
7#define INTC ATLASINT_INTC 26#define PCIB ATLASINT_PCIB
8#define INTB ATLASINT_INTB 27#define PCIC ATLASINT_PCIC
28#define PCID ATLASINT_PCID
9#define INTA ATLASINT_INTA 29#define INTA ATLASINT_INTA
10#define SCSI ATLASINT_SCSI 30#define INTB ATLASINT_INTB
11#define ETH ATLASINT_ETH 31#define ETH ATLASINT_ETH
32#define INTC ATLASINT_INTC
33#define SCSI ATLASINT_SCSI
34#define INTD ATLASINT_INTD
12 35
13static char irq_tab[][5] __initdata = { 36static char irq_tab[][5] __initdata = {
14 /* INTA INTB INTC INTD */ 37 /* INTA INTB INTC INTD */
@@ -27,13 +50,13 @@ static char irq_tab[][5] __initdata = {
27 {0, 0, 0, 0, 0 }, /* 12: Unused */ 50 {0, 0, 0, 0, 0 }, /* 12: Unused */
28 {0, 0, 0, 0, 0 }, /* 13: Unused */ 51 {0, 0, 0, 0, 0 }, /* 13: Unused */
29 {0, 0, 0, 0, 0 }, /* 14: Unused */ 52 {0, 0, 0, 0, 0 }, /* 14: Unused */
30 {0, 0, 0, 0, 0 }, /* 15: Unused */ 53 {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */
31 {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */ 54 {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */
32 {0, 0, 0, 0, 0 }, /* 17: Core */ 55 {0, 0, 0, 0, 0 }, /* 17: Core */
33 {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot 1 */ 56 {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */
34 {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Ethernet */ 57 {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */
35 {0, 0, 0, 0, 0 }, /* 20: PCI Slot 3 */ 58 {0, 0, 0, 0, 0 }, /* 20: Unused */
36 {0, 0, 0, 0, 0 } /* 21: PCI Slot 4 */ 59 {0, 0, 0, 0, 0 } /* 21: Unused */
37}; 60};
38 61
39int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 62int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
index 39fe2b16fcec..c2f8304fe55b 100644
--- a/arch/mips/pci/fixup-au1000.c
+++ b/arch/mips/pci/fixup-au1000.c
@@ -26,7 +26,6 @@
26 * with this program; if not, write to the Free Software Foundation, Inc., 26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */ 28 */
29#include <linux/config.h>
30#include <linux/types.h> 29#include <linux/types.h>
31#include <linux/pci.h> 30#include <linux/pci.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
@@ -34,82 +33,7 @@
34 33
35#include <asm/mach-au1x00/au1000.h> 34#include <asm/mach-au1x00/au1000.h>
36 35
37/* 36extern char irq_tab_alchemy[][5];
38 * Shortcut
39 */
40#ifdef CONFIG_SOC_AU1500
41#define INTA AU1000_PCI_INTA
42#define INTB AU1000_PCI_INTB
43#define INTC AU1000_PCI_INTC
44#define INTD AU1000_PCI_INTD
45#endif
46
47#ifdef CONFIG_SOC_AU1550
48#define INTA AU1550_PCI_INTA
49#define INTB AU1550_PCI_INTB
50#define INTC AU1550_PCI_INTC
51#define INTD AU1550_PCI_INTD
52#endif
53
54#define INTX 0xFF /* not valid */
55
56#ifdef CONFIG_MIPS_DB1500
57static char irq_tab_alchemy[][5] __initdata = {
58 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */
59 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
60};
61#endif
62
63#ifdef CONFIG_MIPS_BOSPORUS
64static char irq_tab_alchemy[][5] __initdata = {
65 [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */
66 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */
67 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
68};
69#endif
70
71#ifdef CONFIG_MIPS_MIRAGE
72static char irq_tab_alchemy[][5] __initdata = {
73 [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */
74 [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */
75 [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */
76};
77#endif
78
79#ifdef CONFIG_MIPS_DB1550
80static char irq_tab_alchemy[][5] __initdata = {
81 [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */
82 [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
83 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
84};
85#endif
86
87#ifdef CONFIG_MIPS_PB1500
88static char irq_tab_alchemy[][5] __initdata = {
89 [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */
90 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
91};
92#endif
93
94#ifdef CONFIG_MIPS_PB1550
95static char irq_tab_alchemy[][5] __initdata = {
96 [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
97 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
98};
99#endif
100
101#ifdef CONFIG_MIPS_MTX1
102static char irq_tab_alchemy[][5] __initdata = {
103 [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */
104 [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
105 [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */
106 [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
107 [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */
108 [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
109 [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */
110 [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
111};
112#endif
113 37
114int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 38int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
115{ 39{
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 57e1ca2116bb..909292f50d06 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -21,6 +21,20 @@
21 21
22extern int cobalt_board_id; 22extern int cobalt_board_id;
23 23
24static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
25{
26 if (dev->devfn == PCI_DEVFN(0, 0) &&
27 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
28
29 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
30
31 printk(KERN_INFO "Galileo: fixed bridge class\n");
32 }
33}
34
35DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
36 qube_raq_galileo_early_fixup);
37
24static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) 38static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
25{ 39{
26 unsigned short cfgword; 40 unsigned short cfgword;
@@ -48,6 +62,9 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
48{ 62{
49 unsigned short galileo_id; 63 unsigned short galileo_id;
50 64
65 if (dev->devfn != PCI_DEVFN(0, 0))
66 return;
67
51 /* Fix PCI latency-timer and cache-line-size values in Galileo 68 /* Fix PCI latency-timer and cache-line-size values in Galileo
52 * host bridge. 69 * host bridge.
53 */ 70 */
@@ -55,6 +72,13 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
55 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); 72 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
56 73
57 /* 74 /*
75 * The code described by the comment below has been removed
76 * as it causes bus mastering by the Ethernet controllers
77 * to break under any kind of network load. We always set
78 * the retry timeouts to their maximum.
79 *
80 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
81 *
58 * On all machines prior to Q2, we had the STOP line disconnected 82 * On all machines prior to Q2, we had the STOP line disconnected
59 * from Galileo to VIA on PCI. The new Galileo does not function 83 * from Galileo to VIA on PCI. The new Galileo does not function
60 * correctly unless we have it connected. 84 * correctly unless we have it connected.
@@ -64,21 +88,43 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
64 */ 88 */
65 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); 89 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
66 galileo_id &= 0xff; /* mask off class info */ 90 galileo_id &= 0xff; /* mask off class info */
91
92 printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
93
94#if 0
67 if (galileo_id >= 0x10) { 95 if (galileo_id >= 0x10) {
68 /* New Galileo, assumes PCI stop line to VIA is connected. */ 96 /* New Galileo, assumes PCI stop line to VIA is connected. */
69 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); 97 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
70 } else if (galileo_id == 0x1 || galileo_id == 0x2) { 98 } else if (galileo_id == 0x1 || galileo_id == 0x2)
99#endif
100 {
71 signed int timeo; 101 signed int timeo;
72 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
73 timeo = GALILEO_INL(GT_PCI0_TOR_OFS); 103 timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
74 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
75 GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS); 105 GALILEO_OUTL(
106 (0xff << 16) | /* retry count */
107 (0xff << 8) | /* timeout 1 */
108 0xff, /* timeout 0 */
109 GT_PCI0_TOR_OFS);
110
111 /* enable PCI retry exceeded interrupt */
112 GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
76 } 113 }
77} 114}
78 115
79DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, 116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
80 qube_raq_galileo_fixup); 117 qube_raq_galileo_fixup);
81 118
119static char irq_tab_qube1[] __initdata = {
120 [COBALT_PCICONF_CPU] = 0,
121 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
122 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
123 [COBALT_PCICONF_VIA] = 0,
124 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
125 [COBALT_PCICONF_ETH1] = 0
126};
127
82static char irq_tab_cobalt[] __initdata = { 128static char irq_tab_cobalt[] __initdata = {
83 [COBALT_PCICONF_CPU] = 0, 129 [COBALT_PCICONF_CPU] = 0,
84 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 130 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
@@ -99,6 +145,9 @@ static char irq_tab_raq2[] __initdata = {
99 145
100int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 146int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
101{ 147{
148 if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
149 return irq_tab_qube1[slot];
150
102 if (cobalt_board_id == COBALT_BRD_ID_RAQ2) 151 if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
103 return irq_tab_raq2[slot]; 152 return irq_tab_raq2[slot];
104 153
diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c
new file mode 100644
index 000000000000..4256b3b30b77
--- /dev/null
+++ b/arch/mips/pci/fixup-pnx8550.c
@@ -0,0 +1,57 @@
1/*
2 * Philips PNX8550 pci fixups.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <asm/mach-pnx8550/pci.h>
26#include <asm/mach-pnx8550/int.h>
27
28
29#undef DEBUG
30#ifdef DEBUG
31#define DBG(x...) printk(x)
32#else
33#define DBG(x...)
34#endif
35
36extern char irq_tab_jbs[][5];
37
38void __init pcibios_fixup_resources(struct pci_dev *dev)
39{
40 /* no need to fixup IO resources */
41}
42
43void __init pcibios_fixup(void)
44{
45 /* nothing to do here */
46}
47
48int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
49{
50 return irq_tab_jbs[slot][pin];
51}
52
53/* Do platform specific device initialization at pci_enable_device() time */
54int pcibios_plat_dev_init(struct pci_dev *dev)
55{
56 return 0;
57}
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
new file mode 100644
index 000000000000..f455520ada88
--- /dev/null
+++ b/arch/mips/pci/fixup-tx4938.c
@@ -0,0 +1,92 @@
1/*
2 * Toshiba rbtx4938 pci routines
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/tx4938/rbtx4938.h>
18
19extern struct pci_controller tx4938_pci_controller[];
20
21int pci_get_irq(struct pci_dev *dev, int pin)
22{
23 int irq = pin;
24 u8 slot = PCI_SLOT(dev->devfn);
25 struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
26
27 if (controller == &tx4938_pci_controller[1]) {
28 /* TX4938 PCIC1 */
29 switch (slot) {
30 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
31 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
32 return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
33 break;
34 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
35 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
36 return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
37 break;
38 }
39 return 0;
40 }
41
42 /* IRQ rotation */
43 irq--; /* 0-3 */
44 if (dev->bus->parent == NULL &&
45 (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
46 /* PCI CardSlot (IDSEL=A23) */
47 /* PCIA => PCIA (IDSEL=A23) */
48 irq = (irq + 0 + slot) % 4;
49 } else {
50 /* PCI Backplane */
51 irq = (irq + 33 - slot) % 4;
52 }
53 irq++; /* 1-4 */
54
55 switch (irq) {
56 case 1:
57 irq = RBTX4938_IRQ_IOC_PCIA;
58 break;
59 case 2:
60 irq = RBTX4938_IRQ_IOC_PCIB;
61 break;
62 case 3:
63 irq = RBTX4938_IRQ_IOC_PCIC;
64 break;
65 case 4:
66 irq = RBTX4938_IRQ_IOC_PCID;
67 break;
68 }
69 return irq;
70}
71
72int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
73{
74 unsigned char irq = 0;
75
76 irq = pci_get_irq(dev, pin);
77
78 printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
79 dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
80 PCI_FUNC(dev->devfn), irq);
81
82 return irq;
83}
84
85/*
86 * Do platform specific device initialization at pci_enable_device() time
87 */
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 return 0;
91}
92
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index c1c91ca0f9c2..be1420126c42 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -50,11 +50,6 @@
50 50
51int (*board_pci_idsel)(unsigned int devsel, int assert); 51int (*board_pci_idsel)(unsigned int devsel, int assert);
52 52
53/* CP0 hazard avoidance. */
54#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
55 "nop; nop; nop; nop;\t" \
56 ".set reorder\n\t")
57
58void mod_wired_entry(int entry, unsigned long entrylo0, 53void mod_wired_entry(int entry, unsigned long entrylo0,
59 unsigned long entrylo1, unsigned long entryhi, 54 unsigned long entrylo1, unsigned long entryhi,
60 unsigned long pagemask) 55 unsigned long pagemask)
@@ -66,16 +61,12 @@ void mod_wired_entry(int entry, unsigned long entrylo0,
66 old_ctx = read_c0_entryhi() & 0xff; 61 old_ctx = read_c0_entryhi() & 0xff;
67 old_pagemask = read_c0_pagemask(); 62 old_pagemask = read_c0_pagemask();
68 write_c0_index(entry); 63 write_c0_index(entry);
69 BARRIER;
70 write_c0_pagemask(pagemask); 64 write_c0_pagemask(pagemask);
71 write_c0_entryhi(entryhi); 65 write_c0_entryhi(entryhi);
72 write_c0_entrylo0(entrylo0); 66 write_c0_entrylo0(entrylo0);
73 write_c0_entrylo1(entrylo1); 67 write_c0_entrylo1(entrylo1);
74 BARRIER;
75 tlb_write_indexed(); 68 tlb_write_indexed();
76 BARRIER;
77 write_c0_entryhi(old_ctx); 69 write_c0_entryhi(old_ctx);
78 BARRIER;
79 write_c0_pagemask(old_pagemask); 70 write_c0_pagemask(old_pagemask);
80} 71}
81 72
@@ -128,9 +119,8 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
128 last_entryLo0 = last_entryLo1 = 0xffffffff; 119 last_entryLo0 = last_entryLo1 = 0xffffffff;
129 } 120 }
130 121
131 /* Since the Au1xxx doesn't do the idsel timing exactly to spec, 122 /* Allow board vendors to implement their own off-chip idsel.
132 * many board vendors implement their own off-chip idsel, so call 123 * If it doesn't succeed, may as well bail out at this point.
133 * it now. If it doesn't succeed, may as well bail out at this point.
134 */ 124 */
135 if (board_pci_idsel) { 125 if (board_pci_idsel) {
136 if (board_pci_idsel(device, 1) == 0) { 126 if (board_pci_idsel(device, 1) == 0) {
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 4b4e086a7eb1..dc35270b65a2 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -17,7 +19,6 @@
17 * 19 *
18 * MIPS boards specific PCI support. 20 * MIPS boards specific PCI support.
19 */ 21 */
20#include <linux/config.h>
21#include <linux/types.h> 22#include <linux/types.h>
22#include <linux/pci.h> 23#include <linux/pci.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
@@ -57,13 +58,6 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
57 return -1; 58 return -1;
58 } 59 }
59 60
60#ifdef CONFIG_MIPS_BOARDS_GEN
61 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
62 /* MIPS Core boards have Bonito connected as device 17 */
63 return -1;
64 }
65#endif
66
67 /* Clear cause register bits */ 61 /* Clear cause register bits */
68 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | 62 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
69 BONITO_PCICMD_MTABORT_CLR); 63 BONITO_PCICMD_MTABORT_CLR);
diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c
index c5b0fc184c2a..c1807934768d 100644
--- a/arch/mips/pci/ops-gt64111.c
+++ b/arch/mips/pci/ops-gt64111.c
@@ -18,15 +18,15 @@
18#include <asm/cobalt/cobalt.h> 18#include <asm/cobalt/cobalt.h>
19 19
20/* 20/*
21 * Accessing device 31 hangs the GT64120. Not sure if this will also hang 21 * Device 31 on the GT64111 is used to generate PCI special
22 * the GT64111, let's be paranoid for now. 22 * cycles, so we shouldn't expected to find a device there ...
23 */ 23 */
24static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) 24static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
25{ 25{
26 if (bus->number == 0 && devfn == PCI_DEVFN(31, 0)) 26 if (bus->number == 0 && PCI_SLOT(devfn) < 31)
27 return -1; 27 return 0;
28 28
29 return 0; 29 return -1;
30} 30}
31 31
32static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn, 32static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
diff --git a/arch/mips/pci/ops-gt64120.c b/arch/mips/pci/ops-gt64120.c
index 7b99dfa33dfc..6335844d607a 100644
--- a/arch/mips/pci/ops-gt64120.c
+++ b/arch/mips/pci/ops-gt64120.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
43 unsigned char busnum = bus->number; 45 unsigned char busnum = bus->number;
44 u32 intr; 46 u32 intr;
45 47
46 if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
47 /* Galileo itself is devfn 0, don't move it around */
48 return -1;
49
50 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) 48 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
51 return -1; /* Because of a bug in the galileo (for slot 31). */ 49 return -1; /* Because of a bug in the galileo (for slot 31). */
52 50
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 7bc099643a9d..5d9fbb0f4670 100644
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -21,7 +21,6 @@
21 * MIPS boards specific PCI support. 21 * MIPS boards specific PCI support.
22 * 22 *
23 */ 23 */
24#include <linux/config.h>
25#include <linux/types.h> 24#include <linux/types.h>
26#include <linux/pci.h> 25#include <linux/pci.h>
27#include <linux/kernel.h> 26#include <linux/kernel.h>
@@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type,
49 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 48 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
50{ 49{
51 unsigned char busnum = bus->number; 50 unsigned char busnum = bus->number;
52 unsigned char type;
53 u32 intr; 51 u32 intr;
54 52
55#ifdef CONFIG_MIPS_BOARDS_GEN
56 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
57 /* MIPS Core boards have SOCit connected as device 17 */
58 return -1;
59 }
60#endif
61
62 /* Clear status register bits. */ 53 /* Clear status register bits. */
63 MSC_WRITE(MSC01_PCI_INTSTAT, 54 MSC_WRITE(MSC01_PCI_INTSTAT,
64 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); 55 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
65 56
66 /* Setup address */
67 if (busnum == 0)
68 type = 0; /* Type 0 */
69 else
70 type = 1; /* Type 1 */
71
72 MSC_WRITE(MSC01_PCI_CFGADDR, 57 MSC_WRITE(MSC01_PCI_CFGADDR,
73 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | 58 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
74 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) 59 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
75 | (PCI_FUNC(devfn) << 60 (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
76 MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / 61 ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
77 4) <<
78 MSC01_PCI_CFGADDR_RNUM_SHF)
79 | (type)));
80 62
81 /* Perform access */ 63 /* Perform access */
82 if (access_type == PCI_ACCESS_WRITE) 64 if (access_type == PCI_ACCESS_WRITE)
@@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type,
86 68
87 /* Detect Master/Target abort */ 69 /* Detect Master/Target abort */
88 MSC_READ(MSC01_PCI_INTSTAT, intr); 70 MSC_READ(MSC01_PCI_INTSTAT, intr);
89 if (intr & (MSC01_PCI_INTCFG_MA_BIT | 71 if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
90 MSC01_PCI_INTCFG_TA_BIT)) {
91 /* Error occurred */ 72 /* Error occurred */
92 73
93 /* Clear bits */ 74 /* Clear bits */
94 MSC_READ(MSC01_PCI_INTSTAT, intr);
95 MSC_WRITE(MSC01_PCI_INTSTAT, 75 MSC_WRITE(MSC01_PCI_INTSTAT,
96 (MSC01_PCI_INTCFG_MA_BIT | 76 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
97 MSC01_PCI_INTCFG_TA_BIT));
98 77
99 return -1; 78 return -1;
100 } 79 }
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
index a7169928b351..a8d38dc8c504 100644
--- a/arch/mips/pci/ops-nile4.c
+++ b/arch/mips/pci/ops-nile4.c
@@ -15,7 +15,7 @@
15 15
16volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; 16volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
17 17
18static spinlock_t nile4_pci_lock; 18static DEFINE_SPINLOCK(nile4_pci_lock);
19 19
20static int nile4_pcibios_config_access(unsigned char access_type, 20static int nile4_pcibios_config_access(unsigned char access_type,
21 struct pci_bus *bus, unsigned int devfn, int where, u32 * val) 21 struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c
new file mode 100644
index 000000000000..454b65cc3354
--- /dev/null
+++ b/arch/mips/pci/ops-pnx8550.c
@@ -0,0 +1,284 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * 2.6 port, Embedded Alley Solutions, Inc
6 *
7 * Based on:
8 * Author: source@mvista.com
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 */
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/vmalloc.h>
28#include <linux/delay.h>
29
30#include <asm/mach-pnx8550/pci.h>
31#include <asm/mach-pnx8550/glb.h>
32#include <asm/debug.h>
33
34
35static inline void clear_status(void)
36{
37 unsigned long pci_stat;
38
39 pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS);
40 outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR);
41}
42
43static inline unsigned int
44calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where)
45{
46 unsigned int addr;
47
48 addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0);
49 addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc);
50
51 return addr;
52}
53
54static int
55config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val)
56{
57 unsigned int flags;
58 unsigned long loops = 0;
59 unsigned long ioaddr = calc_cfg_addr(bus, devfn, where);
60
61 local_irq_save(flags);
62 /*Clear pending interrupt status */
63 if (inl(PCI_BASE | PCI_GPPM_STATUS)) {
64 clear_status();
65 while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ;
66 }
67
68 outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR);
69
70 if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE))
71 outl(*val, PCI_BASE | PCI_GPPM_WDAT);
72
73 outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK),
74 PCI_BASE | PCI_GPPM_CTRL);
75
76 loops =
77 ((loops_per_jiffy *
78 PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT));
79 while (1) {
80 if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) {
81 if ((pci_cmd == PCI_CMD_IOR) ||
82 (pci_cmd == PCI_CMD_CONFIG_READ))
83 *val = inl(PCI_BASE | PCI_GPPM_RDAT);
84 clear_status();
85 local_irq_restore(flags);
86 return PCIBIOS_SUCCESSFUL;
87 } else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) {
88 break;
89 }
90
91 loops--;
92 if (loops == 0) {
93 printk("%s : Arbiter Locked.\n", __FUNCTION__);
94 }
95 }
96
97 clear_status();
98 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) {
99 printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n",
100 __FUNCTION__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr,
101 pci_cmd);
102 }
103
104 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ))
105 *val = 0xffffffff;
106 local_irq_restore(flags);
107 return PCIBIOS_DEVICE_NOT_FOUND;
108}
109
110/*
111 * We can't address 8 and 16 bit words directly. Instead we have to
112 * read/write a 32bit word and mask/modify the data we actually want.
113 */
114static int
115read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
116{
117 unsigned int data = 0;
118 int err;
119
120 if (bus == 0)
121 return -1;
122
123 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
124 switch (where & 0x03) {
125 case 0:
126 *val = (unsigned char)(data & 0x000000ff);
127 break;
128 case 1:
129 *val = (unsigned char)((data & 0x0000ff00) >> 8);
130 break;
131 case 2:
132 *val = (unsigned char)((data & 0x00ff0000) >> 16);
133 break;
134 case 3:
135 *val = (unsigned char)((data & 0xff000000) >> 24);
136 break;
137 }
138
139 return err;
140}
141
142static int
143read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
144{
145 unsigned int data = 0;
146 int err;
147
148 if (bus == 0)
149 return -1;
150
151 if (where & 0x01)
152 return PCIBIOS_BAD_REGISTER_NUMBER;
153
154 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data);
155 switch (where & 0x02) {
156 case 0:
157 *val = (unsigned short)(data & 0x0000ffff);
158 break;
159 case 2:
160 *val = (unsigned short)((data & 0xffff0000) >> 16);
161 break;
162 }
163
164 return err;
165}
166
167static int
168read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
169{
170 int err;
171 if (bus == 0)
172 return -1;
173
174 if (where & 0x03)
175 return PCIBIOS_BAD_REGISTER_NUMBER;
176
177 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val);
178
179 return err;
180}
181
182static int
183write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
184{
185 unsigned int data = (unsigned int)val;
186 int err;
187
188 if (bus == 0)
189 return -1;
190
191 switch (where & 0x03) {
192 case 1:
193 data = (data << 8);
194 break;
195 case 2:
196 data = (data << 16);
197 break;
198 case 3:
199 data = (data << 24);
200 break;
201 default:
202 break;
203 }
204
205 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
206
207 return err;
208}
209
210static int
211write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
212{
213 unsigned int data = (unsigned int)val;
214 int err;
215
216 if (bus == 0)
217 return -1;
218
219 if (where & 0x01)
220 return PCIBIOS_BAD_REGISTER_NUMBER;
221
222 switch (where & 0x02) {
223 case 2:
224 data = (data << 16);
225 break;
226 default:
227 break;
228 }
229 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data);
230
231 return err;
232}
233
234static int
235write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
236{
237 int err;
238 if (bus == 0)
239 return -1;
240
241 if (where & 0x03)
242 return PCIBIOS_BAD_REGISTER_NUMBER;
243
244 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val);
245
246 return err;
247}
248
249static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
250{
251 switch (size) {
252 case 1: {
253 u8 _val;
254 int rc = read_config_byte(bus, devfn, where, &_val);
255 *val = _val;
256 return rc;
257 }
258 case 2: {
259 u16 _val;
260 int rc = read_config_word(bus, devfn, where, &_val);
261 *val = _val;
262 return rc;
263 }
264 default:
265 return read_config_dword(bus, devfn, where, val);
266 }
267}
268
269static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
270{
271 switch (size) {
272 case 1:
273 return write_config_byte(bus, devfn, where, (u8) val);
274 case 2:
275 return write_config_word(bus, devfn, where, (u16) val);
276 default:
277 return write_config_dword(bus, devfn, where, val);
278 }
279}
280
281struct pci_ops pnx8550_pci_ops = {
282 config_read,
283 config_write
284};
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
new file mode 100644
index 000000000000..4c0dcfce5297
--- /dev/null
+++ b/arch/mips/pci/ops-tx4938.c
@@ -0,0 +1,198 @@
1/*
2 * Define the pci_ops for the Toshiba rbtx4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/addrspace.h>
18#include <asm/tx4938/rbtx4938.h>
19
20/* initialize in setup */
21struct resource pci_io_resource = {
22 .name = "pci IO space",
23 .start = 0,
24 .end = 0,
25 .flags = IORESOURCE_IO
26};
27
28/* initialize in setup */
29struct resource pci_mem_resource = {
30 .name = "pci memory space",
31 .start = 0,
32 .end = 0,
33 .flags = IORESOURCE_MEM
34};
35
36struct resource tx4938_pcic1_pci_io_resource = {
37 .name = "PCI1 IO",
38 .start = 0,
39 .end = 0,
40 .flags = IORESOURCE_IO
41};
42struct resource tx4938_pcic1_pci_mem_resource = {
43 .name = "PCI1 mem",
44 .start = 0,
45 .end = 0,
46 .flags = IORESOURCE_MEM
47};
48
49static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
50{
51 if (bus > 0) {
52 /* Type 1 configuration */
53 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
54 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
55 } else {
56 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
57 return -1;
58
59 /* Type 0 configuration */
60 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
61 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
62 }
63 /* clear M_ABORT and Disable M_ABORT Int. */
64 tx4938_pcicptr->pcistatus =
65 (tx4938_pcicptr->pcistatus & 0x0000ffff) |
66 (PCI_STATUS_REC_MASTER_ABORT << 16);
67 tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
68
69 return 0;
70}
71
72static int check_abort(int flags)
73{
74 int code = PCIBIOS_SUCCESSFUL;
75 /* wait write cycle completion before checking error status */
76 while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
77 ;
78 if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
79 tx4938_pcicptr->pcistatus =
80 (tx4938_pcicptr->
81 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
82 << 16);
83 tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
84 code = PCIBIOS_DEVICE_NOT_FOUND;
85 }
86 return code;
87}
88
89static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
90 int where, int size, u32 * val)
91{
92 int flags, retval, dev, busno, func;
93
94 dev = PCI_SLOT(devfn);
95 func = PCI_FUNC(devfn);
96
97 /* check if the bus is top-level */
98 if (bus->parent != NULL)
99 busno = bus->number;
100 else {
101 busno = 0;
102 }
103
104 if (mkaddr(busno, devfn, where, &flags))
105 return -1;
106
107 switch (size) {
108 case 1:
109 *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
110#ifdef __BIG_ENDIAN
111 ((where & 3) ^ 3));
112#else
113 (where & 3));
114#endif
115 break;
116 case 2:
117 *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
118#ifdef __BIG_ENDIAN
119 ((where & 3) ^ 2));
120#else
121 (where & 3));
122#endif
123 break;
124 case 4:
125 *val = tx4938_pcicptr->g2pcfgdata;
126 break;
127 }
128
129 retval = check_abort(flags);
130 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
131 *val = 0xffffffff;
132
133 return retval;
134}
135
136static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
137 int size, u32 val)
138{
139 int flags, dev, busno, func;
140
141 busno = bus->number;
142 dev = PCI_SLOT(devfn);
143 func = PCI_FUNC(devfn);
144
145 /* check if the bus is top-level */
146 if (bus->parent != NULL) {
147 busno = bus->number;
148 } else {
149 busno = 0;
150 }
151
152 if (mkaddr(busno, devfn, where, &flags))
153 return -1;
154
155 switch (size) {
156 case 1:
157 *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
158#ifdef __BIG_ENDIAN
159 ((where & 3) ^ 3)) = val;
160#else
161 (where & 3)) = val;
162#endif
163 break;
164 case 2:
165 *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
166#ifdef __BIG_ENDIAN
167 ((where & 0x3) ^ 0x2)) = val;
168#else
169 (where & 3)) = val;
170#endif
171 break;
172 case 4:
173 tx4938_pcicptr->g2pcfgdata = val;
174 break;
175 }
176
177 return check_abort(flags);
178}
179
180struct pci_ops tx4938_pci_ops = {
181 tx4938_pcibios_read_config,
182 tx4938_pcibios_write_config
183};
184
185struct pci_controller tx4938_pci_controller[] = {
186 /* h/w only supports devices 0x00 to 0x14 */
187 {
188 .pci_ops = &tx4938_pci_ops,
189 .io_resource = &pci_io_resource,
190 .mem_resource = &pci_mem_resource,
191 },
192 /* h/w only supports devices 0x00 to 0x14 */
193 {
194 .pci_ops = &tx4938_pci_ops,
195 .io_resource = &tx4938_pcic1_pci_io_resource,
196 .mem_resource = &tx4938_pcic1_pci_mem_resource,
197 }
198};
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
new file mode 100644
index 000000000000..f194b4e4f86a
--- /dev/null
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -0,0 +1,265 @@
1/*
2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20/*
21 * BCM1x80/1x55-specific PCI support
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 *
33 * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
34 */
35#include <linux/config.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/mm.h>
41#include <linux/console.h>
42#include <linux/tty.h>
43
44#include <asm/sibyte/bcm1480_regs.h>
45#include <asm/sibyte/bcm1480_scd.h>
46#include <asm/sibyte/board.h>
47#include <asm/io.h>
48
49/*
50 * Macros for calculating offsets into config space given a device
51 * structure or dev/fun/reg
52 */
53#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
54#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
55
56static void *cfg_space;
57
58#define PCI_BUS_ENABLED 1
59#define PCI_DEVICE_MODE 2
60
61static int bcm1480_bus_status = 0;
62
63#define PCI_BRIDGE_DEVICE 0
64
65/*
66 * Read/write 32-bit values in config space.
67 */
68static inline u32 READCFG32(u32 addr)
69{
70 return *(u32 *)(cfg_space + (addr&~3));
71}
72
73static inline void WRITECFG32(u32 addr, u32 data)
74{
75 *(u32 *)(cfg_space + (addr & ~3)) = data;
76}
77
78int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
79{
80 return dev->irq;
81}
82
83/* Do platform specific device initialization at pci_enable_device() time */
84int pcibios_plat_dev_init(struct pci_dev *dev)
85{
86 return 0;
87}
88
89/*
90 * Some checks before doing config cycles:
91 * In PCI Device Mode, hide everything on bus 0 except the LDT host
92 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
93 */
94static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
95{
96 u32 devno;
97
98 if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
99 return 0;
100
101 if (bus->number == 0) {
102 devno = PCI_SLOT(devfn);
103 if (bcm1480_bus_status & PCI_DEVICE_MODE)
104 return 0;
105 else
106 return 1;
107 } else
108 return 1;
109}
110
111/*
112 * Read/write access functions for various sizes of values
113 * in config space. Return all 1's for disallowed accesses
114 * for a kludgy but adequate simulation of master aborts.
115 */
116
117static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
118 int where, int size, u32 * val)
119{
120 u32 data = 0;
121
122 if ((size == 2) && (where & 1))
123 return PCIBIOS_BAD_REGISTER_NUMBER;
124 else if ((size == 4) && (where & 3))
125 return PCIBIOS_BAD_REGISTER_NUMBER;
126
127 if (bcm1480_pci_can_access(bus, devfn))
128 data = READCFG32(CFGADDR(bus, devfn, where));
129 else
130 data = 0xFFFFFFFF;
131
132 if (size == 1)
133 *val = (data >> ((where & 3) << 3)) & 0xff;
134 else if (size == 2)
135 *val = (data >> ((where & 3) << 3)) & 0xffff;
136 else
137 *val = data;
138
139 return PCIBIOS_SUCCESSFUL;
140}
141
142static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
143 int where, int size, u32 val)
144{
145 u32 cfgaddr = CFGADDR(bus, devfn, where);
146 u32 data = 0;
147
148 if ((size == 2) && (where & 1))
149 return PCIBIOS_BAD_REGISTER_NUMBER;
150 else if ((size == 4) && (where & 3))
151 return PCIBIOS_BAD_REGISTER_NUMBER;
152
153 if (!bcm1480_pci_can_access(bus, devfn))
154 return PCIBIOS_BAD_REGISTER_NUMBER;
155
156 data = READCFG32(cfgaddr);
157
158 if (size == 1)
159 data = (data & ~(0xff << ((where & 3) << 3))) |
160 (val << ((where & 3) << 3));
161 else if (size == 2)
162 data = (data & ~(0xffff << ((where & 3) << 3))) |
163 (val << ((where & 3) << 3));
164 else
165 data = val;
166
167 WRITECFG32(cfgaddr, data);
168
169 return PCIBIOS_SUCCESSFUL;
170}
171
172struct pci_ops bcm1480_pci_ops = {
173 bcm1480_pcibios_read,
174 bcm1480_pcibios_write,
175};
176
177static struct resource bcm1480_mem_resource = {
178 .name = "BCM1480 PCI MEM",
179 .start = 0x30000000UL,
180 .end = 0x3fffffffUL,
181 .flags = IORESOURCE_MEM,
182};
183
184static struct resource bcm1480_io_resource = {
185 .name = "BCM1480 PCI I/O",
186 .start = 0x2c000000UL,
187 .end = 0x2dffffffUL,
188 .flags = IORESOURCE_IO,
189};
190
191struct pci_controller bcm1480_controller = {
192 .pci_ops = &bcm1480_pci_ops,
193 .mem_resource = &bcm1480_mem_resource,
194 .io_resource = &bcm1480_io_resource,
195};
196
197
198static int __init bcm1480_pcibios_init(void)
199{
200 uint32_t cmdreg;
201 uint64_t reg;
202 extern int pci_probe_only;
203
204 /* CFE will assign PCI resources */
205 pci_probe_only = 1;
206
207 /* Avoid ISA compat ranges. */
208 PCIBIOS_MIN_IO = 0x00008000UL;
209 PCIBIOS_MIN_MEM = 0x01000000UL;
210
211 /* Set I/O resource limits. - unlimited for now to accomodate HT */
212 ioport_resource.end = 0xffffffffUL;
213 iomem_resource.end = 0xffffffffUL;
214
215 cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);
216
217 /*
218 * See if the PCI bus has been configured by the firmware.
219 */
220 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
221 if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
222 bcm1480_bus_status |= PCI_DEVICE_MODE;
223 } else {
224 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
225 PCI_COMMAND));
226 if (!(cmdreg & PCI_COMMAND_MASTER)) {
227 printk
228 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
229 iounmap(cfg_space);
230 return 1; /* XXX */
231 }
232 bcm1480_bus_status |= PCI_BUS_ENABLED;
233 }
234
235 /* turn on ExpMemEn */
236 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
237 printk("PCIFeatureCtrl = %x\n", cmdreg);
238 WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
239 cmdreg | 0x10);
240 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
241 printk("PCIFeatureCtrl = %x\n", cmdreg);
242
243 /*
244 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
245 * space. Use "match bytes" policy to make everything look
246 * little-endian. So, you need to also set
247 * CONFIG_SWAP_IO_SPACE, but this is the combination that
248 * works correctly with most of Linux's drivers.
249 * XXX ehs: Should this happen in PCI Device mode?
250 */
251
252 set_io_port_base((unsigned long)
253 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
254 isa_slot_offset = (unsigned long)
255 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
256
257 register_pci_controller(&bcm1480_controller);
258
259#ifdef CONFIG_VGA_CONSOLE
260 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
261#endif
262 return 0;
263}
264
265arch_initcall(bcm1480_pcibios_init);
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
new file mode 100644
index 000000000000..aca4a2e7a1c6
--- /dev/null
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -0,0 +1,224 @@
1/*
2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20/*
21 * BCM1480/1455-specific HT support (looking like PCI)
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 *
33 */
34#include <linux/config.h>
35#include <linux/types.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/mm.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42
43#include <asm/sibyte/bcm1480_regs.h>
44#include <asm/sibyte/bcm1480_scd.h>
45#include <asm/sibyte/board.h>
46#include <asm/io.h>
47
48/*
49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg
51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
54
55static void *ht_cfg_space;
56
57#define PCI_BUS_ENABLED 1
58#define PCI_DEVICE_MODE 2
59
60static int bcm1480ht_bus_status = 0;
61
62#define PCI_BRIDGE_DEVICE 0
63#define HT_BRIDGE_DEVICE 1
64
65/*
66 * HT's level-sensitive interrupts require EOI, which is generated
67 * through a 4MB memory-mapped region
68 */
69unsigned long ht_eoi_space;
70
71/*
72 * Read/write 32-bit values in config space.
73 */
74static inline u32 READCFG32(u32 addr)
75{
76 return *(u32 *)(ht_cfg_space + (addr&~3));
77}
78
79static inline void WRITECFG32(u32 addr, u32 data)
80{
81 *(u32 *)(ht_cfg_space + (addr & ~3)) = data;
82}
83
84/*
85 * Some checks before doing config cycles:
86 * In PCI Device Mode, hide everything on bus 0 except the LDT host
87 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
88 */
89static int bcm1480ht_can_access(struct pci_bus *bus, int devfn)
90{
91 u32 devno;
92
93 if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
94 return 0;
95
96 if (bus->number == 0) {
97 devno = PCI_SLOT(devfn);
98 if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
99 return 0;
100 }
101 return 1;
102}
103
104/*
105 * Read/write access functions for various sizes of values
106 * in config space. Return all 1's for disallowed accesses
107 * for a kludgy but adequate simulation of master aborts.
108 */
109
110static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn,
111 int where, int size, u32 * val)
112{
113 u32 data = 0;
114
115 if ((size == 2) && (where & 1))
116 return PCIBIOS_BAD_REGISTER_NUMBER;
117 else if ((size == 4) && (where & 3))
118 return PCIBIOS_BAD_REGISTER_NUMBER;
119
120 if (bcm1480ht_can_access(bus, devfn))
121 data = READCFG32(CFGADDR(bus, devfn, where));
122 else
123 data = 0xFFFFFFFF;
124
125 if (size == 1)
126 *val = (data >> ((where & 3) << 3)) & 0xff;
127 else if (size == 2)
128 *val = (data >> ((where & 3) << 3)) & 0xffff;
129 else
130 *val = data;
131
132 return PCIBIOS_SUCCESSFUL;
133}
134
135static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn,
136 int where, int size, u32 val)
137{
138 u32 cfgaddr = CFGADDR(bus, devfn, where);
139 u32 data = 0;
140
141 if ((size == 2) && (where & 1))
142 return PCIBIOS_BAD_REGISTER_NUMBER;
143 else if ((size == 4) && (where & 3))
144 return PCIBIOS_BAD_REGISTER_NUMBER;
145
146 if (!bcm1480ht_can_access(bus, devfn))
147 return PCIBIOS_BAD_REGISTER_NUMBER;
148
149 data = READCFG32(cfgaddr);
150
151 if (size == 1)
152 data = (data & ~(0xff << ((where & 3) << 3))) |
153 (val << ((where & 3) << 3));
154 else if (size == 2)
155 data = (data & ~(0xffff << ((where & 3) << 3))) |
156 (val << ((where & 3) << 3));
157 else
158 data = val;
159
160 WRITECFG32(cfgaddr, data);
161
162 return PCIBIOS_SUCCESSFUL;
163}
164
165static int bcm1480ht_pcibios_get_busno(void)
166{
167 return 0;
168}
169
170struct pci_ops bcm1480ht_pci_ops = {
171 .read = bcm1480ht_pcibios_read,
172 .write = bcm1480ht_pcibios_write,
173};
174
175static struct resource bcm1480ht_mem_resource = {
176 .name = "BCM1480 HT MEM",
177 .start = 0x40000000UL,
178 .end = 0x5fffffffUL,
179 .flags = IORESOURCE_MEM,
180};
181
182static struct resource bcm1480ht_io_resource = {
183 .name = "BCM1480 HT I/O",
184 .start = 0x00000000UL,
185 .end = 0x01ffffffUL,
186 .flags = IORESOURCE_IO,
187};
188
189struct pci_controller bcm1480ht_controller = {
190 .pci_ops = &bcm1480ht_pci_ops,
191 .mem_resource = &bcm1480ht_mem_resource,
192 .io_resource = &bcm1480ht_io_resource,
193 .index = 1,
194 .get_busno = bcm1480ht_pcibios_get_busno,
195};
196
197static int __init bcm1480ht_pcibios_init(void)
198{
199 uint32_t cmdreg;
200
201 ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
202
203 /*
204 * See if the PCI bus has been configured by the firmware.
205 */
206 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
207 PCI_COMMAND));
208 if (!(cmdreg & PCI_COMMAND_MASTER)) {
209 printk("HT: Skipping HT probe. Bus is not initialized.\n");
210 iounmap(ht_cfg_space);
211 return 1; /* XXX */
212 }
213 bcm1480ht_bus_status |= PCI_BUS_ENABLED;
214
215 ht_eoi_space = (unsigned long)
216 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
217 4 * 1024 * 1024);
218
219 register_pci_controller(&bcm1480ht_controller);
220
221 return 0;
222}
223
224arch_initcall(bcm1480ht_pcibios_init);
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 068e0e508e15..efc96ce99eeb 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -485,5 +485,12 @@ static void __init pci_fixup_ioc3(struct pci_dev *d)
485 pci_disable_swapping(d); 485 pci_disable_swapping(d);
486} 486}
487 487
488int pcibus_to_node(struct pci_bus *bus)
489{
490 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
491
492 return bc->nasid;
493}
494
488DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
489 pci_fixup_ioc3); 496 pci_fixup_ioc3);
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 000dc6af6cd3..180af89bcb1e 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -136,7 +136,9 @@ static int __init mace_init(void)
136 BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, 136 BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
137 "MACE PCI error", NULL)); 137 "MACE PCI error", NULL));
138 138
139 ioport_resource.end = mace_pci_io_resource.end; 139 iomem_resource = mace_pci_mem_resource;
140 ioport_resource = mace_pci_io_resource;
141
140 register_pci_controller(&mace_pci_controller); 142 register_pci_controller(&mace_pci_controller);
141 143
142 return 0; 144 return 0;
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index ae3cc4b254b5..88fb191ad2eb 100644
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -7,12 +7,8 @@
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h> 10#include <linux/pci.h>
12#include <linux/types.h> 11#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <asm/bootinfo.h> 12#include <asm/bootinfo.h>
17 13
18extern struct pci_ops nile4_pci_ops; 14extern struct pci_ops nile4_pci_ops;
@@ -20,14 +16,14 @@ extern struct pci_ops gt64120_pci_ops;
20static struct resource lasat_pci_mem_resource = { 16static struct resource lasat_pci_mem_resource = {
21 .name = "LASAT PCI MEM", 17 .name = "LASAT PCI MEM",
22 .start = 0x18000000, 18 .start = 0x18000000,
23 .end = 0x19FFFFFF, 19 .end = 0x19ffffff,
24 .flags = IORESOURCE_MEM, 20 .flags = IORESOURCE_MEM,
25}; 21};
26 22
27static struct resource lasat_pci_io_resource = { 23static struct resource lasat_pci_io_resource = {
28 .name = "LASAT PCI IO", 24 .name = "LASAT PCI IO",
29 .start = 0x1a000000, 25 .start = 0x1a000000,
30 .end = 0x1bFFFFFF, 26 .end = 0x1bffffff,
31 .flags = IORESOURCE_IO, 27 .flags = IORESOURCE_IO,
32}; 28};
33 29
@@ -38,23 +34,25 @@ static struct pci_controller lasat_pci_controller = {
38 34
39static int __init lasat_pci_setup(void) 35static int __init lasat_pci_setup(void)
40{ 36{
41 printk("PCI: starting\n"); 37 printk("PCI: starting\n");
42 38
43 switch (mips_machtype) { 39 switch (mips_machtype) {
44 case MACH_LASAT_100: 40 case MACH_LASAT_100:
45 lasat_pci_controller.pci_ops = &gt64120_pci_ops; 41 lasat_pci_controller.pci_ops = &gt64120_pci_ops;
46 break; 42 break;
47 case MACH_LASAT_200: 43 case MACH_LASAT_200:
48 lasat_pci_controller.pci_ops = &nile4_pci_ops; 44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
49 break; 45 break;
50 default: 46 default:
51 panic("pcibios_init: mips_machtype incorrect"); 47 panic("pcibios_init: mips_machtype incorrect");
52 } 48 }
53 49
54 register_pci_controller(&lasat_pci_controller); 50 register_pci_controller(&lasat_pci_controller);
55 return 0; 51
52 return 0;
56} 53}
57early_initcall(lasat_pci_setup); 54
55arch_initcall(lasat_pci_setup);
58 56
59#define LASATINT_ETH1 0 57#define LASATINT_ETH1 0
60#define LASATINT_ETH0 1 58#define LASATINT_ETH0 1
@@ -68,24 +66,22 @@ early_initcall(lasat_pci_setup);
68 66
69int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 67int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
70{ 68{
71 switch (slot) { 69 switch (slot) {
72 case 1: 70 case 1:
73 return LASATINT_PCIA; /* Expansion Module 0 */ 71 case 2:
74 case 2: 72 case 3:
75 return LASATINT_PCIB; /* Expansion Module 1 */ 73 return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
76 case 3: 74 case 4:
77 return LASATINT_PCIC; /* Expansion Module 2 */ 75 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
78 case 4: 76 case 5:
79 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ 77 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
80 case 5: 78 case 6:
81 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ 79 return LASATINT_HDC; /* IDE controller */
82 case 6: 80 default:
83 return LASATINT_HDC; /* IDE controller */ 81 return 0xff; /* Illegal */
84 default: 82 }
85 return 0xff; /* Illegal */
86 }
87 83
88 return -1; 84 return -1;
89} 85}
90 86
91/* Do platform specific device initialization at pci_enable_device() time */ 87/* Do platform specific device initialization at pci_enable_device() time */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index a8d499b0a36f..21402ffd7c98 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -127,15 +127,20 @@ static int __init pcibios_init(void)
127 if (!hose->iommu) 127 if (!hose->iommu)
128 PCI_DMA_BUS_IS_PHYS = 1; 128 PCI_DMA_BUS_IS_PHYS = 1;
129 129
130 if (hose->get_busno && pci_probe_only)
131 next_busno = (*hose->get_busno)();
132
130 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 133 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
131 hose->bus = bus; 134 hose->bus = bus;
132 hose->need_domain_info = need_domain_info; 135 hose->need_domain_info = need_domain_info;
133 next_busno = bus->subordinate + 1; 136 if (bus) {
134 /* Don't allow 8-bit bus number overflow inside the hose - 137 next_busno = bus->subordinate + 1;
135 reserve some space for bridges. */ 138 /* Don't allow 8-bit bus number overflow inside the hose -
136 if (next_busno > 224) { 139 reserve some space for bridges. */
137 next_busno = 0; 140 if (next_busno > 224) {
138 need_domain_info = 1; 141 next_busno = 0;
142 need_domain_info = 1;
143 }
139 } 144 }
140 continue; 145 continue;
141 146
@@ -164,7 +169,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
164 169
165 pci_read_config_word(dev, PCI_COMMAND, &cmd); 170 pci_read_config_word(dev, PCI_COMMAND, &cmd);
166 old_cmd = cmd; 171 old_cmd = cmd;
167 for(idx=0; idx<6; idx++) { 172 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
168 /* Only set up the requested stuff */ 173 /* Only set up the requested stuff */
169 if (!(mask & (1<<idx))) 174 if (!(mask & (1<<idx)))
170 continue; 175 continue;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-03 04:46:38 -0400