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-rw-r--r--arch/mips/pci/Makefile4
-rw-r--r--arch/mips/pci/fixup-cobalt.c61
-rw-r--r--arch/mips/pci/fixup-excite.c36
-rw-r--r--arch/mips/pci/fixup-fuloong2e.c5
-rw-r--r--arch/mips/pci/fixup-lemote2f.c160
-rw-r--r--arch/mips/pci/ops-bonito64.c7
-rw-r--r--arch/mips/pci/ops-loongson2.c216
-rw-r--r--arch/mips/pci/ops-pmcmsp.c2
-rw-r--r--arch/mips/pci/ops-titan-ht.c1
-rw-r--r--arch/mips/pci/pci-bcm47xx.c1
-rw-r--r--arch/mips/pci/pci-excite.c149
-rw-r--r--arch/mips/pci/pci-octeon.c6
-rw-r--r--arch/mips/pci/pci-sb1250.c3
-rw-r--r--arch/mips/pci/pci.c8
14 files changed, 450 insertions, 209 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 91bfe73a7f60..c9209ca6c8e7 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -22,13 +22,13 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
22# 22#
23# These are still pretty much in the old state, watch, go blind. 23# These are still pretty much in the old state, watch, go blind.
24# 24#
25obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
26obj-$(CONFIG_LASAT) += pci-lasat.o 25obj-$(CONFIG_LASAT) += pci-lasat.o
27obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 26obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 27obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 28obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 29obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o 30obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
31obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002dd..acacd1407c63 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -51,6 +51,67 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
51DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, 51DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
52 qube_raq_galileo_early_fixup); 52 qube_raq_galileo_early_fixup);
53 53
54static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
55 struct resource *res)
56{
57 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
58 unsigned long offset = hose->io_offset;
59 struct resource orig = *res;
60
61 if (!(res->flags & IORESOURCE_IO) ||
62 !(res->flags & IORESOURCE_PCI_FIXED))
63 return;
64
65 res->start -= offset;
66 res->end -= offset;
67 dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
68 &orig, res);
69}
70
71static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
72{
73 u32 class;
74 u8 progif;
75
76 /*
77 * If the IDE controller is in legacy mode, pci_setup_device() fills in
78 * the resources with the legacy addresses that normally appear on the
79 * PCI bus, just as if we had read them from a BAR.
80 *
81 * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
82 * will never appear on the PCI bus because it converts memory accesses
83 * in the PCI I/O region (which is never at address zero) into I/O port
84 * accesses with no address translation.
85 *
86 * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
87 * to physical address 0x100001f0 will become a PCI access to I/O port
88 * 0x100001f0. There's no way to generate an access to I/O port 0x1f0,
89 * but the VT82C586 IDE controller does respond at 0x100001f0 because
90 * it only decodes the low 24 bits of the address.
91 *
92 * When this quirk runs, the pci_dev resources should contain bus
93 * addresses, not Linux I/O port numbers, so convert legacy addresses
94 * like 0x1f0 to bus addresses like 0x100001f0. Later, we'll convert
95 * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
96 */
97 class = dev->class >> 8;
98 if (class != PCI_CLASS_STORAGE_IDE)
99 return;
100
101 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
102 if ((progif & 1) == 0) {
103 cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
104 cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
105 }
106 if ((progif & 4) == 0) {
107 cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
108 cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
109 }
110}
111
112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
113 cobalt_legacy_ide_fixup);
114
54static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) 115static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
55{ 116{
56 unsigned short cfgword; 117 unsigned short cfgword;
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
deleted file mode 100644
index cd64d9f177c4..000000000000
--- a/arch/mips/pci/fixup-excite.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <excite.h>
23
24int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
25{
26 if (pin == 0)
27 return -1;
28
29 return USB_IRQ; /* USB controller is the only PCI device */
30}
31
32/* Do platform specific device initialization at pci_enable_device() time */
33int pcibios_plat_dev_init(struct pci_dev *dev)
34{
35 return 0;
36}
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 0c4c7a81213f..4f6d8da07f93 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -13,7 +13,8 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <asm/mips-boards/bonito64.h> 16
17#include <loongson.h>
17 18
18/* South bridge slot number is set by the pci probe process */ 19/* South bridge slot number is set by the pci probe process */
19static u8 sb_slot = 5; 20static u8 sb_slot = 5;
@@ -35,7 +36,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
35 break; 36 break;
36 } 37 }
37 } else { 38 } else {
38 irq = BONITO_IRQ_BASE + 25 + pin; 39 irq = LOONGSON_IRQ_BASE + 25 + pin;
39 } 40 }
40 return irq; 41 return irq;
41 42
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
new file mode 100644
index 000000000000..4b9768d5d729
--- /dev/null
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -0,0 +1,160 @@
1/*
2 * Copyright (C) 2008 Lemote Technology
3 * Copyright (C) 2004 ICT CAS
4 * Author: Li xiaoyu, lixy@ict.ac.cn
5 *
6 * Copyright (C) 2007 Lemote, Inc.
7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/pci.h>
16
17#include <loongson.h>
18#include <cs5536/cs5536.h>
19#include <cs5536/cs5536_pci.h>
20
21/* PCI interrupt pins
22 *
23 * These should not be changed, or you should consider loongson2f interrupt
24 * register and your pci card dispatch
25 */
26
27#define PCIA 4
28#define PCIB 5
29#define PCIC 6
30#define PCID 7
31
32/* all the pci device has the PCIA pin, check the datasheet. */
33static char irq_tab[][5] __initdata = {
34 /* INTA INTB INTC INTD */
35 {0, 0, 0, 0, 0}, /* 11: Unused */
36 {0, 0, 0, 0, 0}, /* 12: Unused */
37 {0, 0, 0, 0, 0}, /* 13: Unused */
38 {0, 0, 0, 0, 0}, /* 14: Unused */
39 {0, 0, 0, 0, 0}, /* 15: Unused */
40 {0, 0, 0, 0, 0}, /* 16: Unused */
41 {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */
42 {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */
43 {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */
44 {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */
45 {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */
46 {0, 0, 0, 0, 0}, /* 22: Unused */
47 {0, 0, 0, 0, 0}, /* 23: Unused */
48 {0, 0, 0, 0, 0}, /* 24: Unused */
49 {0, 0, 0, 0, 0}, /* 25: Unused */
50 {0, 0, 0, 0, 0}, /* 26: Unused */
51 {0, 0, 0, 0, 0}, /* 27: Unused */
52};
53
54int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
55{
56 int virq;
57
58 if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
59 && (PCI_SLOT(dev->devfn) < 32)) {
60 virq = irq_tab[slot][pin];
61 printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
62 virq + LOONGSON_IRQ_BASE);
63 if (virq != 0)
64 return LOONGSON_IRQ_BASE + virq;
65 else
66 return 0;
67 } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */
68 switch (PCI_FUNC(dev->devfn)) {
69 case 2:
70 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
71 CS5536_IDE_INTR);
72 return CS5536_IDE_INTR; /* for IDE */
73 case 3:
74 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
75 CS5536_ACC_INTR);
76 return CS5536_ACC_INTR; /* for AUDIO */
77 case 4: /* for OHCI */
78 case 5: /* for EHCI */
79 case 6: /* for UDC */
80 case 7: /* for OTG */
81 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
82 CS5536_USB_INTR);
83 return CS5536_USB_INTR;
84 }
85 return dev->irq;
86 } else {
87 printk(KERN_INFO " strange pci slot number.\n");
88 return 0;
89 }
90}
91
92/* Do platform specific device initialization at pci_enable_device() time */
93int pcibios_plat_dev_init(struct pci_dev *dev)
94{
95 return 0;
96}
97
98/* CS5536 SPEC. fixup */
99static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
100{
101 /* the uart1 and uart2 interrupt in PIC is enabled as default */
102 pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
103 pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
104}
105
106static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
107{
108 /* setting the mutex pin as IDE function */
109 pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
110 CS5536_IDE_FLASH_SIGNATURE);
111}
112
113static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
114{
115 /* enable the AUDIO interrupt in PIC */
116 pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
117
118 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
119}
120
121static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
122{
123 /* enable the OHCI interrupt in PIC */
124 /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
125 pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
126}
127
128static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
129{
130 u32 hi, lo;
131
132 /* Serial short detect enable */
133 _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
134 _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 3), lo);
135
136 /* setting the USB2.0 micro frame length */
137 pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
138}
139
140static void __init loongson_nec_fixup(struct pci_dev *pdev)
141{
142 unsigned int val;
143
144 pci_read_config_dword(pdev, 0xe0, &val);
145 /* Only 2 port be used */
146 pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
147}
148
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
150 loongson_cs5536_isa_fixup);
151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
152 loongson_cs5536_ohci_fixup);
153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
154 loongson_cs5536_ehci_fixup);
155DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
156 loongson_cs5536_acc_fixup);
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
158 loongson_cs5536_ide_fixup);
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
160 loongson_nec_fixup);
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 54e55e7a2431..1b3e03f20c54 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,13 +29,8 @@
29#define PCI_ACCESS_READ 0 29#define PCI_ACCESS_READ 0
30#define PCI_ACCESS_WRITE 1 30#define PCI_ACCESS_WRITE 1
31 31
32#ifdef CONFIG_LEMOTE_FULOONG2E
33#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
34#define ID_SEL_BEGIN 11
35#else
36#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) 32#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
37#define ID_SEL_BEGIN 10 33#define ID_SEL_BEGIN 10
38#endif
39#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) 34#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
40 35
41 36
@@ -77,10 +72,8 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
77 addrp = CFG_SPACE_REG(addr & 0xffff); 72 addrp = CFG_SPACE_REG(addr & 0xffff);
78 if (access_type == PCI_ACCESS_WRITE) { 73 if (access_type == PCI_ACCESS_WRITE) {
79 writel(cpu_to_le32(*data), addrp); 74 writel(cpu_to_le32(*data), addrp);
80#ifndef CONFIG_LEMOTE_FULOONG2E
81 /* Wait till done */ 75 /* Wait till done */
82 while (BONITO_PCIMSTAT & 0xF); 76 while (BONITO_PCIMSTAT & 0xF);
83#endif
84 } else { 77 } else {
85 *data = le32_to_cpu(readl(addrp)); 78 *data = le32_to_cpu(readl(addrp));
86 } 79 }
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
new file mode 100644
index 000000000000..d657ee0bc131
--- /dev/null
+++ b/arch/mips/pci/ops-loongson2.c
@@ -0,0 +1,216 @@
1/*
2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 *
7 * Copyright (C) 2009 Lemote Inc.
8 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 */
14#include <linux/types.h>
15#include <linux/pci.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <loongson.h>
20
21#ifdef CONFIG_CS5536
22#include <cs5536/cs5536_pci.h>
23#include <cs5536/cs5536.h>
24#endif
25
26#define PCI_ACCESS_READ 0
27#define PCI_ACCESS_WRITE 1
28
29#define CFG_SPACE_REG(offset) \
30 (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
31#define ID_SEL_BEGIN 11
32#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
33
34
35static int loongson_pcibios_config_access(unsigned char access_type,
36 struct pci_bus *bus,
37 unsigned int devfn, int where,
38 u32 *data)
39{
40 u32 busnum = bus->number;
41 u32 addr, type;
42 u32 dummy;
43 void *addrp;
44 int device = PCI_SLOT(devfn);
45 int function = PCI_FUNC(devfn);
46 int reg = where & ~3;
47
48 if (busnum == 0) {
49 /* board-specific part,currently,only fuloong2f,yeeloong2f
50 * use CS5536, fuloong2e use via686b, gdium has no
51 * south bridge
52 */
53#ifdef CONFIG_CS5536
54 /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
55 * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
56 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
57 * will not go this branch, but the others. so, no calling dead
58 * loop here.
59 */
60 if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
61 switch (access_type) {
62 case PCI_ACCESS_READ:
63 *data = cs5536_pci_conf_read4(function, reg);
64 break;
65 case PCI_ACCESS_WRITE:
66 cs5536_pci_conf_write4(function, reg, *data);
67 break;
68 }
69 return 0;
70 }
71#endif
72 /* Type 0 configuration for onboard PCI bus */
73 if (device > MAX_DEV_NUM)
74 return -1;
75
76 addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
77 type = 0;
78 } else {
79 /* Type 1 configuration for offboard PCI bus */
80 addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
81 type = 0x10000;
82 }
83
84 /* Clear aborts */
85 LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
86 LOONGSON_PCICMD_MTABORT_CLR;
87
88 LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
89
90 /* Flush Bonito register block */
91 dummy = LOONGSON_PCIMAP_CFG;
92 mmiowb();
93
94 addrp = CFG_SPACE_REG(addr & 0xffff);
95 if (access_type == PCI_ACCESS_WRITE)
96 writel(cpu_to_le32(*data), addrp);
97 else
98 *data = le32_to_cpu(readl(addrp));
99
100 /* Detect Master/Target abort */
101 if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
102 LOONGSON_PCICMD_MTABORT_CLR)) {
103 /* Error occurred */
104
105 /* Clear bits */
106 LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
107 LOONGSON_PCICMD_MTABORT_CLR);
108
109 return -1;
110 }
111
112 return 0;
113
114}
115
116
117/*
118 * We can't address 8 and 16 bit words directly. Instead we have to
119 * read/write a 32bit word and mask/modify the data we actually want.
120 */
121static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
122 int where, int size, u32 *val)
123{
124 u32 data = 0;
125
126 if ((size == 2) && (where & 1))
127 return PCIBIOS_BAD_REGISTER_NUMBER;
128 else if ((size == 4) && (where & 3))
129 return PCIBIOS_BAD_REGISTER_NUMBER;
130
131 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
132 &data))
133 return -1;
134
135 if (size == 1)
136 *val = (data >> ((where & 3) << 3)) & 0xff;
137 else if (size == 2)
138 *val = (data >> ((where & 3) << 3)) & 0xffff;
139 else
140 *val = data;
141
142 return PCIBIOS_SUCCESSFUL;
143}
144
145static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
146 int where, int size, u32 val)
147{
148 u32 data = 0;
149
150 if ((size == 2) && (where & 1))
151 return PCIBIOS_BAD_REGISTER_NUMBER;
152 else if ((size == 4) && (where & 3))
153 return PCIBIOS_BAD_REGISTER_NUMBER;
154
155 if (size == 4)
156 data = val;
157 else {
158 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
159 where, &data))
160 return -1;
161
162 if (size == 1)
163 data = (data & ~(0xff << ((where & 3) << 3))) |
164 (val << ((where & 3) << 3));
165 else if (size == 2)
166 data = (data & ~(0xffff << ((where & 3) << 3))) |
167 (val << ((where & 3) << 3));
168 }
169
170 if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
171 &data))
172 return -1;
173
174 return PCIBIOS_SUCCESSFUL;
175}
176
177struct pci_ops loongson_pci_ops = {
178 .read = loongson_pcibios_read,
179 .write = loongson_pcibios_write
180};
181
182#ifdef CONFIG_CS5536
183DEFINE_RAW_SPINLOCK(msr_lock);
184
185void _rdmsr(u32 msr, u32 *hi, u32 *lo)
186{
187 struct pci_bus bus = {
188 .number = PCI_BUS_CS5536
189 };
190 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
191 unsigned long flags;
192
193 raw_spin_lock_irqsave(&msr_lock, flags);
194 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
195 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
196 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
197 raw_spin_unlock_irqrestore(&msr_lock, flags);
198}
199EXPORT_SYMBOL(_rdmsr);
200
201void _wrmsr(u32 msr, u32 hi, u32 lo)
202{
203 struct pci_bus bus = {
204 .number = PCI_BUS_CS5536
205 };
206 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
207 unsigned long flags;
208
209 raw_spin_lock_irqsave(&msr_lock, flags);
210 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
211 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
212 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
213 raw_spin_unlock_irqrestore(&msr_lock, flags);
214}
215EXPORT_SYMBOL(_wrmsr);
216#endif
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 32548b5d68d6..04b31478a6d7 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -206,7 +206,7 @@ static void pci_proc_init(void)
206} 206}
207#endif /* CONFIG_PROC_FS && PCI_COUNTERS */ 207#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
208 208
209DEFINE_SPINLOCK(bpci_lock); 209static DEFINE_SPINLOCK(bpci_lock);
210 210
211/***************************************************************************** 211/*****************************************************************************
212 * 212 *
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
index 46c636c27e06..749c1922d420 100644
--- a/arch/mips/pci/ops-titan-ht.c
+++ b/arch/mips/pci/ops-titan-ht.c
@@ -26,7 +26,6 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/slab.h>
30#include <linux/delay.h> 29#include <linux/delay.h>
31#include <asm/io.h> 30#include <asm/io.h>
32 31
diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c
index bea9b6cdfdbf..455f8e50a007 100644
--- a/arch/mips/pci/pci-bcm47xx.c
+++ b/arch/mips/pci/pci-bcm47xx.c
@@ -57,4 +57,3 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
57 dev->irq = res; 57 dev->irq = res;
58 return 0; 58 return 0;
59} 59}
60
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
deleted file mode 100644
index 8a56876afcc6..000000000000
--- a/arch/mips/pci/pci-excite.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/bitops.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28
29extern struct pci_ops titan_pci_ops;
30
31
32static struct resource
33 mem_resource = {
34 .name = "PCI memory",
35 .start = EXCITE_PHYS_PCI_MEM,
36 .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
37 .flags = IORESOURCE_MEM
38 },
39 io_resource = {
40 .name = "PCI I/O",
41 .start = EXCITE_PHYS_PCI_IO,
42 .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
43 .flags = IORESOURCE_IO
44 };
45
46
47static struct pci_controller bx_controller = {
48 .pci_ops = &titan_pci_ops,
49 .mem_resource = &mem_resource,
50 .mem_offset = 0x00000000UL,
51 .io_resource = &io_resource,
52 .io_offset = 0x00000000UL
53};
54
55
56static char
57 iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
58 modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
59
60#define RM9000x2_OCD_HTSC 0x0604
61#define RM9000x2_OCD_HTBHL 0x060c
62#define RM9000x2_OCD_PCIHRST 0x078c
63
64#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
65#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
66
67#define PCISC_FB2B 0x00000200
68#define PCISC_MWICG 0x00000010
69#define PCISC_EMC 0x00000004
70#define PCISC_ERMA 0x00000002
71
72
73
74static int __init basler_excite_pci_setup(void)
75{
76 const unsigned int fullbars = memsize / (256 << 20);
77 unsigned int i;
78
79 /* Check modebits to see if PCI is really enabled. */
80 if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
81 panic(modebits_no_pci);
82
83 if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
84 "Memory-mapped PCI I/O page"))
85 panic(iopage_failed);
86
87 /* Enable PCI 0 as master for config cycles */
88 ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
89
90
91 /* Set up latency timer */
92 ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
93
94 /* Setup host IO and Memory space */
95 ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
96 ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
97 ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
98 ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
99
100 /* Set up PCI BARs to map all installed memory */
101 for (i = 0; i < 6; i++) {
102 const unsigned int bar = 0x610 + i * 4;
103
104 if (i < fullbars) {
105 ocd_writel(0x10000000 * i, bar);
106 ocd_writel(0x01000000 * i, bar + 0x140);
107 ocd_writel(0x0ffff029, bar + 0x100);
108 continue;
109 }
110
111 if (i == fullbars) {
112 int o;
113 u32 mask;
114
115 const unsigned long rem = memsize - i * 0x10000000;
116 if (!rem) {
117 ocd_writel(0x00000000, bar + 0x100);
118 continue;
119 }
120
121 o = ffs(rem) - 1;
122 if (rem & ~(0x1 << o))
123 o++;
124 mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
125 ocd_writel(0x10000000 * i, bar);
126 ocd_writel(0x01000000 * i, bar + 0x140);
127 ocd_writel(0x00000029 | mask, bar + 0x100);
128 continue;
129 }
130
131 ocd_writel(0x00000000, bar + 0x100);
132 }
133
134 /* Finally, enable the PCI interrupt */
135#if USB_IRQ > 7
136 set_c0_intcontrol(1 << USB_IRQ);
137#else
138 set_c0_status(1 << (USB_IRQ + 8));
139#endif
140
141 ioport_resource.start = EXCITE_PHYS_PCI_IO;
142 ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
143 set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
144 register_pci_controller(&bx_controller);
145 return 0;
146}
147
148
149arch_initcall(basler_excite_pci_setup);
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 9cb0c807f564..d248b707eff3 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -209,16 +209,14 @@ const char *octeon_get_pci_interrupts(void)
209 case CVMX_BOARD_TYPE_NAO38: 209 case CVMX_BOARD_TYPE_NAO38:
210 /* This is really the NAC38 */ 210 /* This is really the NAC38 */
211 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; 211 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
212 case CVMX_BOARD_TYPE_THUNDER:
213 return "";
214 case CVMX_BOARD_TYPE_EBH3000:
215 return "";
216 case CVMX_BOARD_TYPE_EBH3100: 212 case CVMX_BOARD_TYPE_EBH3100:
217 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 213 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
218 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 214 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
219 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; 215 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
220 case CVMX_BOARD_TYPE_BBGW_REF: 216 case CVMX_BOARD_TYPE_BBGW_REF:
221 return "AABCD"; 217 return "AABCD";
218 case CVMX_BOARD_TYPE_THUNDER:
219 case CVMX_BOARD_TYPE_EBH3000:
222 default: 220 default:
223 return ""; 221 return "";
224 } 222 }
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index ada24e6f951f..1711e8e101bc 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -37,6 +37,7 @@
37#include <linux/mm.h> 37#include <linux/mm.h>
38#include <linux/console.h> 38#include <linux/console.h>
39#include <linux/tty.h> 39#include <linux/tty.h>
40#include <linux/vt.h>
40 41
41#include <asm/io.h> 42#include <asm/io.h>
42 43
@@ -254,7 +255,7 @@ static int __init sb1250_pcibios_init(void)
254 * XXX ehs: Should this happen in PCI Device mode? 255 * XXX ehs: Should this happen in PCI Device mode?
255 */ 256 */
256 io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024); 257 io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
257 sb1250_controller.io_map_base = io_map_base; 258 sb1250_controller.io_map_base = (unsigned long)io_map_base;
258 set_io_port_base((unsigned long)io_map_base); 259 set_io_port_base((unsigned long)io_map_base);
259 260
260#ifdef CONFIG_SIBYTE_HAS_LDT 261#ifdef CONFIG_SIBYTE_HAS_LDT
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 9a11c2226891..38bc28005b4a 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -49,8 +49,8 @@ static int pci_initialized;
49 * but we want to try to avoid allocating at 0x2900-0x2bff 49 * but we want to try to avoid allocating at 0x2900-0x2bff
50 * which might have be mirrored at 0x0100-0x03ff.. 50 * which might have be mirrored at 0x0100-0x03ff..
51 */ 51 */
52void 52resource_size_t
53pcibios_align_resource(void *data, struct resource *res, 53pcibios_align_resource(void *data, const struct resource *res,
54 resource_size_t size, resource_size_t align) 54 resource_size_t size, resource_size_t align)
55{ 55{
56 struct pci_dev *dev = data; 56 struct pci_dev *dev = data;
@@ -73,7 +73,7 @@ pcibios_align_resource(void *data, struct resource *res,
73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
74 } 74 }
75 75
76 res->start = start; 76 return start;
77} 77}
78 78
79static void __devinit pcibios_scanbus(struct pci_controller *hose) 79static void __devinit pcibios_scanbus(struct pci_controller *hose)
@@ -251,8 +251,6 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev,
251 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 251 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
252 if (!dev->resource[i].start) 252 if (!dev->resource[i].start)
253 continue; 253 continue;
254 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
255 continue;
256 if (dev->resource[i].flags & IORESOURCE_IO) 254 if (dev->resource[i].flags & IORESOURCE_IO)
257 offset = hose->io_offset; 255 offset = hose->io_offset;
258 else if (dev->resource[i].flags & IORESOURCE_MEM) 256 else if (dev->resource[i].flags & IORESOURCE_MEM)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-17 19:46:47 -0400