5 files changed, 75 insertions, 53 deletions

diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 4aa20280613e..fd6203f14f1f 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -3,8 +3,8 @@
 #
 
 obj-y                           += cache.o dma-default.o extable.o fault.o \
-                                   gup.o init.o mmap.o page.o tlbex.o \
-                                   tlbex-fault.o uasm.o
+                                   gup.o init.o mmap.o page.o page-funcs.o \
+                                   tlbex.o tlbex-fault.o uasm.o
 
 obj-$(CONFIG_32BIT)             += ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)             += pgtable-64.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5109be96d98d..f092c265dc63 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
                         c->icache.linesz = 2 << lsize;
                 else
                         c->icache.linesz = lsize;
-                c->icache.sets = 64 << ((config1 >> 22) & 7);
+                c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 
                 icache_size = c->icache.sets *
@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
                         c->dcache.linesz = 2 << lsize;
                 else
                         c->dcache.linesz= lsize;
-                c->dcache.sets = 64 << ((config1 >> 13) & 7);
+                c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
                 dcache_size = c->dcache.sets *
@@ -1051,6 +1051,7 @@ static void __cpuinit probe_pcache(void)
         case CPU_R14000:
                 break;
 
+        case CPU_M14KC:
         case CPU_24K:
         case CPU_34K:
         case CPU_74K:
diff --git a/arch/mips/mm/page-funcs.S b/arch/mips/mm/page-funcs.S
new file mode 100644
index 000000000000..48a6b38ff13e
--- /dev/null
+++ b/arch/mips/mm/page-funcs.S
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Micro-assembler generated clear_page/copy_page functions.
+ *
+ * Copyright (C) 2012  MIPS Technologies, Inc.
+ * Copyright (C) 2012  Ralf Baechle <ralf@linux-mips.org>
+ */
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
+#define cpu_clear_page_function_name    clear_page_cpu
+#define cpu_copy_page_function_name     copy_page_cpu
+#else
+#define cpu_clear_page_function_name    clear_page
+#define cpu_copy_page_function_name     copy_page
+#endif
+
+/*
+ * Maximum sizes:
+ *
+ * R4000 128 bytes S-cache:             0x058 bytes
+ * R4600 v1.7:                          0x05c bytes
+ * R4600 v2.0:                          0x060 bytes
+ * With prefetching, 16 word strides    0x120 bytes
+ */
+EXPORT(__clear_page_start)
+LEAF(cpu_clear_page_function_name)
+1:      j       1b              /* Dummy, will be replaced. */
+        .space 288
+END(cpu_clear_page_function_name)
+EXPORT(__clear_page_end)
+
+/*
+ * Maximum sizes:
+ *
+ * R4000 128 bytes S-cache:             0x11c bytes
+ * R4600 v1.7:                          0x080 bytes
+ * R4600 v2.0:                          0x07c bytes
+ * With prefetching, 16 word strides    0x540 bytes
+ */
+EXPORT(__copy_page_start)
+LEAF(cpu_copy_page_function_name)
+1:      j       1b              /* Dummy, will be replaced. */
+        .space 1344
+END(cpu_copy_page_function_name)
+EXPORT(__copy_page_end)
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index cc0b626858b3..98f530e18216 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2007  Maciej W. Rozycki
  * Copyright (C) 2008  Thiemo Seufer
+ * Copyright (C) 2012  MIPS Technologies, Inc.
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -71,45 +72,6 @@ static struct uasm_reloc __cpuinitdata relocs[5];
 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 
-/*
- * Maximum sizes:
- *
- * R4000 128 bytes S-cache:             0x058 bytes
- * R4600 v1.7:                          0x05c bytes
- * R4600 v2.0:                          0x060 bytes
- * With prefetching, 16 word strides    0x120 bytes
- */
-
-static u32 clear_page_array[0x120 / 4];
-
-#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
-void clear_page_cpu(void *page) __attribute__((alias("clear_page_array")));
-#else
-void clear_page(void *page) __attribute__((alias("clear_page_array")));
-#endif
-
-EXPORT_SYMBOL(clear_page);
-
-/*
- * Maximum sizes:
- *
- * R4000 128 bytes S-cache:             0x11c bytes
- * R4600 v1.7:                          0x080 bytes
- * R4600 v2.0:                          0x07c bytes
- * With prefetching, 16 word strides    0x540 bytes
- */
-static u32 copy_page_array[0x540 / 4];
-
-#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
-void
-copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array")));
-#else
-void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
-#endif
-
-EXPORT_SYMBOL(copy_page);
-
-
 static int pref_bias_clear_store __cpuinitdata;
 static int pref_bias_copy_load __cpuinitdata;
 static int pref_bias_copy_store __cpuinitdata;
@@ -282,10 +244,15 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
                 }
 }
 
+extern u32 __clear_page_start;
+extern u32 __clear_page_end;
+extern u32 __copy_page_start;
+extern u32 __copy_page_end;
+
 void __cpuinit build_clear_page(void)
 {
         int off;
-        u32 *buf = (u32 *)&clear_page_array;
+        u32 *buf = &__clear_page_start;
         struct uasm_label *l = labels;
         struct uasm_reloc *r = relocs;
         int i;
@@ -356,17 +323,17 @@ void __cpuinit build_clear_page(void)
         uasm_i_jr(&buf, RA);
         uasm_i_nop(&buf);
 
-        BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array));
+        BUG_ON(buf > &__clear_page_end);
 
         uasm_resolve_relocs(relocs, labels);
 
         pr_debug("Synthesized clear page handler (%u instructions).\n",
-                 (u32)(buf - clear_page_array));
+                 (u32)(buf - &__clear_page_start));
 
         pr_debug("\t.set push\n");
         pr_debug("\t.set noreorder\n");
-        for (i = 0; i < (buf - clear_page_array); i++)
-                pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
+        for (i = 0; i < (buf - &__clear_page_start); i++)
+                pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
         pr_debug("\t.set pop\n");
 }
 
@@ -427,7 +394,7 @@ static inline void build_copy_store_pref(u32 **buf, int off)
 void __cpuinit build_copy_page(void)
 {
         int off;
-        u32 *buf = (u32 *)&copy_page_array;
+        u32 *buf = &__copy_page_start;
         struct uasm_label *l = labels;
         struct uasm_reloc *r = relocs;
         int i;
@@ -595,21 +562,23 @@ void __cpuinit build_copy_page(void)
         uasm_i_jr(&buf, RA);
         uasm_i_nop(&buf);
 
-        BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array));
+        BUG_ON(buf > &__copy_page_end);
 
         uasm_resolve_relocs(relocs, labels);
 
         pr_debug("Synthesized copy page handler (%u instructions).\n",
-                 (u32)(buf - copy_page_array));
+                 (u32)(buf - &__copy_page_start));
 
         pr_debug("\t.set push\n");
         pr_debug("\t.set noreorder\n");
-        for (i = 0; i < (buf - copy_page_array); i++)
-                pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
+        for (i = 0; i < (buf - &__copy_page_start); i++)
+                pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
         pr_debug("\t.set pop\n");
 }
 
 #ifdef CONFIG_SIBYTE_DMA_PAGEOPS
+extern void clear_page_cpu(void *page);
+extern void copy_page_cpu(void *to, void *from);
 
 /*
  * Pad descriptors to cacheline, since each is exclusively owned by a
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0bc485b3cd60..03eb0ef91580 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -9,6 +9,7 @@
  * Copyright (C) 2005, 2007, 2008, 2009  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2008, 2009 Cavium Networks, Inc.
+ * Copyright (C) 2011  MIPS Technologies, Inc.
  *
  * ... and the days got worse and worse and now you see
  * I've gone completly out of my mind.
@@ -494,6 +495,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_R14000:
         case CPU_4KC:
         case CPU_4KEC:
+        case CPU_M14KC:
         case CPU_SB1:
         case CPU_SB1A:
         case CPU_4KSC: