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-rw-r--r--arch/mips/mm/c-octeon.c4
-rw-r--r--arch/mips/mm/cache.c4
-rw-r--r--arch/mips/mm/cerr-sb1.c7
-rw-r--r--arch/mips/mm/dma-default.c7
-rw-r--r--arch/mips/mm/init.c10
-rw-r--r--arch/mips/mm/tlbex.c36
-rw-r--r--arch/mips/mm/uasm.c16
-rw-r--r--arch/mips/mm/uasm.h7
8 files changed, 66 insertions, 25 deletions
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 94e05e5733c1..e06f1af760a7 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -174,7 +174,7 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
174 * Probe Octeon's caches 174 * Probe Octeon's caches
175 * 175 *
176 */ 176 */
177static void __devinit probe_octeon(void) 177static void __cpuinit probe_octeon(void)
178{ 178{
179 unsigned long icache_size; 179 unsigned long icache_size;
180 unsigned long dcache_size; 180 unsigned long dcache_size;
@@ -235,7 +235,7 @@ static void __devinit probe_octeon(void)
235 * Setup the Octeon cache flush routines 235 * Setup the Octeon cache flush routines
236 * 236 *
237 */ 237 */
238void __devinit octeon_cache_init(void) 238void __cpuinit octeon_cache_init(void)
239{ 239{
240 extern unsigned long ebase; 240 extern unsigned long ebase;
241 extern char except_vec2_octeon; 241 extern char except_vec2_octeon;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 694d51f523d1..e716cafc346d 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -155,7 +155,7 @@ static inline void setup_protection_map(void)
155 protection_map[15] = PAGE_SHARED; 155 protection_map[15] = PAGE_SHARED;
156} 156}
157 157
158void __devinit cpu_cache_init(void) 158void __cpuinit cpu_cache_init(void)
159{ 159{
160 if (cpu_has_3k_cache) { 160 if (cpu_has_3k_cache) {
161 extern void __weak r3k_cache_init(void); 161 extern void __weak r3k_cache_init(void);
@@ -194,7 +194,7 @@ void __devinit cpu_cache_init(void)
194 194
195int __weak __uncached_access(struct file *file, unsigned long addr) 195int __weak __uncached_access(struct file *file, unsigned long addr)
196{ 196{
197 if (file->f_flags & O_SYNC) 197 if (file->f_flags & O_DSYNC)
198 return 1; 198 return 1;
199 199
200 return addr >= __pa(high_memory); 200 return addr >= __pa(high_memory);
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 1bd1f18ac23c..3571090ba178 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -567,13 +567,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
567 datalo = ((unsigned long long)datalohi << 32) | datalolo; 567 datalo = ((unsigned long long)datalohi << 32) | datalolo;
568 ecc = dc_ecc(datalo); 568 ecc = dc_ecc(datalo);
569 if (ecc != datahi) { 569 if (ecc != datahi) {
570 int bits = 0; 570 int bits;
571 bad_ecc |= 1 << (3-offset); 571 bad_ecc |= 1 << (3-offset);
572 ecc ^= datahi; 572 ecc ^= datahi;
573 while (ecc) { 573 bits = hweight8(ecc);
574 if (ecc & 1) bits++;
575 ecc >>= 1;
576 }
577 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; 574 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
578 } 575 }
579 printk(" %02X-%016llX", datahi, datalo); 576 printk(" %02X-%016llX", datahi, datalo);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 7e48e76148aa..9367e33fbd18 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -90,6 +90,9 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
90{ 90{
91 void *ret; 91 void *ret;
92 92
93 if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
94 return ret;
95
93 gfp = massage_gfp_flags(dev, gfp); 96 gfp = massage_gfp_flags(dev, gfp);
94 97
95 ret = (void *) __get_free_pages(gfp, get_order(size)); 98 ret = (void *) __get_free_pages(gfp, get_order(size));
@@ -122,6 +125,10 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
122 dma_addr_t dma_handle) 125 dma_addr_t dma_handle)
123{ 126{
124 unsigned long addr = (unsigned long) vaddr; 127 unsigned long addr = (unsigned long) vaddr;
128 int order = get_order(size);
129
130 if (dma_release_from_coherent(dev, order, vaddr))
131 return;
125 132
126 plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); 133 plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
127 134
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 4d72aabe8352..dee564aad23a 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -27,6 +27,7 @@
27#include <linux/swap.h> 27#include <linux/swap.h>
28#include <linux/proc_fs.h> 28#include <linux/proc_fs.h>
29#include <linux/pfn.h> 29#include <linux/pfn.h>
30#include <linux/hardirq.h>
30 31
31#include <asm/asm-offsets.h> 32#include <asm/asm-offsets.h>
32#include <asm/bootinfo.h> 33#include <asm/bootinfo.h>
@@ -132,7 +133,10 @@ void *kmap_coherent(struct page *page, unsigned long addr)
132 inc_preempt_count(); 133 inc_preempt_count();
133 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); 134 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
134#ifdef CONFIG_MIPS_MT_SMTC 135#ifdef CONFIG_MIPS_MT_SMTC
135 idx += FIX_N_COLOURS * smp_processor_id(); 136 idx += FIX_N_COLOURS * smp_processor_id() +
137 (in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0);
138#else
139 idx += in_interrupt() ? FIX_N_COLOURS : 0;
136#endif 140#endif
137 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 141 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
138 pte = mk_pte(page, PAGE_KERNEL); 142 pte = mk_pte(page, PAGE_KERNEL);
@@ -420,7 +424,7 @@ void __init mem_init(void)
420 reservedpages << (PAGE_SHIFT-10), 424 reservedpages << (PAGE_SHIFT-10),
421 datasize >> 10, 425 datasize >> 10,
422 initsize >> 10, 426 initsize >> 10,
423 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); 427 totalhigh_pages << (PAGE_SHIFT-10));
424} 428}
425#endif /* !CONFIG_NEED_MULTIPLE_NODES */ 429#endif /* !CONFIG_NEED_MULTIPLE_NODES */
426 430
@@ -458,7 +462,9 @@ void __init_refok free_initmem(void)
458 __pa_symbol(&__init_end)); 462 __pa_symbol(&__init_end));
459} 463}
460 464
465#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
461unsigned long pgd_current[NR_CPUS]; 466unsigned long pgd_current[NR_CPUS];
467#endif
462/* 468/*
463 * On 64-bit we've got three-level pagetables with a slightly 469 * On 64-bit we've got three-level pagetables with a slightly
464 * different layout ... 470 * different layout ...
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index bb1719a55d22..badcf5e8d695 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -73,9 +73,6 @@ static int __cpuinit m4kc_tlbp_war(void)
73enum label_id { 73enum label_id {
74 label_second_part = 1, 74 label_second_part = 1,
75 label_leave, 75 label_leave,
76#ifdef MODULE_START
77 label_module_alloc,
78#endif
79 label_vmalloc, 76 label_vmalloc,
80 label_vmalloc_done, 77 label_vmalloc_done,
81 label_tlbw_hazard, 78 label_tlbw_hazard,
@@ -92,9 +89,6 @@ enum label_id {
92 89
93UASM_L_LA(_second_part) 90UASM_L_LA(_second_part)
94UASM_L_LA(_leave) 91UASM_L_LA(_leave)
95#ifdef MODULE_START
96UASM_L_LA(_module_alloc)
97#endif
98UASM_L_LA(_vmalloc) 92UASM_L_LA(_vmalloc)
99UASM_L_LA(_vmalloc_done) 93UASM_L_LA(_vmalloc_done)
100UASM_L_LA(_tlbw_hazard) 94UASM_L_LA(_tlbw_hazard)
@@ -160,6 +154,12 @@ static u32 tlb_handler[128] __cpuinitdata;
160static struct uasm_label labels[128] __cpuinitdata; 154static struct uasm_label labels[128] __cpuinitdata;
161static struct uasm_reloc relocs[128] __cpuinitdata; 155static struct uasm_reloc relocs[128] __cpuinitdata;
162 156
157#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
158/*
159 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
160 * we cannot do r3000 under these circumstances.
161 */
162
163/* 163/*
164 * The R3000 TLB handler is simple. 164 * The R3000 TLB handler is simple.
165 */ 165 */
@@ -199,6 +199,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
199 199
200 dump_handler((u32 *)ebase, 32); 200 dump_handler((u32 *)ebase, 32);
201} 201}
202#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
202 203
203/* 204/*
204 * The R4000 TLB handler is much more complicated. We have two 205 * The R4000 TLB handler is much more complicated. We have two
@@ -497,8 +498,9 @@ static void __cpuinit
497build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 498build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
498 unsigned int tmp, unsigned int ptr) 499 unsigned int tmp, unsigned int ptr)
499{ 500{
501#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
500 long pgdc = (long)pgd_current; 502 long pgdc = (long)pgd_current;
501 503#endif
502 /* 504 /*
503 * The vmalloc handling is not in the hotpath. 505 * The vmalloc handling is not in the hotpath.
504 */ 506 */
@@ -506,7 +508,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
506 uasm_il_bltz(p, r, tmp, label_vmalloc); 508 uasm_il_bltz(p, r, tmp, label_vmalloc);
507 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 509 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
508 510
509#ifdef CONFIG_SMP 511#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
512 /*
513 * &pgd << 11 stored in CONTEXT [23..63].
514 */
515 UASM_i_MFC0(p, ptr, C0_CONTEXT);
516 uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
517 uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
518 uasm_i_drotr(p, ptr, ptr, 11);
519#elif defined(CONFIG_SMP)
510# ifdef CONFIG_MIPS_MT_SMTC 520# ifdef CONFIG_MIPS_MT_SMTC
511 /* 521 /*
512 * SMTC uses TCBind value as "CPU" index 522 * SMTC uses TCBind value as "CPU" index
@@ -520,7 +530,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
520 */ 530 */
521 uasm_i_dmfc0(p, ptr, C0_CONTEXT); 531 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
522 uasm_i_dsrl(p, ptr, ptr, 23); 532 uasm_i_dsrl(p, ptr, ptr, 23);
523#endif 533# endif
524 UASM_i_LA_mostly(p, tmp, pgdc); 534 UASM_i_LA_mostly(p, tmp, pgdc);
525 uasm_i_daddu(p, ptr, ptr, tmp); 535 uasm_i_daddu(p, ptr, ptr, tmp);
526 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 536 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -802,8 +812,6 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
802 } else { 812 } else {
803#if defined(CONFIG_HUGETLB_PAGE) 813#if defined(CONFIG_HUGETLB_PAGE)
804 const enum label_id ls = label_tlb_huge_update; 814 const enum label_id ls = label_tlb_huge_update;
805#elif defined(MODULE_START)
806 const enum label_id ls = label_module_alloc;
807#else 815#else
808 const enum label_id ls = label_vmalloc; 816 const enum label_id ls = label_vmalloc;
809#endif 817#endif
@@ -1033,6 +1041,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1033 iPTE_LW(p, pte, ptr); 1041 iPTE_LW(p, pte, ptr);
1034} 1042}
1035 1043
1044#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1036/* 1045/*
1037 * R3000 style TLB load/store/modify handlers. 1046 * R3000 style TLB load/store/modify handlers.
1038 */ 1047 */
@@ -1184,6 +1193,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
1184 1193
1185 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1194 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1186} 1195}
1196#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1187 1197
1188/* 1198/*
1189 * R4000 style TLB load/store/modify handlers. 1199 * R4000 style TLB load/store/modify handlers.
@@ -1400,6 +1410,7 @@ void __cpuinit build_tlb_refill_handler(void)
1400 case CPU_TX3912: 1410 case CPU_TX3912:
1401 case CPU_TX3922: 1411 case CPU_TX3922:
1402 case CPU_TX3927: 1412 case CPU_TX3927:
1413#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1403 build_r3000_tlb_refill_handler(); 1414 build_r3000_tlb_refill_handler();
1404 if (!run_once) { 1415 if (!run_once) {
1405 build_r3000_tlb_load_handler(); 1416 build_r3000_tlb_load_handler();
@@ -1407,6 +1418,9 @@ void __cpuinit build_tlb_refill_handler(void)
1407 build_r3000_tlb_modify_handler(); 1418 build_r3000_tlb_modify_handler();
1408 run_once++; 1419 run_once++;
1409 } 1420 }
1421#else
1422 panic("No R3000 TLB refill handler");
1423#endif
1410 break; 1424 break;
1411 1425
1412 case CPU_R6000: 1426 case CPU_R6000:
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index f467199676a8..0a165c5179a1 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -60,11 +60,11 @@ enum opcode {
60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
63 insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, 63 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
64 insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, 64 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, 65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, 66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori 67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
68}; 68};
69 69
70struct insn { 70struct insn {
@@ -104,6 +104,7 @@ static struct insn insn_table[] __cpuinitdata = {
104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, 104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, 105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
107 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
107 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 108 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
108 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 109 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
109 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, 110 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
@@ -132,6 +133,7 @@ static struct insn insn_table[] __cpuinitdata = {
132 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 133 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
133 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, 134 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
134 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 135 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
136 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
135 { insn_invalid, 0, 0 } 137 { insn_invalid, 0, 0 }
136}; 138};
137 139
@@ -304,6 +306,12 @@ Ip_u2u1s3(op) \
304 build_insn(buf, insn##op, b, a, c); \ 306 build_insn(buf, insn##op, b, a, c); \
305} 307}
306 308
309#define I_u2u1msbu3(op) \
310Ip_u2u1msbu3(op) \
311{ \
312 build_insn(buf, insn##op, b, a, c+d-1, c); \
313}
314
307#define I_u1u2(op) \ 315#define I_u1u2(op) \
308Ip_u1u2(op) \ 316Ip_u1u2(op) \
309{ \ 317{ \
@@ -349,6 +357,7 @@ I_u2u1u3(_dsll32)
349I_u2u1u3(_dsra) 357I_u2u1u3(_dsra)
350I_u2u1u3(_dsrl) 358I_u2u1u3(_dsrl)
351I_u2u1u3(_dsrl32) 359I_u2u1u3(_dsrl32)
360I_u2u1u3(_drotr)
352I_u3u1u2(_dsubu) 361I_u3u1u2(_dsubu)
353I_0(_eret) 362I_0(_eret)
354I_u1(_j) 363I_u1(_j)
@@ -377,6 +386,7 @@ I_0(_tlbwi)
377I_0(_tlbwr) 386I_0(_tlbwr)
378I_u3u1u2(_xor) 387I_u3u1u2(_xor)
379I_u2u1u3(_xori) 388I_u2u1u3(_xori)
389I_u2u1msbu3(_dins);
380 390
381/* Handle labels. */ 391/* Handle labels. */
382void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 392void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
index c6d1e3dd82d4..3d153edaa51e 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/mm/uasm.h
@@ -34,6 +34,11 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
34void __cpuinit \ 34void __cpuinit \
35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
36 36
37#define Ip_u2u1msbu3(op) \
38void __cpuinit \
39uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
40 unsigned int d)
41
37#define Ip_u1u2(op) \ 42#define Ip_u1u2(op) \
38void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) 43void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
39 44
@@ -65,6 +70,7 @@ Ip_u2u1u3(_dsll32);
65Ip_u2u1u3(_dsra); 70Ip_u2u1u3(_dsra);
66Ip_u2u1u3(_dsrl); 71Ip_u2u1u3(_dsrl);
67Ip_u2u1u3(_dsrl32); 72Ip_u2u1u3(_dsrl32);
73Ip_u2u1u3(_drotr);
68Ip_u3u1u2(_dsubu); 74Ip_u3u1u2(_dsubu);
69Ip_0(_eret); 75Ip_0(_eret);
70Ip_u1(_j); 76Ip_u1(_j);
@@ -93,6 +99,7 @@ Ip_0(_tlbwi);
93Ip_0(_tlbwr); 99Ip_0(_tlbwr);
94Ip_u3u1u2(_xor); 100Ip_u3u1u2(_xor);
95Ip_u2u1u3(_xori); 101Ip_u2u1u3(_xori);
102Ip_u2u1msbu3(_dins);
96 103
97/* Handle labels. */ 104/* Handle labels. */
98struct uasm_label { 105struct uasm_label {