2 files changed, 4 insertions, 8 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ecca559b8d7b..2078915eacb9 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
                 return;
 
         default:
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
 #ifdef CONFIG_MIPS_CPU_SCACHE
                         if (mips_sc_init ()) {
                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 93d937b4b1ba..df96da7e939b 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
         c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
 
         /* Ignore anything but MIPSxx processors */
-        if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
-            c->isa_level != MIPS_CPU_ISA_M32R2 &&
-            c->isa_level != MIPS_CPU_ISA_M64R1 &&
-            c->isa_level != MIPS_CPU_ISA_M64R2)
+        if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                              MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
                 return 0;
 
         /* Does this MIPS32/MIPS64 CPU have a config2 register? */