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-rw-r--r--arch/mips/mm/cex-sb1.S2
-rw-r--r--arch/mips/mm/tlbex.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index 2d08268bb705..89c412bc4b64 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -79,7 +79,7 @@ LEAF(except_vec2_sb1)
79recovered_dcache: 79recovered_dcache:
80 /* 80 /*
81 * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA). 81 * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
82 * Ought to log the occurence of this recovered dcache error. 82 * Ought to log the occurrence of this recovered dcache error.
83 */ 83 */
84 b recovered 84 b recovered
85 mtc0 $0,C0_CERR_D 85 mtc0 $0,C0_CERR_D
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 04f9e17db9d0..5ef294fbb6e7 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -352,7 +352,7 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
352 352
353/* 353/*
354 * Write random or indexed TLB entry, and care about the hazards from 354 * Write random or indexed TLB entry, and care about the hazards from
355 * the preceeding mtc0 and for the following eret. 355 * the preceding mtc0 and for the following eret.
356 */ 356 */
357enum tlb_write_entry { tlb_random, tlb_indexed }; 357enum tlb_write_entry { tlb_random, tlb_indexed };
358 358