diff options
Diffstat (limited to 'arch/mips/mm/uasm.c')
-rw-r--r-- | arch/mips/mm/uasm.c | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 0a165c5179a1..611d564fdcf1 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c | |||
@@ -19,8 +19,7 @@ | |||
19 | #include <asm/inst.h> | 19 | #include <asm/inst.h> |
20 | #include <asm/elf.h> | 20 | #include <asm/elf.h> |
21 | #include <asm/bugs.h> | 21 | #include <asm/bugs.h> |
22 | 22 | #include <asm/uasm.h> | |
23 | #include "uasm.h" | ||
24 | 23 | ||
25 | enum fields { | 24 | enum fields { |
26 | RS = 0x001, | 25 | RS = 0x001, |
@@ -32,7 +31,8 @@ enum fields { | |||
32 | BIMM = 0x040, | 31 | BIMM = 0x040, |
33 | JIMM = 0x080, | 32 | JIMM = 0x080, |
34 | FUNC = 0x100, | 33 | FUNC = 0x100, |
35 | SET = 0x200 | 34 | SET = 0x200, |
35 | SCIMM = 0x400 | ||
36 | }; | 36 | }; |
37 | 37 | ||
38 | #define OP_MASK 0x3f | 38 | #define OP_MASK 0x3f |
@@ -53,6 +53,8 @@ enum fields { | |||
53 | #define FUNC_SH 0 | 53 | #define FUNC_SH 0 |
54 | #define SET_MASK 0x7 | 54 | #define SET_MASK 0x7 |
55 | #define SET_SH 0 | 55 | #define SET_SH 0 |
56 | #define SCIMM_MASK 0xfffff | ||
57 | #define SCIMM_SH 6 | ||
56 | 58 | ||
57 | enum opcode { | 59 | enum opcode { |
58 | insn_invalid, | 60 | insn_invalid, |
@@ -62,9 +64,10 @@ enum opcode { | |||
62 | insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, | 64 | insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, |
63 | insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, | 65 | insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, |
64 | insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, | 66 | insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, |
65 | insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, | 67 | insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, |
66 | insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, | 68 | insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, |
67 | insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins | 69 | insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, |
70 | insn_dins, insn_syscall | ||
68 | }; | 71 | }; |
69 | 72 | ||
70 | struct insn { | 73 | struct insn { |
@@ -117,6 +120,7 @@ static struct insn insn_table[] __cpuinitdata = { | |||
117 | { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, | 120 | { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
118 | { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, | 121 | { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, |
119 | { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, | 122 | { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, |
123 | { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, | ||
120 | { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, | 124 | { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
121 | { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, | 125 | { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
122 | { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, | 126 | { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, |
@@ -126,14 +130,17 @@ static struct insn insn_table[] __cpuinitdata = { | |||
126 | { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, | 130 | { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, |
127 | { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, | 131 | { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, |
128 | { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, | 132 | { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, |
133 | { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, | ||
129 | { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, | 134 | { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, |
130 | { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, | 135 | { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
131 | { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, | 136 | { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, |
137 | { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, | ||
132 | { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, | 138 | { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, |
133 | { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, | 139 | { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, |
134 | { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, | 140 | { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, |
135 | { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, | 141 | { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
136 | { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, | 142 | { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, |
143 | { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, | ||
137 | { insn_invalid, 0, 0 } | 144 | { insn_invalid, 0, 0 } |
138 | }; | 145 | }; |
139 | 146 | ||
@@ -206,6 +213,14 @@ static inline __cpuinit u32 build_jimm(u32 arg) | |||
206 | return (arg >> 2) & JIMM_MASK; | 213 | return (arg >> 2) & JIMM_MASK; |
207 | } | 214 | } |
208 | 215 | ||
216 | static inline __cpuinit u32 build_scimm(u32 arg) | ||
217 | { | ||
218 | if (arg & ~SCIMM_MASK) | ||
219 | printk(KERN_WARNING "Micro-assembler field overflow\n"); | ||
220 | |||
221 | return (arg & SCIMM_MASK) << SCIMM_SH; | ||
222 | } | ||
223 | |||
209 | static inline __cpuinit u32 build_func(u32 arg) | 224 | static inline __cpuinit u32 build_func(u32 arg) |
210 | { | 225 | { |
211 | if (arg & ~FUNC_MASK) | 226 | if (arg & ~FUNC_MASK) |
@@ -264,6 +279,8 @@ static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...) | |||
264 | op |= build_func(va_arg(ap, u32)); | 279 | op |= build_func(va_arg(ap, u32)); |
265 | if (ip->fields & SET) | 280 | if (ip->fields & SET) |
266 | op |= build_set(va_arg(ap, u32)); | 281 | op |= build_set(va_arg(ap, u32)); |
282 | if (ip->fields & SCIMM) | ||
283 | op |= build_scimm(va_arg(ap, u32)); | ||
267 | va_end(ap); | 284 | va_end(ap); |
268 | 285 | ||
269 | **buf = op; | 286 | **buf = op; |
@@ -371,6 +388,7 @@ I_u2s3u1(_lw) | |||
371 | I_u1u2u3(_mfc0) | 388 | I_u1u2u3(_mfc0) |
372 | I_u1u2u3(_mtc0) | 389 | I_u1u2u3(_mtc0) |
373 | I_u2u1u3(_ori) | 390 | I_u2u1u3(_ori) |
391 | I_u3u1u2(_or) | ||
374 | I_u2s3u1(_pref) | 392 | I_u2s3u1(_pref) |
375 | I_0(_rfe) | 393 | I_0(_rfe) |
376 | I_u2s3u1(_sc) | 394 | I_u2s3u1(_sc) |
@@ -379,14 +397,17 @@ I_u2s3u1(_sd) | |||
379 | I_u2u1u3(_sll) | 397 | I_u2u1u3(_sll) |
380 | I_u2u1u3(_sra) | 398 | I_u2u1u3(_sra) |
381 | I_u2u1u3(_srl) | 399 | I_u2u1u3(_srl) |
400 | I_u2u1u3(_rotr) | ||
382 | I_u3u1u2(_subu) | 401 | I_u3u1u2(_subu) |
383 | I_u2s3u1(_sw) | 402 | I_u2s3u1(_sw) |
384 | I_0(_tlbp) | 403 | I_0(_tlbp) |
404 | I_0(_tlbr) | ||
385 | I_0(_tlbwi) | 405 | I_0(_tlbwi) |
386 | I_0(_tlbwr) | 406 | I_0(_tlbwr) |
387 | I_u3u1u2(_xor) | 407 | I_u3u1u2(_xor) |
388 | I_u2u1u3(_xori) | 408 | I_u2u1u3(_xori) |
389 | I_u2u1msbu3(_dins); | 409 | I_u2u1msbu3(_dins); |
410 | I_u1(_syscall); | ||
390 | 411 | ||
391 | /* Handle labels. */ | 412 | /* Handle labels. */ |
392 | void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) | 413 | void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) |