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-rw-r--r--arch/mips/mm/cache.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index fde7e56d13fe..e422b38d3113 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -49,7 +49,7 @@ EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
49EXPORT_SYMBOL(flush_data_cache_page); 49EXPORT_SYMBOL(flush_data_cache_page);
50EXPORT_SYMBOL(flush_icache_all); 50EXPORT_SYMBOL(flush_icache_all);
51 51
52#ifdef CONFIG_DMA_NONCOHERENT 52#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
53 53
54/* DMA cache operations. */ 54/* DMA cache operations. */
55void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); 55void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
@@ -58,7 +58,7 @@ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
58 58
59EXPORT_SYMBOL(_dma_cache_wback_inv); 59EXPORT_SYMBOL(_dma_cache_wback_inv);
60 60
61#endif /* CONFIG_DMA_NONCOHERENT */ 61#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
62 62
63/* 63/*
64 * We could optimize the case where the cache argument is not BCACHE but 64 * We could optimize the case where the cache argument is not BCACHE but