1 files changed, 11 insertions, 9 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 32b7f6aeb983..4182e1176fae 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -154,7 +154,8 @@ static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 
 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 {
-        unsigned long start = page;
+        unsigned long indexmask = current_cpu_data.icache.waysize - 1;
+        unsigned long start = INDEX_BASE + (page & indexmask);
         unsigned long end = start + PAGE_SIZE;
         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
         unsigned long ws_end = current_cpu_data.icache.ways <<
@@ -749,12 +750,12 @@ static void __init probe_pcache(void)
                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                 c->icache.ways = 2;
-                c->icache.waybit = ffs(icache_size/2) - 1;
+                c->icache.waybit = __ffs(icache_size/2);
 
                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
                 c->dcache.ways = 2;
-                c->dcache.waybit= ffs(dcache_size/2) - 1;
+                c->dcache.waybit= __ffs(dcache_size/2);
 
                 c->options |= MIPS_CPU_CACHE_CDEX_P;
                 break;
@@ -837,12 +838,12 @@ static void __init probe_pcache(void)
                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                 c->icache.ways = 2;
-                c->icache.waybit = ffs(icache_size/2) - 1;
+                c->icache.waybit = __ffs(icache_size/2);
 
                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
                 c->dcache.ways = 2;
-                c->dcache.waybit = ffs(dcache_size/2) - 1;
+                c->dcache.waybit = __ffs(dcache_size/2);
 
                 c->options |= MIPS_CPU_CACHE_CDEX_P;
                 break;
@@ -873,12 +874,12 @@ static void __init probe_pcache(void)
                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                 c->icache.ways = 4;
-                c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
+                c->icache.waybit = __ffs(icache_size / c->icache.ways);
 
                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
                 c->dcache.ways = 4;
-                c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
+                c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 
 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
                 c->options |= MIPS_CPU_CACHE_CDEX_P;
@@ -906,7 +907,7 @@ static void __init probe_pcache(void)
                 icache_size = c->icache.sets *
                               c->icache.ways *
                               c->icache.linesz;
-                c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
+                c->icache.waybit = __ffs(icache_size/c->icache.ways);
 
                 if (config & 0x8)               /* VI bit */
                         c->icache.flags |= MIPS_CACHE_VTAG;
@@ -926,7 +927,7 @@ static void __init probe_pcache(void)
                 dcache_size = c->dcache.sets *
                               c->dcache.ways *
                               c->dcache.linesz;
-                c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
+                c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
 
                 c->options |= MIPS_CPU_PREFETCH;
                 break;
@@ -1198,6 +1199,7 @@ void __init r4k_cache_init(void)
 
         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
         flush_icache_all        = r4k_flush_icache_all;
+        local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
         flush_data_cache_page   = r4k_flush_data_cache_page;
         flush_icache_range      = r4k_flush_icache_range;