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-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c92
-rw-r--r--arch/mips/mips-boards/generic/Makefile4
-rw-r--r--arch/mips/mips-boards/generic/gdb_hook.c2
-rw-r--r--arch/mips/mips-boards/generic/init.c2
-rw-r--r--arch/mips/mips-boards/generic/memory.c9
-rw-r--r--arch/mips/mips-boards/generic/mipsIRQ.S155
-rw-r--r--arch/mips/mips-boards/generic/pci.c1
-rw-r--r--arch/mips/mips-boards/generic/time.c68
-rw-r--r--arch/mips/mips-boards/malta/Makefile1
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c105
-rw-r--r--arch/mips/mips-boards/malta/malta_smp.c128
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c86
-rw-r--r--arch/mips/mips-boards/sim/cmdline.c59
-rw-r--r--arch/mips/mips-boards/sim/sim_cmdline.c6
-rw-r--r--arch/mips/mips-boards/sim/sim_int.c64
-rw-r--r--arch/mips/mips-boards/sim/sim_irq.S4
-rw-r--r--arch/mips/mips-boards/sim/sim_mem.c9
-rw-r--r--arch/mips/mips-boards/sim/sim_smp.c14
18 files changed, 536 insertions, 273 deletions
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index bc0ebc69bfb3..db53950b7cfb 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -39,8 +39,6 @@
39 39
40static struct atlas_ictrl_regs *atlas_hw0_icregs; 40static struct atlas_ictrl_regs *atlas_hw0_icregs;
41 41
42extern asmlinkage void mipsIRQ(void);
43
44#if 0 42#if 0
45#define DEBUG_INT(x...) printk(x) 43#define DEBUG_INT(x...) printk(x)
46#else 44#else
@@ -98,7 +96,7 @@ static inline int ls1bit32(unsigned int x)
98 return b; 96 return b;
99} 97}
100 98
101void atlas_hw0_irqdispatch(struct pt_regs *regs) 99static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
102{ 100{
103 unsigned long int_status; 101 unsigned long int_status;
104 int irq; 102 int irq;
@@ -116,6 +114,91 @@ void atlas_hw0_irqdispatch(struct pt_regs *regs)
116 do_IRQ(irq, regs); 114 do_IRQ(irq, regs);
117} 115}
118 116
117static inline int clz(unsigned long x)
118{
119 __asm__ (
120 " .set push \n"
121 " .set mips32 \n"
122 " clz %0, %1 \n"
123 " .set pop \n"
124 : "=r" (x)
125 : "r" (x));
126
127 return x;
128}
129
130/*
131 * Version of ffs that only looks at bits 12..15.
132 */
133static inline unsigned int irq_ffs(unsigned int pending)
134{
135#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
136 return -clz(pending) + 31 - CAUSEB_IP;
137#else
138 unsigned int a0 = 7;
139 unsigned int t0;
140
141 t0 = s0 & 0xf000;
142 t0 = t0 < 1;
143 t0 = t0 << 2;
144 a0 = a0 - t0;
145 s0 = s0 << t0;
146
147 t0 = s0 & 0xc000;
148 t0 = t0 < 1;
149 t0 = t0 << 1;
150 a0 = a0 - t0;
151 s0 = s0 << t0;
152
153 t0 = s0 & 0x8000;
154 t0 = t0 < 1;
155 //t0 = t0 << 2;
156 a0 = a0 - t0;
157 //s0 = s0 << t0;
158
159 return a0;
160#endif
161}
162
163/*
164 * IRQs on the Atlas board look basically (barring software IRQs which we
165 * don't use at all and all external interrupt sources are combined together
166 * on hardware interrupt 0 (MIPS IRQ 2)) like:
167 *
168 * MIPS IRQ Source
169 * -------- ------
170 * 0 Software (ignored)
171 * 1 Software (ignored)
172 * 2 Combined hardware interrupt (hw0)
173 * 3 Hardware (ignored)
174 * 4 Hardware (ignored)
175 * 5 Hardware (ignored)
176 * 6 Hardware (ignored)
177 * 7 R4k timer (what we use)
178 *
179 * We handle the IRQ according to _our_ priority which is:
180 *
181 * Highest ---- R4k Timer
182 * Lowest ---- Combined hardware interrupt
183 *
184 * then we just return, if multiple IRQs are pending then we will just take
185 * another exception, big deal.
186 */
187asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
188{
189 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
190 int irq;
191
192 irq = irq_ffs(pending);
193
194 if (irq == MIPSCPU_INT_ATLAS)
195 atlas_hw0_irqdispatch(regs);
196 else if (irq > 0)
197 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
198 else
199 spurious_interrupt(regs);
200}
201
119void __init arch_init_irq(void) 202void __init arch_init_irq(void)
120{ 203{
121 int i; 204 int i;
@@ -128,9 +211,6 @@ void __init arch_init_irq(void)
128 */ 211 */
129 atlas_hw0_icregs->intrsten = 0xffffffff; 212 atlas_hw0_icregs->intrsten = 0xffffffff;
130 213
131 /* Now safe to set the exception vector. */
132 set_except_vector(0, mipsIRQ);
133
134 for (i = ATLASINT_BASE; i <= ATLASINT_END; i++) { 214 for (i = ATLASINT_BASE; i <= ATLASINT_END; i++) {
135 irq_desc[i].status = IRQ_DISABLED; 215 irq_desc[i].status = IRQ_DISABLED;
136 irq_desc[i].action = 0; 216 irq_desc[i].action = 0;
diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile
index b21bc6887fa8..be47c1c2bc80 100644
--- a/arch/mips/mips-boards/generic/Makefile
+++ b/arch/mips/mips-boards/generic/Makefile
@@ -18,8 +18,8 @@
18# Makefile for the MIPS boards generic routines under Linux. 18# Makefile for the MIPS boards generic routines under Linux.
19# 19#
20 20
21obj-y := mipsIRQ.o reset.o display.o init.o memory.o \ 21obj-y := reset.o display.o init.o memory.o printf.o \
22 printf.o cmdline.o time.o 22 cmdline.o time.o
23obj-$(CONFIG_PCI) += pci.o 23obj-$(CONFIG_PCI) += pci.o
24obj-$(CONFIG_KGDB) += gdb_hook.o 24obj-$(CONFIG_KGDB) += gdb_hook.o
25 25
diff --git a/arch/mips/mips-boards/generic/gdb_hook.c b/arch/mips/mips-boards/generic/gdb_hook.c
index 91a2ccbe3730..6a1854de4579 100644
--- a/arch/mips/mips-boards/generic/gdb_hook.c
+++ b/arch/mips/mips-boards/generic/gdb_hook.c
@@ -25,7 +25,7 @@
25#include <asm/serial.h> 25#include <asm/serial.h>
26#include <asm/io.h> 26#include <asm/io.h>
27 27
28static struct serial_state rs_table[RS_TABLE_SIZE] = { 28static struct serial_state rs_table[] = {
29 SERIAL_PORT_DFNS /* Defined in serial.h */ 29 SERIAL_PORT_DFNS /* Defined in serial.h */
30}; 30};
31 31
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index eab5a705e989..df4e94735604 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -220,7 +220,6 @@ void __init kgdb_config (void)
220 generic_putDebugChar (*s++); 220 generic_putDebugChar (*s++);
221 } 221 }
222 222
223 kgdb_enabled = 1;
224 /* Breakpoint is invoked after interrupts are initialised */ 223 /* Breakpoint is invoked after interrupts are initialised */
225 } 224 }
226} 225}
@@ -338,6 +337,7 @@ void __init prom_init(void)
338 case MIPS_REVISION_CORID_CORE_MSC: 337 case MIPS_REVISION_CORID_CORE_MSC:
339 case MIPS_REVISION_CORID_CORE_FPGA2: 338 case MIPS_REVISION_CORID_CORE_FPGA2:
340 case MIPS_REVISION_CORID_CORE_FPGA3: 339 case MIPS_REVISION_CORID_CORE_FPGA3:
340 case MIPS_REVISION_CORID_CORE_24K:
341 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 341 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
342 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 342 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
343 343
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index 32c9210373ac..bc4d093685bb 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -22,10 +22,12 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/mm.h> 23#include <linux/mm.h>
24#include <linux/bootmem.h> 24#include <linux/bootmem.h>
25#include <linux/pfn.h>
25#include <linux/string.h> 26#include <linux/string.h>
26 27
27#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
28#include <asm/page.h> 29#include <asm/page.h>
30#include <asm/sections.h>
29 31
30#include <asm/mips-boards/prom.h> 32#include <asm/mips-boards/prom.h>
31 33
@@ -46,9 +48,6 @@ static char *mtypes[3] = {
46}; 48};
47#endif 49#endif
48 50
49/* References to section boundaries */
50extern char _end;
51
52struct prom_pmemblock * __init prom_getmdesc(void) 51struct prom_pmemblock * __init prom_getmdesc(void)
53{ 52{
54 char *memsize_str; 53 char *memsize_str;
@@ -106,10 +105,10 @@ struct prom_pmemblock * __init prom_getmdesc(void)
106 105
107 mdesc[3].type = yamon_dontuse; 106 mdesc[3].type = yamon_dontuse;
108 mdesc[3].base = 0x00100000; 107 mdesc[3].base = 0x00100000;
109 mdesc[3].size = CPHYSADDR(PAGE_ALIGN(&_end)) - mdesc[3].base; 108 mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base;
110 109
111 mdesc[4].type = yamon_free; 110 mdesc[4].type = yamon_free;
112 mdesc[4].base = CPHYSADDR(PAGE_ALIGN(&_end)); 111 mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end));
113 mdesc[4].size = memsize - mdesc[4].base; 112 mdesc[4].size = memsize - mdesc[4].base;
114 113
115 return &mdesc[0]; 114 return &mdesc[0];
diff --git a/arch/mips/mips-boards/generic/mipsIRQ.S b/arch/mips/mips-boards/generic/mipsIRQ.S
deleted file mode 100644
index ddd5c73a2971..000000000000
--- a/arch/mips/mips-boards/generic/mipsIRQ.S
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Interrupt exception dispatch code.
23 *
24 */
25#include <linux/config.h>
26
27#include <asm/asm.h>
28#include <asm/mipsregs.h>
29#include <asm/regdef.h>
30#include <asm/stackframe.h>
31
32#ifdef CONFIG_MIPS_ATLAS
33#include <asm/mips-boards/atlasint.h>
34#define CASCADE_IRQ MIPSCPU_INT_ATLAS
35#define CASCADE_DISPATCH atlas_hw0_irqdispatch
36#endif
37#ifdef CONFIG_MIPS_MALTA
38#include <asm/mips-boards/maltaint.h>
39#define CASCADE_IRQ MIPSCPU_INT_I8259A
40#define CASCADE_DISPATCH malta_hw0_irqdispatch
41#endif
42#ifdef CONFIG_MIPS_SEAD
43#include <asm/mips-boards/seadint.h>
44#endif
45
46/* A lot of complication here is taken away because:
47 *
48 * 1) We handle one interrupt and return, sitting in a loop and moving across
49 * all the pending IRQ bits in the cause register is _NOT_ the answer, the
50 * common case is one pending IRQ so optimize in that direction.
51 *
52 * 2) We need not check against bits in the status register IRQ mask, that
53 * would make this routine slow as hell.
54 *
55 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
56 * between like BSD spl() brain-damage.
57 *
58 * Furthermore, the IRQs on the MIPS board look basically (barring software
59 * IRQs which we don't use at all and all external interrupt sources are
60 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
61 *
62 * MIPS IRQ Source
63 * -------- ------
64 * 0 Software (ignored)
65 * 1 Software (ignored)
66 * 2 Combined hardware interrupt (hw0)
67 * 3 Hardware (ignored)
68 * 4 Hardware (ignored)
69 * 5 Hardware (ignored)
70 * 6 Hardware (ignored)
71 * 7 R4k timer (what we use)
72 *
73 * Note: On the SEAD board thing are a little bit different.
74 * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
75 * wired to UART1.
76 *
77 * We handle the IRQ according to _our_ priority which is:
78 *
79 * Highest ---- R4k Timer
80 * Lowest ---- Combined hardware interrupt
81 *
82 * then we just return, if multiple IRQs are pending then we will just take
83 * another exception, big deal.
84 */
85
86 .text
87 .set noreorder
88 .set noat
89 .align 5
90 NESTED(mipsIRQ, PT_SIZE, sp)
91 SAVE_ALL
92 CLI
93 .set at
94
95 mfc0 s0, CP0_CAUSE # get irq bits
96 mfc0 s1, CP0_STATUS # get irq mask
97 andi s0, ST0_IM # CAUSE.CE may be non-zero!
98 and s0, s1
99
100#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
101 .set mips32
102 clz a0, s0
103 .set mips0
104 negu a0
105 addu a0, 31-CAUSEB_IP
106 bltz a0, spurious
107#else
108 beqz s0, spurious
109 li a0, 7
110
111 and t0, s0, 0xf000
112 sltiu t0, t0, 1
113 sll t0, 2
114 subu a0, t0
115 sll s0, t0
116
117 and t0, s0, 0xc000
118 sltiu t0, t0, 1
119 sll t0, 1
120 subu a0, t0
121 sll s0, t0
122
123 and t0, s0, 0x8000
124 sltiu t0, t0, 1
125 # sll t0, 0
126 subu a0, t0
127 # sll s0, t0
128#endif
129
130#ifdef CASCADE_IRQ
131 li a1, CASCADE_IRQ
132 bne a0, a1, 1f
133 addu a0, MIPSCPU_INT_BASE
134
135 jal CASCADE_DISPATCH
136 move a0, sp
137
138 j ret_from_irq
139 nop
1401:
141#else
142 addu a0, MIPSCPU_INT_BASE
143#endif
144
145 jal do_IRQ
146 move a1, sp
147
148 j ret_from_irq
149 nop
150
151
152spurious:
153 j spurious_interrupt
154 nop
155 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index 1f6f9df74ab2..9337f6c8873a 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -198,6 +198,7 @@ void __init mips_pcibios_init(void)
198 case MIPS_REVISION_CORID_CORE_MSC: 198 case MIPS_REVISION_CORID_CORE_MSC:
199 case MIPS_REVISION_CORID_CORE_FPGA2: 199 case MIPS_REVISION_CORID_CORE_FPGA2:
200 case MIPS_REVISION_CORID_CORE_FPGA3: 200 case MIPS_REVISION_CORID_CORE_FPGA3:
201 case MIPS_REVISION_CORID_CORE_24K:
201 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 202 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
202 /* Set up resource ranges from the controller's registers. */ 203 /* Set up resource ranges from the controller's registers. */
203 MSC_READ(MSC01_PCI_SC2PMBASL, start); 204 MSC_READ(MSC01_PCI_SC2PMBASL, start);
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 93f3bf2c2b22..a9f6124b3a22 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -30,6 +30,7 @@
30#include <linux/mc146818rtc.h> 30#include <linux/mc146818rtc.h>
31 31
32#include <asm/mipsregs.h> 32#include <asm/mipsregs.h>
33#include <asm/mipsmtregs.h>
33#include <asm/ptrace.h> 34#include <asm/ptrace.h>
34#include <asm/hardirq.h> 35#include <asm/hardirq.h>
35#include <asm/irq.h> 36#include <asm/irq.h>
@@ -50,16 +51,23 @@ unsigned long cpu_khz;
50static char display_string[] = " LINUX ON ATLAS "; 51static char display_string[] = " LINUX ON ATLAS ";
51#endif 52#endif
52#if defined(CONFIG_MIPS_MALTA) 53#if defined(CONFIG_MIPS_MALTA)
54#if defined(CONFIG_MIPS_MT_SMTC)
55static char display_string[] = " SMTC LINUX ON MALTA ";
56#else
53static char display_string[] = " LINUX ON MALTA "; 57static char display_string[] = " LINUX ON MALTA ";
58#endif /* CONFIG_MIPS_MT_SMTC */
54#endif 59#endif
55#if defined(CONFIG_MIPS_SEAD) 60#if defined(CONFIG_MIPS_SEAD)
56static char display_string[] = " LINUX ON SEAD "; 61static char display_string[] = " LINUX ON SEAD ";
57#endif 62#endif
58static unsigned int display_count = 0; 63static unsigned int display_count;
59#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) 64#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
60 65
61static unsigned int timer_tick_count=0; 66#define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR)
67
68static unsigned int timer_tick_count;
62static int mips_cpu_timer_irq; 69static int mips_cpu_timer_irq;
70extern void smtc_timer_broadcast(int);
63 71
64static inline void scroll_display_message(void) 72static inline void scroll_display_message(void)
65{ 73{
@@ -75,15 +83,55 @@ static void mips_timer_dispatch (struct pt_regs *regs)
75 do_IRQ (mips_cpu_timer_irq, regs); 83 do_IRQ (mips_cpu_timer_irq, regs);
76} 84}
77 85
86/*
87 * Redeclare until I get around mopping the timer code insanity on MIPS.
88 */
78extern int null_perf_irq(struct pt_regs *regs); 89extern int null_perf_irq(struct pt_regs *regs);
79 90
80extern int (*perf_irq)(struct pt_regs *regs); 91extern int (*perf_irq)(struct pt_regs *regs);
81 92
82irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 93irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
83{ 94{
84 int r2 = cpu_has_mips_r2;
85 int cpu = smp_processor_id(); 95 int cpu = smp_processor_id();
96 int r2 = cpu_has_mips_r2;
97
98#ifdef CONFIG_MIPS_MT_SMTC
99 /*
100 * In an SMTC system, one Count/Compare set exists per VPE.
101 * Which TC within a VPE gets the interrupt is essentially
102 * random - we only know that it shouldn't be one with
103 * IXMT set. Whichever TC gets the interrupt needs to
104 * send special interprocessor interrupts to the other
105 * TCs to make sure that they schedule, etc.
106 *
107 * That code is specific to the SMTC kernel, not to
108 * the a particular platform, so it's invoked from
109 * the general MIPS timer_interrupt routine.
110 */
111
112 /*
113 * DVPE is necessary so long as cross-VPE interrupts
114 * are done via read-modify-write of Cause register.
115 */
116 int vpflags = dvpe();
117 write_c0_compare (read_c0_count() - 1);
118 clear_c0_cause(CPUCTR_IMASKBIT);
119 evpe(vpflags);
120
121 if (cpu_data[cpu].vpe_id == 0) {
122 timer_interrupt(irq, dev_id, regs);
123 scroll_display_message();
124 } else
125 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
126 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
86 127
128 if (cpu != 0)
129 /*
130 * Other CPUs should do profiling and process accounting
131 */
132 local_timer_interrupt(irq, dev_id, regs);
133
134#else /* CONFIG_MIPS_MT_SMTC */
87 if (cpu == 0) { 135 if (cpu == 0) {
88 /* 136 /*
89 * CPU 0 handles the global timer interrupt job and process 137 * CPU 0 handles the global timer interrupt job and process
@@ -107,12 +155,14 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
107 * More support needs to be added to kernel/time for 155 * More support needs to be added to kernel/time for
108 * counter/timer interrupts on multiple CPU's 156 * counter/timer interrupts on multiple CPU's
109 */ 157 */
110 write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ)); 158 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
159
111 /* 160 /*
112 * other CPUs should do profiling and process accounting 161 * Other CPUs should do profiling and process accounting
113 */ 162 */
114 local_timer_interrupt (irq, dev_id, regs); 163 local_timer_interrupt(irq, dev_id, regs);
115 } 164 }
165#endif /* CONFIG_MIPS_MT_SMTC */
116 166
117out: 167out:
118 return IRQ_HANDLED; 168 return IRQ_HANDLED;
@@ -126,7 +176,7 @@ static unsigned int __init estimate_cpu_frequency(void)
126 unsigned int prid = read_c0_prid() & 0xffff00; 176 unsigned int prid = read_c0_prid() & 0xffff00;
127 unsigned int count; 177 unsigned int count;
128 178
129#ifdef CONFIG_MIPS_SEAD 179#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
130 /* 180 /*
131 * The SEAD board doesn't have a real time clock, so we can't 181 * The SEAD board doesn't have a real time clock, so we can't
132 * really calculate the timer frequency 182 * really calculate the timer frequency
@@ -211,7 +261,11 @@ void __init mips_timer_setup(struct irqaction *irq)
211 261
212 /* we are using the cpu counter for timer interrupts */ 262 /* we are using the cpu counter for timer interrupts */
213 irq->handler = mips_timer_interrupt; /* we use our own handler */ 263 irq->handler = mips_timer_interrupt; /* we use our own handler */
264#ifdef CONFIG_MIPS_MT_SMTC
265 setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT);
266#else
214 setup_irq(mips_cpu_timer_irq, irq); 267 setup_irq(mips_cpu_timer_irq, irq);
268#endif /* CONFIG_MIPS_MT_SMTC */
215 269
216#ifdef CONFIG_SMP 270#ifdef CONFIG_SMP
217 /* irq_desc(riptor) is a global resource, when the interrupt overlaps 271 /* irq_desc(riptor) is a global resource, when the interrupt overlaps
diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile
index fd4c143c0e2f..77ee5c6d33c1 100644
--- a/arch/mips/mips-boards/malta/Makefile
+++ b/arch/mips/mips-boards/malta/Makefile
@@ -20,3 +20,4 @@
20# 20#
21 21
22obj-y := malta_int.o malta_setup.o 22obj-y := malta_int.o malta_setup.o
23obj-$(CONFIG_SMP) += malta_smp.o
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index d06dc5ad6c9e..7cc0ba4f553a 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -40,7 +40,6 @@
40#include <asm/mips-boards/msc01_pci.h> 40#include <asm/mips-boards/msc01_pci.h>
41#include <asm/msc01_ic.h> 41#include <asm/msc01_ic.h>
42 42
43extern asmlinkage void mipsIRQ(void);
44extern void mips_timer_interrupt(void); 43extern void mips_timer_interrupt(void);
45 44
46static DEFINE_SPINLOCK(mips_irq_lock); 45static DEFINE_SPINLOCK(mips_irq_lock);
@@ -58,6 +57,7 @@ static inline int mips_pcibios_iack(void)
58 case MIPS_REVISION_CORID_CORE_MSC: 57 case MIPS_REVISION_CORID_CORE_MSC:
59 case MIPS_REVISION_CORID_CORE_FPGA2: 58 case MIPS_REVISION_CORID_CORE_FPGA2:
60 case MIPS_REVISION_CORID_CORE_FPGA3: 59 case MIPS_REVISION_CORID_CORE_FPGA3:
60 case MIPS_REVISION_CORID_CORE_24K:
61 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 61 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
62 MSC_READ(MSC01_PCI_IACK, irq); 62 MSC_READ(MSC01_PCI_IACK, irq);
63 irq &= 0xff; 63 irq &= 0xff;
@@ -114,13 +114,14 @@ static inline int get_int(void)
114 return irq; 114 return irq;
115} 115}
116 116
117void malta_hw0_irqdispatch(struct pt_regs *regs) 117static void malta_hw0_irqdispatch(struct pt_regs *regs)
118{ 118{
119 int irq; 119 int irq;
120 120
121 irq = get_int(); 121 irq = get_int();
122 if (irq < 0) 122 if (irq < 0) {
123 return; /* interrupt has already been cleared */ 123 return; /* interrupt has already been cleared */
124 }
124 125
125 do_IRQ(MALTA_INT_BASE+irq, regs); 126 do_IRQ(MALTA_INT_BASE+irq, regs);
126} 127}
@@ -143,6 +144,7 @@ void corehi_irqdispatch(struct pt_regs *regs)
143 case MIPS_REVISION_CORID_CORE_MSC: 144 case MIPS_REVISION_CORID_CORE_MSC:
144 case MIPS_REVISION_CORID_CORE_FPGA2: 145 case MIPS_REVISION_CORID_CORE_FPGA2:
145 case MIPS_REVISION_CORID_CORE_FPGA3: 146 case MIPS_REVISION_CORID_CORE_FPGA3:
147 case MIPS_REVISION_CORID_CORE_24K:
146 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 148 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
147 ll_msc_irq(regs); 149 ll_msc_irq(regs);
148 break; 150 break;
@@ -182,6 +184,92 @@ void corehi_irqdispatch(struct pt_regs *regs)
182 die("CoreHi interrupt", regs); 184 die("CoreHi interrupt", regs);
183} 185}
184 186
187static inline int clz(unsigned long x)
188{
189 __asm__ (
190 " .set push \n"
191 " .set mips32 \n"
192 " clz %0, %1 \n"
193 " .set pop \n"
194 : "=r" (x)
195 : "r" (x));
196
197 return x;
198}
199
200/*
201 * Version of ffs that only looks at bits 12..15.
202 */
203static inline unsigned int irq_ffs(unsigned int pending)
204{
205#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
206 return -clz(pending) + 31 - CAUSEB_IP;
207#else
208 unsigned int a0 = 7;
209 unsigned int t0;
210
211 t0 = s0 & 0xf000;
212 t0 = t0 < 1;
213 t0 = t0 << 2;
214 a0 = a0 - t0;
215 s0 = s0 << t0;
216
217 t0 = s0 & 0xc000;
218 t0 = t0 < 1;
219 t0 = t0 << 1;
220 a0 = a0 - t0;
221 s0 = s0 << t0;
222
223 t0 = s0 & 0x8000;
224 t0 = t0 < 1;
225 //t0 = t0 << 2;
226 a0 = a0 - t0;
227 //s0 = s0 << t0;
228
229 return a0;
230#endif
231}
232
233/*
234 * IRQs on the Malta board look basically (barring software IRQs which we
235 * don't use at all and all external interrupt sources are combined together
236 * on hardware interrupt 0 (MIPS IRQ 2)) like:
237 *
238 * MIPS IRQ Source
239 * -------- ------
240 * 0 Software (ignored)
241 * 1 Software (ignored)
242 * 2 Combined hardware interrupt (hw0)
243 * 3 Hardware (ignored)
244 * 4 Hardware (ignored)
245 * 5 Hardware (ignored)
246 * 6 Hardware (ignored)
247 * 7 R4k timer (what we use)
248 *
249 * We handle the IRQ according to _our_ priority which is:
250 *
251 * Highest ---- R4k Timer
252 * Lowest ---- Combined hardware interrupt
253 *
254 * then we just return, if multiple IRQs are pending then we will just take
255 * another exception, big deal.
256 */
257
258asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
259{
260 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
261 int irq;
262
263 irq = irq_ffs(pending);
264
265 if (irq == MIPSCPU_INT_I8259A)
266 malta_hw0_irqdispatch(regs);
267 else if (irq > 0)
268 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
269 else
270 spurious_interrupt(regs);
271}
272
185static struct irqaction i8259irq = { 273static struct irqaction i8259irq = {
186 .handler = no_action, 274 .handler = no_action,
187 .name = "XT-PIC cascade" 275 .name = "XT-PIC cascade"
@@ -214,7 +302,6 @@ int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
214 302
215void __init arch_init_irq(void) 303void __init arch_init_irq(void)
216{ 304{
217 set_except_vector(0, mipsIRQ);
218 init_i8259_irqs(); 305 init_i8259_irqs();
219 306
220 if (!cpu_has_veic) 307 if (!cpu_has_veic)
@@ -224,6 +311,7 @@ void __init arch_init_irq(void)
224 case MIPS_REVISION_CORID_CORE_MSC: 311 case MIPS_REVISION_CORID_CORE_MSC:
225 case MIPS_REVISION_CORID_CORE_FPGA2: 312 case MIPS_REVISION_CORID_CORE_FPGA2:
226 case MIPS_REVISION_CORID_CORE_FPGA3: 313 case MIPS_REVISION_CORID_CORE_FPGA3:
314 case MIPS_REVISION_CORID_CORE_24K:
227 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 315 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
228 if (cpu_has_veic) 316 if (cpu_has_veic)
229 init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 317 init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
@@ -240,12 +328,17 @@ void __init arch_init_irq(void)
240 else if (cpu_has_vint) { 328 else if (cpu_has_vint) {
241 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 329 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
242 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); 330 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
243 331#ifdef CONFIG_MIPS_MT_SMTC
332 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
333 (0x100 << MIPSCPU_INT_I8259A));
334 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
335 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
336#else /* Not SMTC */
244 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); 337 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
245 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 338 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
339#endif /* CONFIG_MIPS_MT_SMTC */
246 } 340 }
247 else { 341 else {
248 set_except_vector(0, mipsIRQ);
249 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); 342 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
250 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 343 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
251 } 344 }
diff --git a/arch/mips/mips-boards/malta/malta_smp.c b/arch/mips/mips-boards/malta/malta_smp.c
new file mode 100644
index 000000000000..6c6c8eeedbce
--- /dev/null
+++ b/arch/mips/mips-boards/malta/malta_smp.c
@@ -0,0 +1,128 @@
1/*
2 * Malta Platform-specific hooks for SMP operation
3 */
4
5#include <linux/kernel.h>
6#include <linux/sched.h>
7#include <linux/cpumask.h>
8#include <linux/interrupt.h>
9
10#include <asm/atomic.h>
11#include <asm/cpu.h>
12#include <asm/processor.h>
13#include <asm/system.h>
14#include <asm/hardirq.h>
15#include <asm/mmu_context.h>
16#include <asm/smp.h>
17#ifdef CONFIG_MIPS_MT_SMTC
18#include <asm/smtc_ipi.h>
19#endif /* CONFIG_MIPS_MT_SMTC */
20
21/* VPE/SMP Prototype implements platform interfaces directly */
22#if !defined(CONFIG_MIPS_MT_SMP)
23
24/*
25 * Cause the specified action to be performed on a targeted "CPU"
26 */
27
28void core_send_ipi(int cpu, unsigned int action)
29{
30/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
31#ifdef CONFIG_MIPS_MT_SMTC
32 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
33#endif /* CONFIG_MIPS_MT_SMTC */
34}
35
36/*
37 * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
38 */
39
40void __init prom_build_cpu_map(void)
41{
42 int nextslot;
43
44 /*
45 * As of November, 2004, MIPSsim only simulates one core
46 * at a time. However, that core may be a MIPS MT core
47 * with multiple virtual processors and thread contexts.
48 */
49
50 if (read_c0_config3() & (1<<2)) {
51 nextslot = mipsmt_build_cpu_map(1);
52 }
53}
54
55/*
56 * Platform "CPU" startup hook
57 */
58
59void prom_boot_secondary(int cpu, struct task_struct *idle)
60{
61#ifdef CONFIG_MIPS_MT_SMTC
62 smtc_boot_secondary(cpu, idle);
63#endif /* CONFIG_MIPS_MT_SMTC */
64}
65
66/*
67 * Post-config but pre-boot cleanup entry point
68 */
69
70void prom_init_secondary(void)
71{
72#ifdef CONFIG_MIPS_MT_SMTC
73 void smtc_init_secondary(void);
74 int myvpe;
75
76 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
77 myvpe = read_c0_tcbind() & TCBIND_CURVPE;
78 if (myvpe != 0) {
79 /* Ideally, this should be done only once per VPE, but... */
80 clear_c0_status(STATUSF_IP2);
81 set_c0_status(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP3
82 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6
83 | STATUSF_IP7);
84 }
85
86 smtc_init_secondary();
87#endif /* CONFIG_MIPS_MT_SMTC */
88}
89
90/*
91 * Platform SMP pre-initialization
92 *
93 * As noted above, we can assume a single CPU for now
94 * but it may be multithreaded.
95 */
96
97void plat_smp_setup(void)
98{
99 if (read_c0_config3() & (1<<2))
100 mipsmt_build_cpu_map(0);
101}
102
103void __init plat_prepare_cpus(unsigned int max_cpus)
104{
105 if (read_c0_config3() & (1<<2))
106 mipsmt_prepare_cpus();
107}
108
109/*
110 * SMP initialization finalization entry point
111 */
112
113void prom_smp_finish(void)
114{
115#ifdef CONFIG_MIPS_MT_SMTC
116 smtc_smp_finish();
117#endif /* CONFIG_MIPS_MT_SMTC */
118}
119
120/*
121 * Hook for after all CPUs are online
122 */
123
124void prom_cpus_done(void)
125{
126}
127
128#endif /* CONFIG_MIPS32R2_MT_SMP */
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 90fda0d9915f..9168d934c661 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -24,16 +24,94 @@
24#include <linux/irq.h> 24#include <linux/irq.h>
25 25
26#include <asm/irq_cpu.h> 26#include <asm/irq_cpu.h>
27#include <asm/mipsregs.h>
27#include <asm/system.h> 28#include <asm/system.h>
28 29
29#include <asm/mips-boards/seadint.h> 30#include <asm/mips-boards/seadint.h>
30 31
31extern asmlinkage void mipsIRQ(void); 32static inline int clz(unsigned long x)
33{
34 __asm__ (
35 " .set push \n"
36 " .set mips32 \n"
37 " clz %0, %1 \n"
38 " .set pop \n"
39 : "=r" (x)
40 : "r" (x));
41
42 return x;
43}
44
45/*
46 * Version of ffs that only looks at bits 12..15.
47 */
48static inline unsigned int irq_ffs(unsigned int pending)
49{
50#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
51 return -clz(pending) + 31 - CAUSEB_IP;
52#else
53 unsigned int a0 = 7;
54 unsigned int t0;
55
56 t0 = s0 & 0xf000;
57 t0 = t0 < 1;
58 t0 = t0 << 2;
59 a0 = a0 - t0;
60 s0 = s0 << t0;
61
62 t0 = s0 & 0xc000;
63 t0 = t0 < 1;
64 t0 = t0 << 1;
65 a0 = a0 - t0;
66 s0 = s0 << t0;
67
68 t0 = s0 & 0x8000;
69 t0 = t0 < 1;
70 //t0 = t0 << 2;
71 a0 = a0 - t0;
72 //s0 = s0 << t0;
73
74 return a0;
75#endif
76}
77
78/*
79 * IRQs on the SEAD board look basically are combined together on hardware
80 * interrupt 0 (MIPS IRQ 2)) like:
81 *
82 * MIPS IRQ Source
83 * -------- ------
84 * 0 Software (ignored)
85 * 1 Software (ignored)
86 * 2 UART0 (hw0)
87 * 3 UART1 (hw1)
88 * 4 Hardware (ignored)
89 * 5 Hardware (ignored)
90 * 6 Hardware (ignored)
91 * 7 R4k timer (what we use)
92 *
93 * We handle the IRQ according to _our_ priority which is:
94 *
95 * Highest ---- R4k Timer
96 * Lowest ---- Combined hardware interrupt
97 *
98 * then we just return, if multiple IRQs are pending then we will just take
99 * another exception, big deal.
100 */
101asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
102{
103 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
104 int irq;
105
106 irq = irq_ffs(pending);
107
108 if (irq >= 0)
109 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
110 else
111 spurious_interrupt(regs);
112}
32 113
33void __init arch_init_irq(void) 114void __init arch_init_irq(void)
34{ 115{
35 mips_cpu_irq_init(MIPSCPU_INT_BASE); 116 mips_cpu_irq_init(MIPSCPU_INT_BASE);
36
37 /* Now safe to set the exception vector. */
38 set_except_vector(0, mipsIRQ);
39} 117}
diff --git a/arch/mips/mips-boards/sim/cmdline.c b/arch/mips/mips-boards/sim/cmdline.c
deleted file mode 100644
index fef9fbd8e710..000000000000
--- a/arch/mips/mips-boards/sim/cmdline.c
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Kernel command line creation using the prom monitor (YAMON) argc/argv.
19 */
20#include <linux/init.h>
21#include <linux/string.h>
22
23#include <asm/bootinfo.h>
24
25extern int prom_argc;
26extern int *_prom_argv;
27
28/*
29 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
30 * This macro take care of sign extension.
31 */
32#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
33
34char arcs_cmdline[CL_SIZE];
35
36char * __init prom_getcmdline(void)
37{
38 return &(arcs_cmdline[0]);
39}
40
41
42void __init prom_init_cmdline(void)
43{
44 char *cp;
45 int actr;
46
47 actr = 1; /* Always ignore argv[0] */
48
49 cp = &(arcs_cmdline[0]);
50 while(actr < prom_argc) {
51 strcpy(cp, prom_argv(actr));
52 cp += strlen(prom_argv(actr));
53 *cp++ = ' ';
54 actr++;
55 }
56 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
57 --cp;
58 *cp = '\0';
59}
diff --git a/arch/mips/mips-boards/sim/sim_cmdline.c b/arch/mips/mips-boards/sim/sim_cmdline.c
index 9df37c6fca36..c63021a5dc6c 100644
--- a/arch/mips/mips-boards/sim/sim_cmdline.c
+++ b/arch/mips/mips-boards/sim/sim_cmdline.c
@@ -26,8 +26,10 @@ char * __init prom_getcmdline(void)
26 return arcs_cmdline; 26 return arcs_cmdline;
27} 27}
28 28
29
30void __init prom_init_cmdline(void) 29void __init prom_init_cmdline(void)
31{ 30{
32 /* nothing to do */ 31 char *cp;
32 cp = arcs_cmdline;
33 /* Get boot line from environment? */
34 *cp = '\0';
33} 35}
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c
index a4d0a2c05031..2c15c8efec4e 100644
--- a/arch/mips/mips-boards/sim/sim_int.c
+++ b/arch/mips/mips-boards/sim/sim_int.c
@@ -25,17 +25,71 @@
25 25
26extern void mips_cpu_irq_init(int); 26extern void mips_cpu_irq_init(int);
27 27
28extern asmlinkage void simIRQ(void); 28static inline int clz(unsigned long x)
29{
30 __asm__ (
31 " .set push \n"
32 " .set mips32 \n"
33 " clz %0, %1 \n"
34 " .set pop \n"
35 : "=r" (x)
36 : "r" (x));
37
38 return x;
39}
40
41/*
42 * Version of ffs that only looks at bits 12..15.
43 */
44static inline unsigned int irq_ffs(unsigned int pending)
45{
46#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
47 return -clz(pending) + 31 - CAUSEB_IP;
48#else
49 unsigned int a0 = 7;
50 unsigned int t0;
51
52 t0 = s0 & 0xf000;
53 t0 = t0 < 1;
54 t0 = t0 << 2;
55 a0 = a0 - t0;
56 s0 = s0 << t0;
57
58 t0 = s0 & 0xc000;
59 t0 = t0 < 1;
60 t0 = t0 << 1;
61 a0 = a0 - t0;
62 s0 = s0 << t0;
29 63
30asmlinkage void sim_hw0_irqdispatch(struct pt_regs *regs) 64 t0 = s0 & 0x8000;
65 t0 = t0 < 1;
66 //t0 = t0 << 2;
67 a0 = a0 - t0;
68 //s0 = s0 << t0;
69
70 return a0;
71#endif
72}
73
74static inline void sim_hw0_irqdispatch(struct pt_regs *regs)
31{ 75{
32 do_IRQ(2, regs); 76 do_IRQ(2, regs);
33} 77}
34 78
35void __init arch_init_irq(void) 79asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
36{ 80{
37 /* Now safe to set the exception vector. */ 81 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
38 set_except_vector(0, simIRQ); 82 int irq;
83
84 irq = irq_ffs(pending);
39 85
86 if (irq > 0)
87 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
88 else
89 spurious_interrupt(regs);
90}
91
92void __init arch_init_irq(void)
93{
40 mips_cpu_irq_init(MIPSCPU_INT_BASE); 94 mips_cpu_irq_init(MIPSCPU_INT_BASE);
41} 95}
diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S
index da52297a2216..d16cf3822076 100644
--- a/arch/mips/mips-boards/sim/sim_irq.S
+++ b/arch/mips/mips-boards/sim/sim_irq.S
@@ -94,6 +94,8 @@
94 94
95 95
96spurious: 96spurious:
97 j spurious_interrupt 97 jal spurious_interrupt
98 nop
99 j ret_from_irq
98 nop 100 nop
99 END(simIRQ) 101 END(simIRQ)
diff --git a/arch/mips/mips-boards/sim/sim_mem.c b/arch/mips/mips-boards/sim/sim_mem.c
index e57f737bab10..f7ce76983328 100644
--- a/arch/mips/mips-boards/sim/sim_mem.c
+++ b/arch/mips/mips-boards/sim/sim_mem.c
@@ -18,9 +18,11 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/bootmem.h> 20#include <linux/bootmem.h>
21#include <linux/pfn.h>
21 22
22#include <asm/bootinfo.h> 23#include <asm/bootinfo.h>
23#include <asm/page.h> 24#include <asm/page.h>
25#include <asm/sections.h>
24 26
25#include <asm/mips-boards/prom.h> 27#include <asm/mips-boards/prom.h>
26 28
@@ -39,9 +41,6 @@ static char *mtypes[3] = {
39}; 41};
40#endif 42#endif
41 43
42/* References to section boundaries */
43extern char _end;
44
45struct prom_pmemblock * __init prom_getmdesc(void) 44struct prom_pmemblock * __init prom_getmdesc(void)
46{ 45{
47 unsigned int memsize; 46 unsigned int memsize;
@@ -61,10 +60,10 @@ struct prom_pmemblock * __init prom_getmdesc(void)
61 60
62 mdesc[2].type = simmem_reserved; 61 mdesc[2].type = simmem_reserved;
63 mdesc[2].base = 0x00100000; 62 mdesc[2].base = 0x00100000;
64 mdesc[2].size = CPHYSADDR(PAGE_ALIGN(&_end)) - mdesc[2].base; 63 mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base;
65 64
66 mdesc[3].type = simmem_free; 65 mdesc[3].type = simmem_free;
67 mdesc[3].base = CPHYSADDR(PAGE_ALIGN(&_end)); 66 mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end));
68 mdesc[3].size = memsize - mdesc[3].base; 67 mdesc[3].size = memsize - mdesc[3].base;
69 68
70 return &mdesc[0]; 69 return &mdesc[0];
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c
index a9f0c2bfe4ad..b7084e7c4bf9 100644
--- a/arch/mips/mips-boards/sim/sim_smp.c
+++ b/arch/mips/mips-boards/sim/sim_smp.c
@@ -44,8 +44,6 @@
44void core_send_ipi(int cpu, unsigned int action) 44void core_send_ipi(int cpu, unsigned int action)
45{ 45{
46#ifdef CONFIG_MIPS_MT_SMTC 46#ifdef CONFIG_MIPS_MT_SMTC
47 void smtc_send_ipi(int, int, unsigned int);
48
49 smtc_send_ipi(cpu, LINUX_SMP_IPI, action); 47 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
50#endif /* CONFIG_MIPS_MT_SMTC */ 48#endif /* CONFIG_MIPS_MT_SMTC */
51/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ 49/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
@@ -59,15 +57,8 @@ void core_send_ipi(int cpu, unsigned int action)
59void __init prom_build_cpu_map(void) 57void __init prom_build_cpu_map(void)
60{ 58{
61#ifdef CONFIG_MIPS_MT_SMTC 59#ifdef CONFIG_MIPS_MT_SMTC
62 extern int mipsmt_build_cpu_map(int startslot);
63 int nextslot; 60 int nextslot;
64 61
65 cpus_clear(phys_cpu_present_map);
66
67 /* Register the boot CPU */
68
69 smp_prepare_boot_cpu();
70
71 /* 62 /*
72 * As of November, 2004, MIPSsim only simulates one core 63 * As of November, 2004, MIPSsim only simulates one core
73 * at a time. However, that core may be a MIPS MT core 64 * at a time. However, that core may be a MIPS MT core
@@ -87,8 +78,6 @@ void __init prom_build_cpu_map(void)
87void prom_boot_secondary(int cpu, struct task_struct *idle) 78void prom_boot_secondary(int cpu, struct task_struct *idle)
88{ 79{
89#ifdef CONFIG_MIPS_MT_SMTC 80#ifdef CONFIG_MIPS_MT_SMTC
90 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
91
92 smtc_boot_secondary(cpu, idle); 81 smtc_boot_secondary(cpu, idle);
93#endif /* CONFIG_MIPS_MT_SMTC */ 82#endif /* CONFIG_MIPS_MT_SMTC */
94} 83}
@@ -113,7 +102,6 @@ void prom_init_secondary(void)
113void prom_prepare_cpus(unsigned int max_cpus) 102void prom_prepare_cpus(unsigned int max_cpus)
114{ 103{
115#ifdef CONFIG_MIPS_MT_SMTC 104#ifdef CONFIG_MIPS_MT_SMTC
116 void mipsmt_prepare_cpus(int c);
117 /* 105 /*
118 * As noted above, we can assume a single CPU for now 106 * As noted above, we can assume a single CPU for now
119 * but it may be multithreaded. 107 * but it may be multithreaded.
@@ -132,8 +120,6 @@ void prom_prepare_cpus(unsigned int max_cpus)
132void prom_smp_finish(void) 120void prom_smp_finish(void)
133{ 121{
134#ifdef CONFIG_MIPS_MT_SMTC 122#ifdef CONFIG_MIPS_MT_SMTC
135 void smtc_smp_finish(void);
136
137 smtc_smp_finish(); 123 smtc_smp_finish();
138#endif /* CONFIG_MIPS_MT_SMTC */ 124#endif /* CONFIG_MIPS_MT_SMTC */
139} 125}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 15:30:52 -0500