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-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c12
-rw-r--r--arch/mips/mips-boards/malta/malta_smp.c19
2 files changed, 6 insertions, 25 deletions
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index b8488aab6df1..0766e434b6bd 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -53,11 +53,11 @@ extern void kgdb_config(void);
53#endif 53#endif
54 54
55struct resource standard_io_resources[] = { 55struct resource standard_io_resources[] = {
56 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, 56 { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
57 { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, 57 { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
58 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, 58 { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
59 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, 59 { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
60 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, 60 { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
61}; 61};
62 62
63#ifdef CONFIG_MTD 63#ifdef CONFIG_MTD
@@ -111,7 +111,7 @@ void __init fd_activate(void)
111} 111}
112#endif 112#endif
113 113
114void __init plat_setup(void) 114void __init plat_mem_setup(void)
115{ 115{
116 unsigned int i; 116 unsigned int i;
117 117
diff --git a/arch/mips/mips-boards/malta/malta_smp.c b/arch/mips/mips-boards/malta/malta_smp.c
index 6c6c8eeedbce..cf967170fe29 100644
--- a/arch/mips/mips-boards/malta/malta_smp.c
+++ b/arch/mips/mips-boards/malta/malta_smp.c
@@ -34,25 +34,6 @@ void core_send_ipi(int cpu, unsigned int action)
34} 34}
35 35
36/* 36/*
37 * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
38 */
39
40void __init prom_build_cpu_map(void)
41{
42 int nextslot;
43
44 /*
45 * As of November, 2004, MIPSsim only simulates one core
46 * at a time. However, that core may be a MIPS MT core
47 * with multiple virtual processors and thread contexts.
48 */
49
50 if (read_c0_config3() & (1<<2)) {
51 nextslot = mipsmt_build_cpu_map(1);
52 }
53}
54
55/*
56 * Platform "CPU" startup hook 37 * Platform "CPU" startup hook
57 */ 38 */
58 39