12 files changed, 55 insertions, 53 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6ae7ce4ac63e..f4630e1082ab 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -4,7 +4,7 @@
  * Copyright (C) xxxx  the Anonymous
  * Copyright (C) 1994 - 2006 Ralf Baechle
  * Copyright (C) 2003, 2004  Maciej W. Rozycki
- * Copyright (C) 2001, 2004  MIPS Inc.
+ * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -199,6 +199,7 @@ void __init check_wait(void)
                 cpu_wait = rm7k_wait_irqoff;
                 break;
 
+        case CPU_M14KC:
         case CPU_24K:
         case CPU_34K:
         case CPU_1004K:
@@ -810,6 +811,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_5KC;
                 __cpu_name[cpu] = "MIPS 5Kc";
                 break;
+        case PRID_IMP_5KE:
+                c->cputype = CPU_5KE;
+                __cpu_name[cpu] = "MIPS 5KE";
+                break;
         case PRID_IMP_20KC:
                 c->cputype = CPU_20KC;
                 __cpu_name[cpu] = "MIPS 20Kc";
@@ -831,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_74K;
                 __cpu_name[cpu] = "MIPS 74Kc";
                 break;
+        case PRID_IMP_M14KC:
+                c->cputype = CPU_M14KC;
+                __cpu_name[cpu] = "MIPS M14Kc";
+                break;
         case PRID_IMP_1004K:
                 c->cputype = CPU_1004K;
                 __cpu_name[cpu] = "MIPS 1004Kc";
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 57ba13edb03a..3fc1691110dc 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -5,7 +5,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05 by Ralf Baechle
+ * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05, 12 by Ralf Baechle
  * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc.
  */
 #include <linux/interrupt.h>
@@ -35,6 +35,12 @@ EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(kernel_thread);
 
 /*
+ * Functions that operate on entire pages.  Mostly used by memory management.
+ */
+EXPORT_SYMBOL(clear_page);
+EXPORT_SYMBOL(copy_page);
+
+/*
  * Userspace access stuff.
  */
 EXPORT_SYMBOL(__copy_user);
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index ce89c8061708..0441f54b2a6a 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -31,7 +31,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti)
+ *                     struct thread_info *next_ti, int usedfpu)
  */
         .align  7
         LEAF(resume)
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index f29099b104c4..eb5e394a4650 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -162,11 +162,6 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters)
         return counters >> vpe_shift();
 }
 
-static unsigned int counters_per_cpu_to_total(unsigned int counters)
-{
-        return counters << vpe_shift();
-}
-
 #else /* !CONFIG_MIPS_MT_SMP */
 #define vpe_id()        0
 
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 293898391e67..9c51be5a163a 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -43,7 +43,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti) )
+ *                     struct thread_info *next_ti, int usedfpu)
  */
 LEAF(resume)
         mfc0    t1, CP0_STATUS
@@ -51,18 +51,9 @@ LEAF(resume)
         cpu_save_nonscratch a0
         sw      ra, THREAD_REG31(a0)
 
-        /*
-         * check if we need to save FPU registers
-         */
-        lw      t3, TASK_THREAD_INFO(a0)
-        lw      t0, TI_FLAGS(t3)
-        li      t1, _TIF_USEDFPU
-        and     t2, t0, t1
-        beqz    t2, 1f
-        nor     t1, zero, t1
+        beqz    a3, 1f
 
-        and     t0, t0, t1
-        sw      t0, TI_FLAGS(t3)
+        PTR_L   t3, TASK_THREAD_INFO(a0)
 
         /*
          * clear saved user stack CU1 bit
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 9414f9354469..42d2a3938420 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -41,7 +41,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti)
+ *                     struct thread_info *next_ti, int usedfpu)
  */
         .align  5
         LEAF(resume)
@@ -53,16 +53,10 @@
         /*
          * check if we need to save FPU registers
          */
-        PTR_L   t3, TASK_THREAD_INFO(a0)
-        LONG_L  t0, TI_FLAGS(t3)
-        li      t1, _TIF_USEDFPU
-        and     t2, t0, t1
-        beqz    t2, 1f
-        nor     t1, zero, t1
 
-        and     t0, t0, t1
-        LONG_S  t0, TI_FLAGS(t3)
+        beqz    a3, 1f
 
+        PTR_L   t3, TASK_THREAD_INFO(a0)
         /*
          * clear saved user stack CU1 bit
          */
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 3046e2986006..8e393b8443f7 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -15,7 +15,6 @@
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
-#include <linux/init.h>
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
 #include <linux/reboot.h>
@@ -197,13 +196,6 @@ static void bmips_init_secondary(void)
 
         write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 #endif
-
-        /* make sure there won't be a timer interrupt for a little while */
-        write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
-
-        irq_enable_hazard();
-        set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
-        irq_enable_hazard();
 }
 
 /*
@@ -212,6 +204,13 @@ static void bmips_init_secondary(void)
 static void bmips_smp_finish(void)
 {
         pr_info("SMP: CPU%d is running\n", smp_processor_id());
+
+        /* make sure there won't be a timer interrupt for a little while */
+        write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+
+        irq_enable_hazard();
+        set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
+        irq_enable_hazard();
 }
 
 /*
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 48650c818040..1268392f1d27 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -122,13 +122,21 @@ asmlinkage __cpuinit void start_secondary(void)
 
         notify_cpu_starting(cpu);
 
-        mp_ops->smp_finish();
+        set_cpu_online(cpu, true);
+
         set_cpu_sibling_map(cpu);
 
         cpu_set(cpu, cpu_callin_map);
 
         synchronise_count_slave();
 
+        /*
+         * irq will be enabled in ->smp_finish(), enabling it too early
+         * is dangerous.
+         */
+        WARN_ON_ONCE(!irqs_disabled());
+        mp_ops->smp_finish();
+
         cpu_idle();
 }
 
@@ -196,8 +204,6 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
         while (!cpu_isset(cpu, cpu_callin_map))
                 udelay(100);
 
-        set_cpu_online(cpu, true);
-
         return 0;
 }
 
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f5dd38f1d015..15b5f3cfd20c 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -322,7 +322,7 @@ int __init smtc_build_cpu_map(int start_cpu_slot)
 
 /*
  * Common setup before any secondaries are started
- * Make sure all CPU's are in a sensible state before we boot any of the
+ * Make sure all CPUs are in a sensible state before we boot any of the
  * secondaries.
  *
  * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
@@ -340,12 +340,12 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
         /*
          * TCContext gets an offset from the base of the IPIQ array
          * to be used in low-level code to detect the presence of
-         * an active IPI queue
+         * an active IPI queue.
          */
         write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
         /* Bind tc to vpe */
         write_tc_c0_tcbind(vpe);
-        /* In general, all TCs should have the same cpu_data indications */
+        /* In general, all TCs should have the same cpu_data indications. */
         memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
         /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
         if (cpu_data[0].cputype == CPU_34K ||
@@ -358,8 +358,8 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
 }
 
 /*
- * Tweak to get Count registes in as close a sync as possible.
- * Value seems good for 34K-class cores.
+ * Tweak to get Count registes in as close a sync as possible.  The
+ * value seems good for 34K-class cores.
  */
 
 #define CP0_SKEW 8
@@ -615,7 +615,6 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
 
 void smtc_init_secondary(void)
 {
-        local_irq_enable();
 }
 
 void smtc_smp_finish(void)
@@ -631,6 +630,8 @@ void smtc_smp_finish(void)
         if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
                 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
 
+        local_irq_enable();
+
         printk("TC %d going on-line as CPU %d\n",
                 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
 }
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 99f913c8d7a6..842d55e411fd 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -111,7 +111,6 @@ void __cpuinit synchronise_count_master(void)
 void __cpuinit synchronise_count_slave(void)
 {
         int i;
-        unsigned long flags;
         unsigned int initcount;
         int ncpus;
 
@@ -123,8 +122,6 @@ void __cpuinit synchronise_count_slave(void)
         return;
 #endif
 
-        local_irq_save(flags);
-
         /*
          * Not every cpu is online at the time this gets called,
          * so we first wait for the master to say everyone is ready
@@ -154,7 +151,5 @@ void __cpuinit synchronise_count_slave(void)
         }
         /* Arrange for an interrupt in a short while */
         write_c0_compare(read_c0_count() + COUNTON);
-
-        local_irq_restore(flags);
 }
 #undef NR_LOOPS
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 2d0c2a277f52..c3c293543703 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -132,6 +132,9 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
         unsigned long ra = regs->regs[31];
         unsigned long pc = regs->cp0_epc;
 
+        if (!task)
+                task = current;
+
         if (raw_show_trace || !__kernel_text_address(pc)) {
                 show_raw_backtrace(sp);
                 return;
@@ -1249,6 +1252,7 @@ static inline void parity_protection_init(void)
                 break;
 
         case CPU_5KC:
+        case CPU_5KE:
                 write_c0_ecc(0x80000000);
                 back_to_back_c0_hazard();
                 /* Set the PE bit (bit 31) in the c0_errctl register. */
@@ -1498,6 +1502,7 @@ extern void flush_tlb_handlers(void);
  * Timer interrupt
  */
 int cp0_compare_irq;
+EXPORT_SYMBOL_GPL(cp0_compare_irq);
 int cp0_compare_irq_shift;
 
 /*
@@ -1597,7 +1602,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
                         cp0_perfcount_irq = -1;
         } else {
                 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
-                cp0_compare_irq_shift = cp0_compare_irq;
+                cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
                 cp0_perfcount_irq = -1;
         }
 
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 924da5eb7031..df243a64f430 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -1,5 +1,6 @@
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
+#include <asm/thread_info.h>
 #include <asm-generic/vmlinux.lds.h>
 
 #undef mips
@@ -72,7 +73,7 @@ SECTIONS
         .data : {       /* Data */
                 . = . + DATAOFFSET;             /* for CONFIG_MAPPED_KERNEL */
 
-                INIT_TASK_DATA(PAGE_SIZE)
+                INIT_TASK_DATA(THREAD_SIZE)
                 NOSAVE_DATA
                 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
                 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)