1 files changed, 29 insertions, 9 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index fcae66752972..984c0d0a7b4d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -534,8 +534,7 @@ static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 
 /*
  * Simulate trapping 'rdhwr' instructions to provide user accessible
- * registers not implemented in hardware.  The only current use of this
- * is the thread area pointer.
+ * registers not implemented in hardware.
  */
 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 {
@@ -545,11 +544,31 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
                 int rd = (opcode & RD) >> 11;
                 int rt = (opcode & RT) >> 16;
                 switch (rd) {
-                        case 29:
-                                regs->regs[rt] = ti->tp_value;
-                                return 0;
+                case 0:         /* CPU number */
+                        regs->regs[rt] = smp_processor_id();
+                        return 0;
+                case 1:         /* SYNCI length */
+                        regs->regs[rt] = min(current_cpu_data.dcache.linesz,
+                                             current_cpu_data.icache.linesz);
+                        return 0;
+                case 2:         /* Read count register */
+                        regs->regs[rt] = read_c0_count();
+                        return 0;
+                case 3:         /* Count register resolution */
+                        switch (current_cpu_data.cputype) {
+                        case CPU_20KC:
+                        case CPU_25KF:
+                                regs->regs[rt] = 1;
+                                break;
                         default:
-                                return -1;
+                                regs->regs[rt] = 2;
+                        }
+                        return 0;
+                case 29:
+                        regs->regs[rt] = ti->tp_value;
+                        return 0;
+                default:
+                        return -1;
                 }
         }
 
@@ -1287,7 +1306,7 @@ int cp0_compare_irq;
 int cp0_perfcount_irq;
 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
 
-void __init per_cpu_trap_init(void)
+void __cpuinit per_cpu_trap_init(void)
 {
         unsigned int cpu = smp_processor_id();
         unsigned int status_set = ST0_CU0;
@@ -1404,11 +1423,12 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size)
         flush_icache_range(ebase + offset, ebase + offset + size);
 }
 
-static char panic_null_cerr[] __initdata =
+static char panic_null_cerr[] __cpuinitdata =
         "Trying to set NULL cache error exception handler";
 
 /* Install uncached CPU exception handler */
-void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
+void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
+        unsigned long size)
 {
 #ifdef CONFIG_32BIT
         unsigned long uncached_ebase = KSEG1ADDR(ebase);