diff options
Diffstat (limited to 'arch/mips/kernel/smp-bmips.c')
-rw-r--r-- | arch/mips/kernel/smp-bmips.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 159abc8842d2..126da74d4c55 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c | |||
@@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void) | |||
66 | int i, cpu = 1, boot_cpu = 0; | 66 | int i, cpu = 1, boot_cpu = 0; |
67 | 67 | ||
68 | #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) | 68 | #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) |
69 | int cpu_hw_intr; | ||
70 | |||
69 | /* arbitration priority */ | 71 | /* arbitration priority */ |
70 | clear_c0_brcm_cmt_ctrl(0x30); | 72 | clear_c0_brcm_cmt_ctrl(0x30); |
71 | 73 | ||
@@ -80,8 +82,12 @@ static void __init bmips_smp_setup(void) | |||
80 | * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output | 82 | * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output |
81 | * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output | 83 | * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output |
82 | */ | 84 | */ |
83 | change_c0_brcm_cmt_intr(0xf8018000, | 85 | if (boot_cpu == 0) |
84 | (0x02 << 27) | (0x03 << 15)); | 86 | cpu_hw_intr = 0x02; |
87 | else | ||
88 | cpu_hw_intr = 0x1d; | ||
89 | |||
90 | change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15)); | ||
85 | 91 | ||
86 | /* single core, 2 threads (2 pipelines) */ | 92 | /* single core, 2 threads (2 pipelines) */ |
87 | max_cpus = 2; | 93 | max_cpus = 2; |