1 files changed, 72 insertions, 8 deletions

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 24cdf64789c3..4f2d9dece7ab 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -805,7 +805,7 @@ static void reset_counters(void *arg)
         }
 }
 
-/* 24K/34K/1004K cores can share the same event map. */
+/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
 static const struct mips_perf_event mipsxxcore_event_map
                                 [PERF_COUNT_HW_MAX] = {
         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
@@ -814,8 +814,8 @@ static const struct mips_perf_event mipsxxcore_event_map
         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 };
 
-/* 74K core has different branch event code. */
-static const struct mips_perf_event mipsxx74Kcore_event_map
+/* 74K/proAptiv core has different branch event code. */
+static const struct mips_perf_event mipsxxcore_event_map2
                                 [PERF_COUNT_HW_MAX] = {
         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
@@ -849,7 +849,7 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
 };
 
-/* 24K/34K/1004K cores can share the same cache event map. */
+/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
 static const struct mips_perf_event mipsxxcore_cache_map
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -930,8 +930,8 @@ static const struct mips_perf_event mipsxxcore_cache_map
 },
 };
 
-/* 74K core has completely different cache event map. */
-static const struct mips_perf_event mipsxx74Kcore_cache_map
+/* 74K/proAptiv core has completely different cache event map. */
+static const struct mips_perf_event mipsxxcore_cache_map2
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -978,6 +978,11 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
                 [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN, P },
         },
 },
+/*
+ * 74K core does not have specific DTLB events. proAptiv core has
+ * "speculative" DTLB events which are numbered 0x63 (even/odd) and
+ * not included here. One can use raw events if really needed.
+ */
 [C(ITLB)] = {
         [C(OP_READ)] = {
                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
@@ -1378,6 +1383,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 #define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
         ((b) == 0 || (b) == 1)
 
+/* proAptiv */
+#define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b)                              \
+        ((b) == 0 || (b) == 1)
+
 /* 1004K */
 #define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
         ((b) == 0 || (b) == 1 || (b) == 11)
@@ -1391,6 +1400,20 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 #define IS_RANGE_V_1004K_EVENT(r)       ((r) == 47)
 #endif
 
+/* interAptiv */
+#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b)                            \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
+#define IS_RANGE_P_INTERAPTIV_EVENT(r, b)                               \
+        ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
+         (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 ||            \
+         (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 &&         \
+         (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 ||          \
+         ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_INTERAPTIV_EVENT(r)  ((r) == 47 || (r) == 175)
+#endif
+
 /* BMIPS5000 */
 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b)                             \
         ((b) == 0 || (b) == 1)
@@ -1442,6 +1465,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                 break;
         case CPU_74K:
+        case CPU_1074K:
                 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
                 else
@@ -1451,6 +1475,16 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
                 raw_event.range = P;
 #endif
                 break;
+        case CPU_PROAPTIV:
+                if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                raw_event.range = P;
+#endif
+                break;
         case CPU_1004K:
                 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
@@ -1466,6 +1500,21 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
                         raw_event.range = T;
 #endif
                 break;
+        case CPU_INTERAPTIV:
+                if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
+                        raw_event.range = P;
+                else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
+                        raw_event.range = V;
+                else
+                        raw_event.range = T;
+#endif
+                break;
         case CPU_BMIPS5000:
                 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
@@ -1576,14 +1625,29 @@ init_hw_perf_events(void)
                 break;
         case CPU_74K:
                 mipspmu.name = "mips/74K";
-                mipspmu.general_event_map = &mipsxx74Kcore_event_map;
-                mipspmu.cache_event_map = &mipsxx74Kcore_cache_map;
+                mipspmu.general_event_map = &mipsxxcore_event_map2;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map2;
+                break;
+        case CPU_PROAPTIV:
+                mipspmu.name = "mips/proAptiv";
+                mipspmu.general_event_map = &mipsxxcore_event_map2;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map2;
                 break;
         case CPU_1004K:
                 mipspmu.name = "mips/1004K";
                 mipspmu.general_event_map = &mipsxxcore_event_map;
                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
                 break;
+        case CPU_1074K:
+                mipspmu.name = "mips/1074K";
+                mipspmu.general_event_map = &mipsxxcore_event_map;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map;
+                break;
+        case CPU_INTERAPTIV:
+                mipspmu.name = "mips/interAptiv";
+                mipspmu.general_event_map = &mipsxxcore_event_map;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map;
+                break;
         case CPU_LOONGSON1:
                 mipspmu.name = "mips/loongson1";
                 mipspmu.general_event_map = &mipsxxcore_event_map;