1 files changed, 82 insertions, 0 deletions

diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 0c2e853c3db4..0ea75c244b48 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -16,6 +16,7 @@
 #include <linux/suspend.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
+#include <asm/smp-cps.h>
 
 #include <linux/kvm_host.h>
 
@@ -168,6 +169,72 @@ void output_thread_fpu_defines(void)
         OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
         OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
 
+        /* the least significant 64 bits of each FP register */
+        OFFSET(THREAD_FPR0_LS64, task_struct,
+               thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR1_LS64, task_struct,
+               thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR2_LS64, task_struct,
+               thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR3_LS64, task_struct,
+               thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR4_LS64, task_struct,
+               thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR5_LS64, task_struct,
+               thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR6_LS64, task_struct,
+               thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR7_LS64, task_struct,
+               thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR8_LS64, task_struct,
+               thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR9_LS64, task_struct,
+               thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR10_LS64, task_struct,
+               thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR11_LS64, task_struct,
+               thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR12_LS64, task_struct,
+               thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR13_LS64, task_struct,
+               thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR14_LS64, task_struct,
+               thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR15_LS64, task_struct,
+               thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR16_LS64, task_struct,
+               thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR17_LS64, task_struct,
+               thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR18_LS64, task_struct,
+               thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR19_LS64, task_struct,
+               thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR20_LS64, task_struct,
+               thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR21_LS64, task_struct,
+               thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR22_LS64, task_struct,
+               thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR23_LS64, task_struct,
+               thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR24_LS64, task_struct,
+               thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR25_LS64, task_struct,
+               thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR26_LS64, task_struct,
+               thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR27_LS64, task_struct,
+               thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR28_LS64, task_struct,
+               thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR29_LS64, task_struct,
+               thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR30_LS64, task_struct,
+               thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR31_LS64, task_struct,
+               thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);
+
         OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
         BLANK();
 }
@@ -228,6 +295,7 @@ void output_sc_defines(void)
         OFFSET(SC_LO2, sigcontext, sc_lo2);
         OFFSET(SC_HI3, sigcontext, sc_hi3);
         OFFSET(SC_LO3, sigcontext, sc_lo3);
+        OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
         BLANK();
 }
 #endif
@@ -242,6 +310,7 @@ void output_sc_defines(void)
         OFFSET(SC_MDLO, sigcontext, sc_mdlo);
         OFFSET(SC_PC, sigcontext, sc_pc);
         OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
+        OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
         BLANK();
 }
 #endif
@@ -253,6 +322,7 @@ void output_sc32_defines(void)
         OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
         OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
         OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
+        OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
         BLANK();
 }
 #endif
@@ -397,3 +467,15 @@ void output_kvm_defines(void)
         OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
         BLANK();
 }
+
+#ifdef CONFIG_MIPS_CPS
+void output_cps_defines(void)
+{
+        COMMENT(" MIPS CPS offsets. ");
+        OFFSET(BOOTCFG_CORE, boot_config, core);
+        OFFSET(BOOTCFG_VPE, boot_config, vpe);
+        OFFSET(BOOTCFG_PC, boot_config, pc);
+        OFFSET(BOOTCFG_SP, boot_config, sp);
+        OFFSET(BOOTCFG_GP, boot_config, gp);
+}
+#endif