aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/jmr3927/rbhma3100/irq.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/jmr3927/rbhma3100/irq.c')
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c312
1 files changed, 33 insertions, 279 deletions
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 7d2c203cb406..1187b44a3dd4 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -30,53 +30,21 @@
30 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */ 31 */
32#include <linux/init.h> 32#include <linux/init.h>
33
34#include <linux/errno.h>
35#include <linux/irq.h>
36#include <linux/kernel_stat.h>
37#include <linux/signal.h>
38#include <linux/sched.h> 33#include <linux/sched.h>
39#include <linux/types.h> 34#include <linux/types.h>
40#include <linux/interrupt.h> 35#include <linux/interrupt.h>
41#include <linux/ioport.h>
42#include <linux/timex.h>
43#include <linux/slab.h>
44#include <linux/random.h>
45#include <linux/smp.h>
46#include <linux/smp_lock.h>
47#include <linux/bitops.h>
48 36
49#include <asm/irq_regs.h>
50#include <asm/io.h> 37#include <asm/io.h>
51#include <asm/mipsregs.h> 38#include <asm/mipsregs.h>
52#include <asm/system.h> 39#include <asm/system.h>
53 40
54#include <asm/ptrace.h>
55#include <asm/processor.h> 41#include <asm/processor.h>
56#include <asm/jmr3927/irq.h>
57#include <asm/debug.h>
58#include <asm/jmr3927/jmr3927.h> 42#include <asm/jmr3927/jmr3927.h>
59 43
60#if JMR3927_IRQ_END > NR_IRQS 44#if JMR3927_IRQ_END > NR_IRQS
61#error JMR3927_IRQ_END > NR_IRQS 45#error JMR3927_IRQ_END > NR_IRQS
62#endif 46#endif
63 47
64struct tb_irq_space* tb_irq_spaces;
65
66static int jmr3927_irq_base = -1;
67
68#ifdef CONFIG_PCI
69static int jmr3927_gen_iack(void)
70{
71 /* generate ACK cycle */
72#ifdef __BIG_ENDIAN
73 return (tx3927_pcicptr->iiadp >> 24) & 0xff;
74#else
75 return tx3927_pcicptr->iiadp & 0xff;
76#endif
77}
78#endif
79
80#define irc_dlevel 0 48#define irc_dlevel 0
81#define irc_elevel 1 49#define irc_elevel 1
82 50
@@ -87,89 +55,24 @@ static unsigned char irc_level[TX3927_NUM_IR] = {
87 6, 6, 6 /* TMR */ 55 6, 6, 6 /* TMR */
88}; 56};
89 57
90static void jmr3927_irq_disable(unsigned int irq_nr);
91static void jmr3927_irq_enable(unsigned int irq_nr);
92
93static void jmr3927_irq_ack(unsigned int irq)
94{
95 if (irq == JMR3927_IRQ_IRC_TMR0)
96 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
97
98 jmr3927_irq_disable(irq);
99}
100
101static void jmr3927_irq_end(unsigned int irq)
102{
103 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
104 jmr3927_irq_enable(irq);
105}
106
107static void jmr3927_irq_disable(unsigned int irq_nr)
108{
109 struct tb_irq_space* sp;
110
111 for (sp = tb_irq_spaces; sp; sp = sp->next) {
112 if (sp->start_irqno <= irq_nr &&
113 irq_nr < sp->start_irqno + sp->nr_irqs) {
114 if (sp->mask_func)
115 sp->mask_func(irq_nr - sp->start_irqno,
116 sp->space_id);
117 break;
118 }
119 }
120}
121
122static void jmr3927_irq_enable(unsigned int irq_nr)
123{
124 struct tb_irq_space* sp;
125
126 for (sp = tb_irq_spaces; sp; sp = sp->next) {
127 if (sp->start_irqno <= irq_nr &&
128 irq_nr < sp->start_irqno + sp->nr_irqs) {
129 if (sp->unmask_func)
130 sp->unmask_func(irq_nr - sp->start_irqno,
131 sp->space_id);
132 break;
133 }
134 }
135}
136
137/* 58/*
138 * CP0_STATUS is a thread's resource (saved/restored on context switch). 59 * CP0_STATUS is a thread's resource (saved/restored on context switch).
139 * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers. 60 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
140 */ 61 */
141static void mask_irq_isac(int irq_nr, int space_id) 62static void mask_irq_ioc(unsigned int irq)
142{
143 /* 0: mask */
144 unsigned char imask =
145 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
146 unsigned int bit = 1 << irq_nr;
147 jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
148 /* flush write buffer */
149 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
150}
151static void unmask_irq_isac(int irq_nr, int space_id)
152{
153 /* 0: mask */
154 unsigned char imask = jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
155 unsigned int bit = 1 << irq_nr;
156 jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
157 /* flush write buffer */
158 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
159}
160
161static void mask_irq_ioc(int irq_nr, int space_id)
162{ 63{
163 /* 0: mask */ 64 /* 0: mask */
65 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
164 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); 66 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
165 unsigned int bit = 1 << irq_nr; 67 unsigned int bit = 1 << irq_nr;
166 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); 68 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
167 /* flush write buffer */ 69 /* flush write buffer */
168 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); 70 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
169} 71}
170static void unmask_irq_ioc(int irq_nr, int space_id) 72static void unmask_irq_ioc(unsigned int irq)
171{ 73{
172 /* 0: mask */ 74 /* 0: mask */
75 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
173 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); 76 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
174 unsigned int bit = 1 << irq_nr; 77 unsigned int bit = 1 << irq_nr;
175 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); 78 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
@@ -177,8 +80,9 @@ static void unmask_irq_ioc(int irq_nr, int space_id)
177 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); 80 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
178} 81}
179 82
180static void mask_irq_irc(int irq_nr, int space_id) 83static void mask_irq_irc(unsigned int irq)
181{ 84{
85 unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
182 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2]; 86 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
183 if (irq_nr & 1) 87 if (irq_nr & 1)
184 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8); 88 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
@@ -191,8 +95,9 @@ static void mask_irq_irc(int irq_nr, int space_id)
191 (void)tx3927_ircptr->ssr; 95 (void)tx3927_ircptr->ssr;
192} 96}
193 97
194static void unmask_irq_irc(int irq_nr, int space_id) 98static void unmask_irq_irc(unsigned int irq)
195{ 99{
100 unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
196 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2]; 101 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
197 if (irq_nr & 1) 102 if (irq_nr & 1)
198 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8); 103 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
@@ -203,98 +108,14 @@ static void unmask_irq_irc(int irq_nr, int space_id)
203 tx3927_ircptr->imr = irc_elevel; 108 tx3927_ircptr->imr = irc_elevel;
204} 109}
205 110
206struct tb_irq_space jmr3927_isac_irqspace = {
207 .next = NULL,
208 .start_irqno = JMR3927_IRQ_ISAC,
209 nr_irqs : JMR3927_NR_IRQ_ISAC,
210 .mask_func = mask_irq_isac,
211 .unmask_func = unmask_irq_isac,
212 .name = "ISAC",
213 .space_id = 0,
214 can_share : 0
215};
216struct tb_irq_space jmr3927_ioc_irqspace = {
217 .next = NULL,
218 .start_irqno = JMR3927_IRQ_IOC,
219 nr_irqs : JMR3927_NR_IRQ_IOC,
220 .mask_func = mask_irq_ioc,
221 .unmask_func = unmask_irq_ioc,
222 .name = "IOC",
223 .space_id = 0,
224 can_share : 1
225};
226
227struct tb_irq_space jmr3927_irc_irqspace = {
228 .next = NULL,
229 .start_irqno = JMR3927_IRQ_IRC,
230 .nr_irqs = JMR3927_NR_IRQ_IRC,
231 .mask_func = mask_irq_irc,
232 .unmask_func = unmask_irq_irc,
233 .name = "on-chip",
234 .space_id = 0,
235 .can_share = 0
236};
237
238
239#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
240static int tx_branch_likely_bug_count = 0;
241static int have_tx_branch_likely_bug = 0;
242
243static void tx_branch_likely_bug_fixup(void)
244{
245 struct pt_regs *regs = get_irq_regs();
246
247 /* TX39/49-BUG: Under this condition, the insn in delay slot
248 of the branch likely insn is executed (not nullified) even
249 the branch condition is false. */
250 if (!have_tx_branch_likely_bug)
251 return;
252 if ((regs->cp0_epc & 0xfff) == 0xffc &&
253 KSEGX(regs->cp0_epc) != KSEG0 &&
254 KSEGX(regs->cp0_epc) != KSEG1) {
255 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
256 /* beql,bnel,blezl,bgtzl */
257 /* bltzl,bgezl,blezall,bgezall */
258 /* bczfl, bcztl */
259 if ((insn & 0xf0000000) == 0x50000000 ||
260 (insn & 0xfc0e0000) == 0x04020000 ||
261 (insn & 0xf3fe0000) == 0x41020000) {
262 regs->cp0_epc -= 4;
263 tx_branch_likely_bug_count++;
264 printk(KERN_INFO
265 "fix branch-likery bug in %s (insn %08x)\n",
266 current->comm, insn);
267 }
268 }
269}
270#endif
271
272static void jmr3927_spurious(void)
273{
274 struct pt_regs * regs = get_irq_regs();
275
276#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
277 tx_branch_likely_bug_fixup();
278#endif
279 printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
280 regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
281}
282
283asmlinkage void plat_irq_dispatch(void) 111asmlinkage void plat_irq_dispatch(void)
284{ 112{
285 struct pt_regs * regs = get_irq_regs(); 113 unsigned long cp0_cause = read_c0_cause();
286 int irq; 114 int irq;
287 115
288#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND 116 if ((cp0_cause & CAUSEF_IP7) == 0)
289 tx_branch_likely_bug_fixup();
290#endif
291 if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
292#if 0
293 jmr3927_spurious();
294#endif
295 return; 117 return;
296 } 118 irq = (cp0_cause >> CAUSEB_IP2) & 0x0f;
297 irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
298 119
299 do_IRQ(irq + JMR3927_IRQ_IRC); 120 do_IRQ(irq + JMR3927_IRQ_IRC);
300} 121}
@@ -317,35 +138,6 @@ static struct irqaction ioc_action = {
317 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL, 138 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
318}; 139};
319 140
320static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id)
321{
322 unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
323 int i;
324
325 for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
326 if (istat & (1 << i)) {
327 irq = JMR3927_IRQ_ISAC + i;
328 do_IRQ(irq);
329 }
330 }
331 return IRQ_HANDLED;
332}
333
334static struct irqaction isac_action = {
335 jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
336};
337
338
339static irqreturn_t jmr3927_isaerr_interrupt(int irq, void *dev_id)
340{
341 printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
342
343 return IRQ_HANDLED;
344}
345static struct irqaction isaerr_action = {
346 jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
347};
348
349static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) 141static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
350{ 142{
351 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); 143 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
@@ -358,54 +150,19 @@ static struct irqaction pcierr_action = {
358 jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL, 150 jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
359}; 151};
360 152
361int jmr3927_ether1_irq = 0; 153static void __init jmr3927_irq_init(void);
362
363void jmr3927_irq_init(u32 irq_base);
364 154
365void __init arch_init_irq(void) 155void __init arch_init_irq(void)
366{ 156{
367 /* look for io board's presence */
368 int have_isac = jmr3927_have_isac();
369
370 /* Now, interrupt control disabled, */ 157 /* Now, interrupt control disabled, */
371 /* all IRC interrupts are masked, */ 158 /* all IRC interrupts are masked, */
372 /* all IRC interrupt mode are Low Active. */ 159 /* all IRC interrupt mode are Low Active. */
373 160
374 if (have_isac) {
375
376 /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
377 /* temporary enable interrupt control */
378 tx3927_ircptr->cer = 1;
379 /* ETHER1 Int. Is High-Active. */
380 if (tx3927_ircptr->ssr & (1 << 0))
381 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
382#if 0 /* INT3 may be asserted by ether0 (even after reboot...) */
383 else if (tx3927_ircptr->ssr & (1 << 3))
384 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
385#endif
386 /* disable interrupt control */
387 tx3927_ircptr->cer = 0;
388
389 /* Ether1: High Active */
390 if (jmr3927_ether1_irq) {
391 int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
392 tx3927_ircptr->cr[ether1_irc / 8] |=
393 TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
394 }
395 }
396
397 /* mask all IOC interrupts */ 161 /* mask all IOC interrupts */
398 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); 162 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
399 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ 163 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
400 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); 164 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
401 165
402 if (have_isac) {
403 /* mask all ISAC interrupts */
404 jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
405 /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
406 jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
407 }
408
409 /* clear PCI Soft interrupts */ 166 /* clear PCI Soft interrupts */
410 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); 167 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
411 /* clear PCI Reset interrupts */ 168 /* clear PCI Reset interrupts */
@@ -415,21 +172,11 @@ void __init arch_init_irq(void)
415 tx3927_ircptr->cer = TX3927_IRCER_ICE; 172 tx3927_ircptr->cer = TX3927_IRCER_ICE;
416 tx3927_ircptr->imr = irc_elevel; 173 tx3927_ircptr->imr = irc_elevel;
417 174
418 jmr3927_irq_init(NR_ISA_IRQS); 175 jmr3927_irq_init();
419
420 /* setup irq space */
421 add_tb_irq_space(&jmr3927_isac_irqspace);
422 add_tb_irq_space(&jmr3927_ioc_irqspace);
423 add_tb_irq_space(&jmr3927_irc_irqspace);
424 176
425 /* setup IOC interrupt 1 (PCI, MODEM) */ 177 /* setup IOC interrupt 1 (PCI, MODEM) */
426 setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); 178 setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
427 179
428 if (have_isac) {
429 setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
430 setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
431 }
432
433#ifdef CONFIG_PCI 180#ifdef CONFIG_PCI
434 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); 181 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
435#endif 182#endif
@@ -438,21 +185,28 @@ void __init arch_init_irq(void)
438 set_c0_status(ST0_IM); /* IE bit is still 0. */ 185 set_c0_status(ST0_IM); /* IE bit is still 0. */
439} 186}
440 187
441static struct irq_chip jmr3927_irq_controller = { 188static struct irq_chip jmr3927_irq_ioc = {
442 .name = "jmr3927_irq", 189 .name = "jmr3927_ioc",
443 .ack = jmr3927_irq_ack, 190 .ack = mask_irq_ioc,
444 .mask = jmr3927_irq_disable, 191 .mask = mask_irq_ioc,
445 .mask_ack = jmr3927_irq_ack, 192 .mask_ack = mask_irq_ioc,
446 .unmask = jmr3927_irq_enable, 193 .unmask = unmask_irq_ioc,
447 .end = jmr3927_irq_end,
448}; 194};
449 195
450void jmr3927_irq_init(u32 irq_base) 196static struct irq_chip jmr3927_irq_irc = {
197 .name = "jmr3927_irc",
198 .ack = mask_irq_irc,
199 .mask = mask_irq_irc,
200 .mask_ack = mask_irq_irc,
201 .unmask = unmask_irq_irc,
202};
203
204static void __init jmr3927_irq_init(void)
451{ 205{
452 u32 i; 206 u32 i;
453 207
454 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) 208 for (i = JMR3927_IRQ_IRC; i < JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC; i++)
455 set_irq_chip(i, &jmr3927_irq_controller); 209 set_irq_chip_and_handler(i, &jmr3927_irq_irc, handle_level_irq);
456 210 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
457 jmr3927_irq_base = irq_base; 211 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
458} 212}